119 results about "Arithmetic computation" patented technology

Certain examples described herein relate to at least a cryptographic system and a method of operating a cryptographic system. The cryptographic system may be implemented as a co-processor for performing post-quantum cryptographic functions. The cryptographic system has a set of bus interfaces for coupling to an external computing system, a cryptographic math unit and a control unit. The cryptographic math unit in certain examples is adapted to provide one or more masked modes of operation that secure the cryptographic operations against side-channel and non-invasive attacks. The method of operating a cryptographic system involves annotating secret data and tracking those annotations through one or more arithmetic operations.

To provide an instruction execution device configured to implement high computational throughput and energy efficiency, a method, electronic equipment, and a storage medium.SOLUTION: An instruction execution device 100 includes: a dispatching unit configured to respond to determining that at least one source register used for an instruction to be executed corresponds to at least one uniform register in a plurality of uniform registers, the instruction to be executed serving as a uniform instruction including a plurality of uniform computing operations to be dispatched to a first computing unit; and the first computing unit configured to execute uniform calculation operation to obtain a uniform calculation result, the uniform calculation result being written into at least one available uniform register in the plurality of uniform registers.SELECTED DRAWING: Figure 1

An adder tree can be formed for efficient packing of arithmetic units into an integrated circuit. The operands of the tree can be truncated to pack an integer number of nodes in a logic array block. Thus, arithmetic operations can be more efficiently packed onto the integrated circuit, and increased precision and performance are provided.

A recording medium storing a program for causing a computer to execute: determining a number of control qubits using a relationship between a first arithmetic operation time for each of multiple kinds of modular exponentiation calculation processing in an arithmetic operation of prime factorization and a second arithmetic operation time for each of a plurality of measurement and classical conditional arithmetic operations in inverse quantum Fourier transform processing on results of the multiple kinds of modular exponentiation calculation processing in the arithmetic operation of the prime factorization; determining a circuit pattern for performing the arithmetic operation of the prime factorization by executing the multiple kinds of modular exponentiation calculation processing and the inverse quantum Fourier transform processing, based on the number of control qubits; generating a quantum circuit using the circuit pattern; and performing the arithmetic operation of the prime factorization by using the quantum circuit.

[Problem] To provide a quantum circuit that performs arithmetic operations for changing propositions by making the flow of positive calculations reversible. [Solution] A quantum circuit used in a quantum computer, the quantum circuit being characterized in that an inverse-function space is generated with a function obtained from an intersection of an arbitrary string and a rev function as an axis, and the inverse-function space is used for calculation.

The invention relates to a method and an apparatus for executing Structural Query Language (SQL) instructions in a Solid-state Storage Device (SSD). The apparatus includes: a processing unit; and a database accelerator. The processing unit is arranged operably to obtain an SQL query from a host side. The database accelerator is arranged operably to parse the SQL query according an SQL syntax tree to generate a series of table tasks to execute; and during the execution of the table tasks, read tables from a flash module through the processing unit, generate intermediate tables and sub-tables based on the read tables, and perform an arithmetic computation, a logical computation or both on a specific field in one intermediate table to generate a final dataset. The processing unit is arranged operably to reply to the host side with the final dataset.

An arithmetic operator includes: multiple arithmetic elements each serving as a programmable circuit capable of programming a logical function; and a data bus that connects two or more of the multiple arithmetic elements and that transmits transmission data. The transmission data includes first data used in one of the two or more arithmetic elements and second data used to reconfigure a logical function of any one of the two or more arithmetic elements, the transmission data destined for each of the two or more arithmetic elements on the same data bus is collectively transmitted on the same data bus at a cycle different with each of the two or more arithmetic elements, and each arithmetic elements receives the first data and the second data for own arithmetic element by extracting the transmission data destined for the own arithmetic element at a cycle associated with the own arithmetic element.

The present application relates to trailing or leading digit predictors. A method and a leading zero predictor for estimating the number of leading zeros in the result of a fixed-point arithmetic operation, accurate to within one bit of any signed fixed-point number. The leading zero predictor comprises an input encoding circuit that generates an encoded input string from the fixed-point number; a window-based proxy string generation circuit that generates a proxy string by examining successive windows of the encoded input string and setting corresponding bits of the proxy string based on the examination, the leading ones of the proxy string being an estimate of the leading ones in the result of the arithmetic operation; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading ones in the proxy string.

A vector processor includes a mask register configured to hold mask values, an instruction decoder configured to set dependency information included in instruction execution information when a decoded instruction is a subsequent instruction having data dependency with one or more previous instructions, and to set all-set information included in instruction execution information when a decoded instruction sets all of the mask values, a vector processing unit configured to execute vector arithmetic operations based on the instruction execution information, and to store in the data register a result of an arithmetic operation of a vector element corresponding to each mask value that is in a set state, and a dependency reset unit configured to reset the dependency information corresponding to a destination operand of the subsequent instruction and the mask register, when the all-set information is set for the mask register and the mask register is designated by the subsequent instruction.

According to the present invention, multiple parametrically encoded audio signals can be efficiently combined using an audio signal generator, which generates an audio output signal by combining the down-mix channels and the associated parameters of the audio signals directly within the parameter domain, i.e. without reconstructing or decoding the individual input audio signals prior to the generation of the audio output signal. This is achieved by direct mixing of the associated down-mix channels of the individual input signals. It is one key feature of the present invention that the combination of the down-mix channels is achieved by simple, computationally inexpensive arithmetic operations.

In a field device 10, a sensor 101 measures a given physical quantity and outputs a sensor measurement value that is a value representing the measured physical quantity, a first CPU 102 performs a given arithmetic operation and given fixed-cycle processing on the sensor measurement value and voluntarily transmits sequence information containing a result of executing the fixed-cycle processing, and a second CPU 103 determines whether the first CPU 102 has a failure by determining whether the fixed-cycle processing is executed normally based on the sequence information.

The invention discloses a data transformation method and device and a storage medium, and the method comprises the steps: obtaining first color data, second color data and third color data for a positive transformation process of a coding end, carrying out the arithmetic operation of the first color data and the second color data, obtaining first chroma data, and obtaining second chroma data; and performing arithmetic operation on the third color data and the first color data to obtain second chrominance data, and taking the third color data as brightness data. Compared with a traditional method, the conversion method only needs two times of arithmetic operation, the calculation complexity can be remarkably reduced, redundancy between channels in a color space is reduced, meanwhile, hardware resource expenditure can be effectively saved, then the average power consumption of equipment can be reduced, and the working frequency can be improved.

A novel data generation system is provided, which includes a first data processing device having a function of generating a netlist by converting a hardware description language into graph-structured data and performing arithmetic processing based on Monte Carlo tree search, a second data processing device having a function of converting the graph-structured data into matrix data using a graph neural network, and a third data processing device including a transformer model and generating a first command in accordance with an input token sequence. The first data processing device has a function of generating a random number, and as a command executed in the Monte Carlo tree search, the first command or a second command selected using a calculation formula of action selection is selected in accordance with a magnitude relationship between the random number and a specified value.

A processing system and method for executing arithmetic and conversion operations involving 16-bit brain floating-point (BF16)-formatted data are described. An instruction specifying either an arithmetic or conversion operation and a first data element in BF16 data format are received. For arithmetic operations, the exponents of the data elements are aligned, and a result is generated using the aligned exponents. For conversion operations, the mantissa of the BF16 data element is scaled based on its exponent, and the element is converted to a second data format, such as FP32 or a reduced-precision format, using precision-aware scaling and rounding. The result is stored in operations registers, such as for additional processing.

Systems, methods, and computer-readable media for (i) accelerating the inference speed of deep neural networks (DNNs) and (ii) compressing vector representations generated by DNNs from various input data (such as images, audio, video, and text). The method embodiments take a neural network architecture and a task-related loss function as input, measure the performance of the neural network on a training data set, and output a deep neural network with sparse neuron activations. The process of the present invention enhances the existing training objective function of the DNN using a regularization term, promotes sparse activations of neurons, and compresses the DNN by using various algorithms to solve optimization problems. The present disclosure also shows how to exploit sparsification of activations during DNN inference, thereby proportionally reducing the number of arithmetic operations, and how to use the sparse representations generated by the DNN to build an efficient search engine.

A hardware (HW) accelerator architecture is described that adapts to a number of post-quantum cryptography (PQC) algorithms. The architecture determines whether to re-provision memory that stores constants values for arithmetic computations used for executed PQC algorithms. The architecture enables only a single set of constants to be stored at any particular time and the memory only needs to have a capacity to ensure that the largest set of constants among one of several PQC algorithms is stored while obviating the need to store the constants used across all PQC algorithms.

The described hardware accelerator architecture (HW accelerator architecture) facilitates flexibility in adapting to a range of post-quantum cryptography (PQC) algorithms. When additional processing requests are received, the architecture determines whether memory needs to be re-fed to store constant values ​​used for arithmetic calculations performed by the PQC algorithms. Given this flexibility, only a single set of constants needs to be stored at any given time. The memory size can be reduced compared to conventional HW accelerator architectures because the memory must have a capacity sufficient to ensure that the largest set of constants is stored under any one of several PQC algorithms, without requiring the storage of constants used by all PQC algorithms.

A system and method for performing arithmetic operations on compacted data files. The system receives data queries containing arithmetic operations to be performed on compressed data. Using an estimation process, the system locates a starting position in the compacted file and refines this location by finding codeword boundaries in a reference codebook. The system then traverses the file to identify codewords corresponding to the queried data. Each codeword has associated arithmetic metadata including numeric values and data types stored in the reference codebook. The system performs arithmetic operations directly on these codewords using their metadata, without decompressing them back to their original form. Results of arithmetic operations are generated as new codewords. This approach enables mathematical computations on compressed data while maintaining the storage efficiency of data compaction.

A tensor calculation device, a data processor, a tensor calculation method and a storage medium. The tensor calculation device comprises a receiving unit, a tensor processing unit and an arithmetic processing unit; the tensor processing unit is configured to perform a first tensor calculation on a first tensor to obtain a first intermediate tensor; the tensor processing unit is further configured to obtain a virtual tensor and perform a second tensor calculation on a second tensor according to the virtual tensor to obtain a second intermediate tensor, wherein the second intermediate tensor and the second tensor have the same shape, and the numerical values of the elements at all corresponding positions of the second intermediate tensor and the second tensor have the same preset proportional relationship; and the arithmetic processing unit is configured to perform arithmetic operation processing on the second intermediate tensor and the first intermediate tensor to obtain a result tensor. The tensor calculation device does not need to load data for performing the arithmetic operation, and there is no bandwidth competition phenomenon, thereby greatly improving the overall efficiency of the operator and effectively utilizing the powerful computing power of the tensor calculation device itself.

There are provided systems and methods for reducing quantization errors, including method of optimizing a routine for a hardware-based processing system having a fixed length two's complement binary representation, the method comprising: receiving an instruction sequence arranged to perform the routine, wherein the instruction sequence comprises a set of arithmetic operations, wherein the outputs of the arithmetic operations exceed a precision of the hardware-based processing system; identifying one or more pairs of sub-sets of instructions in the sequence of instructions, the sub-sets of each pair having a respective comparable truncation error; and generating an optimized routine by modifying one of the sub-sets of each pair to invert the sign of one or more inputs to said sub-sets and modifying the instruction sequence to compensate for the said inversion.

The invention discloses a bit extraction-based zero arithmetic overhead address generation method and circuit. The method comprises the following steps of: detecting the position of a most significant bit of an input fixed-point integer to determine an interval index; directly extracting an intra-interval offset index from the input through a bit extraction operation; and splicing the interval index and the offset index bit to generate a storage address. The circuit comprises a most significant bit detection module, a bit extraction module and an address splicing module. According to the method, the mathematical characteristic of power interval division of 2 is utilized, the existing division operation is converted into simple bit extraction operation, and arithmetic operation in the address generation process is completely eliminated. Only a priority encoder, a multiplexer and bit splicing logic are needed, and no adder, multiplier or divider is included. Realization results on an FPGA show that the circuit only consumes 5-7 LUTs which are reduced by more than 90% compared with an existing method, and the circuit is particularly suitable for resource-limited embedded systems and processing application of high-throughput data streams.

Methods and related memory devices and systems for performing in-memory processing operations are described. Bit strings (e.g., vectors) may be extracted and processed in logic of a memory device without involving separate processing units. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel fashion during a single clock cycle sequence. Accordingly, the arithmetic may be performed in a single pass because two or more bit strings are extracted and have no intermediate storage of the number. Vectors may be extracted (e.g., identified, transmitted, received) from one or more bit lines. Register of the memory array may be used to write (e.g., store or temporarily store) results or auxiliary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry proximate, proximate, or underneath the memory array may employ XOR or AND (or other) logic to extract, organize, or compute the data.

The invention relates to optimization for a digital processing system. Systems and methods are provided for reducing quantization errors, including a method of optimizing a routine for a hardware-based processing system having a fixed length two complement binary representation, the method comprising: receiving a sequence of instructions arranged to execute the routine, where the sequence of instructions comprises a set of arithmetic operations, wherein the output of the arithmetic operation exceeds the precision of the hardware-based processing system; identifying one or more pairs of instruction subsets in the instruction sequence, each pair of subsets having a corresponding equivalent truncation error; an optimized routine is generated by modifying one of the subsets of each pair to reverse one or more input symbols of the subset and modifying the instruction sequence to compensate for the inversion.

The present invention addresses the problem of calculating the root of a power function. An arithmetic device according to the present invention calculates a root Y of a power function (Y = AX, wherein A is a constant, and X is a prescribed numerical range). The arithmetic device comprises: an input unit into which input data indicating an exponent X is input; a first arithmetic circuit that executes a first arithmetic process on the basis of a linear approximation equation of a graph of a power function in a first numerical region of a numerical range of the exponent X; a second arithmetic circuit that executes a second arithmetic process on the basis of a linear approximation equation of a graph of a power function in a second numerical region of the numerical range, the second numerical region differing from the first numerical region; and a selector that outputs output data indicating the root Y calculated by the first arithmetic circuit when if exponent X indicated by the input data inputted into the input unit belongs to the first numerical region, and outputs output data indicating the root Y calculated by the second arithmetic circuit if the exponent X indicated by the input data inputted into the input unit belongs to the second numerical region.

Systems, devices, and methods related to acceleration circuitry for POSIT operations are described. A first operand formatted in a common digital or POSIT format may be received by a first buffer resident on the acceleration circuitry. A second operand formatted in a common digital or POSIT format may be received by a second buffer resident on the acceleration circuitry. An arithmetic operation, a logical operation, or both may be performed using processing circuitry resident on the acceleration circuitry using the first operand and the second operand. A result of the arithmetic operation, the logical operation, or both may be received by a third buffer resident on the acceleration circuitry.

Disclosed are techniques for macro-operation fusion. In an aspect, a method for macro-operation fusion comprises detecting that a plurality of macro-operations involving a first register is a fusible set of macro-operations comprising a first macro-operation to perform an arithmetic operation using a second register and a second macro-operation to perform the arithmetic operation using an immediate value, wherein the arithmetic operation is addition or subtraction. The method also comprises decoding the fusible set to one micro-operation that performs functions of the fusible set, and executing the one micro-operation that performs the functions of the fusible set. In some aspects, the detection, decoding, and executing steps may be performed by an instruction fetch unit, a decoder unit, and an execution unit, respectively, of a processor. In some aspects, the instruction fetch unit routes the fusible set of macro-operations to the same decoder unit from a plurality of available decoder units.

There is provided an apparatus, a method, and a computer program. The apparatus is provided with a plurality of vector registers, each of the plurality of vector registers configured to store a plurality of elements. The apparatus is also provided with decoder circuitry responsive to a fused extremum instruction to generate control signals, the fused extremum instruction specifying first and second input vector registers. The apparatus is also provided with processing circuitry responsive to the control signals to perform an extremum calculation procedure comprising extracting a plurality of groups of elements comprising at least a first element extracted from the first input vector register and a second element extracted from the second input vector register. The extremum calculating procedure comprises outputting an extremum value from a plurality of arithmetic results, each generated from a respective group of elements by combining, using an arithmetic operation, the first and second elements.

Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes decoding circuitry to decode an instruction, where the instruction specifies locations of a plurality of operands, values of which being in a floating-point format. The exemplary processor further includes execution circuitry to execute the decoded instruction, where the execution includes to: convert the values for each operand, each value being converted into a plurality of lower precision values, where an exponent is to be stored for each operand; perform arithmetic operations among lower precision values converted from values for the plurality of the operands; and generate a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and store the floating-point value.

According to the present invention, multiple parametrically encoded audio signals can be efficiently combined using an audio signal generator, which generates an audio output signal by combining the down-mix channels and the associated parameters of the audio signals directly within the parameter domain, i.e. without reconstructing or decoding the individual input audio signals prior to the generation of the audio output signal. This is achieved by direct mixing of the associated down-mix channels of the individual input signals. It is one key feature of the present invention that the combination of the down-mix channels is achieved by simple, computationally inexpensive arithmetic operations.