44 results about "Arithmetic computation" patented technology

An arithmetic operator includes: multiple arithmetic elements each serving as a programmable circuit capable of programming a logical function; and a data bus that connects two or more of the multiple arithmetic elements and that transmits transmission data. The transmission data includes first data used in one of the two or more arithmetic elements and second data used to reconfigure a logical function of any one of the two or more arithmetic elements, the transmission data destined for each of the two or more arithmetic elements on the same data bus is collectively transmitted on the same data bus at a cycle different with each of the two or more arithmetic elements, and each arithmetic elements receives the first data and the second data for own arithmetic element by extracting the transmission data destined for the own arithmetic element at a cycle associated with the own arithmetic element.

According to the present invention, multiple parametrically encoded audio signals can be efficiently combined using an audio signal generator, which generates an audio output signal by combining the down-mix channels and the associated parameters of the audio signals directly within the parameter domain, i.e. without reconstructing or decoding the individual input audio signals prior to the generation of the audio output signal. This is achieved by direct mixing of the associated down-mix channels of the individual input signals. It is one key feature of the present invention that the combination of the down-mix channels is achieved by simple, computationally inexpensive arithmetic operations.

The invention discloses a data transformation method and device and a storage medium, and the method comprises the steps: obtaining first color data, second color data and third color data for a positive transformation process of a coding end, carrying out the arithmetic operation of the first color data and the second color data, obtaining first chroma data, and obtaining second chroma data; and performing arithmetic operation on the third color data and the first color data to obtain second chrominance data, and taking the third color data as brightness data. Compared with a traditional method, the conversion method only needs two times of arithmetic operation, the calculation complexity can be remarkably reduced, redundancy between channels in a color space is reduced, meanwhile, hardware resource expenditure can be effectively saved, then the average power consumption of equipment can be reduced, and the working frequency can be improved.

A novel data generation system is provided, which includes a first data processing device having a function of generating a netlist by converting a hardware description language into graph-structured data and performing arithmetic processing based on Monte Carlo tree search, a second data processing device having a function of converting the graph-structured data into matrix data using a graph neural network, and a third data processing device including a transformer model and generating a first command in accordance with an input token sequence. The first data processing device has a function of generating a random number, and as a command executed in the Monte Carlo tree search, the first command or a second command selected using a calculation formula of action selection is selected in accordance with a magnitude relationship between the random number and a specified value.

A processing system and method for executing arithmetic and conversion operations involving 16-bit brain floating-point (BF16)-formatted data are described. An instruction specifying either an arithmetic or conversion operation and a first data element in BF16 data format are received. For arithmetic operations, the exponents of the data elements are aligned, and a result is generated using the aligned exponents. For conversion operations, the mantissa of the BF16 data element is scaled based on its exponent, and the element is converted to a second data format, such as FP32 or a reduced-precision format, using precision-aware scaling and rounding. The result is stored in operations registers, such as for additional processing.

There are provided systems and methods for reducing quantization errors, including method of optimizing a routine for a hardware-based processing system having a fixed length two's complement binary representation, the method comprising: receiving an instruction sequence arranged to perform the routine, wherein the instruction sequence comprises a set of arithmetic operations, wherein the outputs of the arithmetic operations exceed a precision of the hardware-based processing system; identifying one or more pairs of sub-sets of instructions in the sequence of instructions, the sub-sets of each pair having a respective comparable truncation error; and generating an optimized routine by modifying one of the sub-sets of each pair to invert the sign of one or more inputs to said sub-sets and modifying the instruction sequence to compensate for the said inversion.

The invention discloses a bit extraction-based zero arithmetic overhead address generation method and circuit. The method comprises the following steps of: detecting the position of a most significant bit of an input fixed-point integer to determine an interval index; directly extracting an intra-interval offset index from the input through a bit extraction operation; and splicing the interval index and the offset index bit to generate a storage address. The circuit comprises a most significant bit detection module, a bit extraction module and an address splicing module. According to the method, the mathematical characteristic of power interval division of 2 is utilized, the existing division operation is converted into simple bit extraction operation, and arithmetic operation in the address generation process is completely eliminated. Only a priority encoder, a multiplexer and bit splicing logic are needed, and no adder, multiplier or divider is included. Realization results on an FPGA show that the circuit only consumes 5-7 LUTs which are reduced by more than 90% compared with an existing method, and the circuit is particularly suitable for resource-limited embedded systems and processing application of high-throughput data streams.

The present invention addresses the problem of calculating the root of a power function. An arithmetic device according to the present invention calculates a root Y of a power function (Y = AX, wherein A is a constant, and X is a prescribed numerical range). The arithmetic device comprises: an input unit into which input data indicating an exponent X is input; a first arithmetic circuit that executes a first arithmetic process on the basis of a linear approximation equation of a graph of a power function in a first numerical region of a numerical range of the exponent X; a second arithmetic circuit that executes a second arithmetic process on the basis of a linear approximation equation of a graph of a power function in a second numerical region of the numerical range, the second numerical region differing from the first numerical region; and a selector that outputs output data indicating the root Y calculated by the first arithmetic circuit when if exponent X indicated by the input data inputted into the input unit belongs to the first numerical region, and outputs output data indicating the root Y calculated by the second arithmetic circuit if the exponent X indicated by the input data inputted into the input unit belongs to the second numerical region.

According to the present invention, multiple parametrically encoded audio signals can be efficiently combined using an audio signal generator, which generates an audio output signal by combining the down-mix channels and the associated parameters of the audio signals directly within the parameter domain, i.e. without reconstructing or decoding the individual input audio signals prior to the generation of the audio output signal. This is achieved by direct mixing of the associated down-mix channels of the individual input signals. It is one key feature of the present invention that the combination of the down-mix channels is achieved by simple, computationally inexpensive arithmetic operations.

This application discloses a data processing method, system, apparatus, device, and storage medium. The method, applied to a processor, includes performing precision adaptive processing on the mantissa portions of a first operand and a second operand to obtain a first processed mantissa and a second processed mantissa. The first and second operands are represented in floating-point format, with a first mantissa bit width. A first arithmetic unit is configured according to the effective bit width of the first and second processed mantissas to perform multiplication operations on the first and second processed mantissas, generating an intermediate mantissa result. The arithmetic bit width of the first arithmetic unit is smaller than that of the second arithmetic unit, which performs multiplication operations on the corresponding mantissa portions of the first and second operands. An arithmetic operation result is generated based on the exponent portions of the first and second operands and the intermediate mantissa result. This solution achieves a balance between accuracy and hardware area, power consumption, and computing power.

A hardware random number generator (HW-RNG) and related method are disclosed. The HW- RNG comprises a sample generation stage, adapted to produce primary samples from a plurality of primitive probability distributions, a sample processing stage and a control unit. The sample generation stage includes sets of programmable p-bit devices, a programming unit to adjust the mean values for each set of p-bit devices, and a distinct sampling circuit for each set of p-bit devices. The sample processing stage comprises function logic blocks and selection circuitry configured to route at least one subset of the primary samples to a corresponding function logic block. The control unit is configured to obtain information relating to a composition of basis distributions representative of a target distribution, instruct the function logic block to perform at least arithmetic operation identified by the information, instruct the programming unit to program the sets of p-bit devices according to the composition of basis distributions, and generate the select signal to operatively couple the function logic block to sampling circuits that produce primary samples of random variables defined by the composition of basis distributions.

In an information processing device, at least one processor acquires edited arithmetic operation data which indicates a result of arithmetic operations which are performed on a numerical formula on the basis of an input operation from a target person, decides whether it is preferable to change an arithmetic operation program which is stored in a memory and is based on the numerical formula, and in a case where it is decided that it is preferable to change the arithmetic operation program, changes the arithmetic operation program on the basis of the edited arithmetic operation result data which is acquired.

This application discloses a data processing apparatus and a data processing method. The apparatus includes: a configuration module, an input routing module, an interconnection routing module, and multiple multiply-accumulate unit modules; the configuration module configures the other modules according to an input mathematical model; the input routing module establishes an input route from the input data channel to the input interface of the multiply-accumulate unit module according to the configuration; the interconnection routing module establishes an interconnection route from the output interface of the preceding multiply-accumulate unit module to the input interface of the following multiply-accumulate unit module according to the numbering order of the multiply-accumulate unit modules, so as to realize the unidirectional cascading of multiple multiply-accumulate unit modules; the multiply-accumulate unit modules obtain their input data through the input route and / or the interconnection route and perform arithmetic operations on their input data according to the configuration. This data processing apparatus can realize flexible and complex arithmetic operations, meet the needs of switching and updating mathematical models, and balance data processing efficiency, data transmission efficiency, and interconnection overhead.

This system performs searches related to entities and returns the search results as entities. [Solution] The information processing device according to the present invention is characterized by comprising: a UI display control unit that displays a UI for arithmetic operation search; a search execution unit that performs an arithmetic operation search based on an entity's calculation formula when the entity's calculation formula is entered into the UI for arithmetic operation search; and a result display control unit that displays the entity returned as a result of the arithmetic operation search based on the entity's calculation formula on the UI for arithmetic operation search.

An apparatus includes processor circuitry having an execution pipeline configured to execute instructions within an instruction stream, the instruction stream including a first instance of an instruction executable to compute an address for accessing a data array. The first instance of the instruction may specify a set of operands, the set of operands including a pointer to a base address of the data array, an index into the data array, and a size of a data element within the data array. In response to receiving the first instance of the instruction, the execution pipeline may be configured to perform an arithmetic operation including multiplication of the index and the size to generate a result for the address. In response to the arithmetic operation generating an overflow condition, the execution pipeline may be further configured to perform a first correction action preventing access to the data array.

Rendering 3D geometry involves processing a very large amount of geometry. Compression techniques can be used to decrease the amount of data required for such geometry overall. A particular compression format for geometry is dense compression format, in which triangle strips are represented in highly compacted code sequences. In particular, compression code sequences describe the connectivity between triangles of a strip, thus ultimately provide a compact representation of which vertex indices comprise each triangle. A vertex index is an index into a vertex buffer that stores the actual vertex data, allowing for deduplication of such data. Though compact, such compression code sequences are somewhat tricky to decompress. A technique is provided herein for decompressing such code sequences. In particular, the technique involves a series of bitwise, arithmetic, and / or logical operations that expand out the code sequences into indices for the triangles.

A method for training a Boolean deep learning model (308, 408, 608), performed by a processor device (302, 402, 510, 602), is provided. The method involves receiving a request from a Boolean deep learning application (306, 406, 512, 606) to instantiate a multi-dimensional Boolean matrix array (414, 502) comprising binary values representing the model's weights or biases. A sequence of matrix arithmetic operations is then received, detailing tasks to be performed on this Boolean matrix array. For each operation in the sequence, the method determines whether the bit data's memory layout (310, 410, 520) needs reordering into a different bit vectorization dimension. If reordering is required, the method converts the current bit data layout accordingly. Following each conversion, the method updates the indicative bit vectorization parameters to reflect the new layout. This dynamic adjustment ensures optimal memory utilization and computational efficiency throughout the training process, improving the performance of the Boolean deep learning model.

The bit length of the given key is compressed to generate a key of equal size to the key used in the cryptographic algorithm. [Solution] The computing device causes a computer, which includes at least a processor and memory, to perform the following steps: when the bit length of a common key assigned for use in communication between a terminal device and a network is longer than the bit length of an input key used in a predetermined algorithm, a processing step of obtaining a bit sequence different from the bit sequence of the common key by performing different arithmetic operations on the bit sequence of the common key based on predetermined conditions; and a hashing step of inputting the bit sequence obtained in the processing step into a predetermined hash function agreed in advance between the terminal device and the network, thereby obtaining a bit sequence having the same bit length as the bit length of the input key.

The application discloses a kind of parallel computing methods based on 64, it is related to computer arithmetic operation technical field.The method includes: data packing step, 8 8-bit data column is packed into 64-bit register, each 8-bit data column includes 6 data bits and 2 carry bits;Parallel computing step, the arithmetic operation of the 8 data column is simultaneously handled using the 64-bit register;Carry processing step, the carry signal of each data column is stored and handled using independent carry register, and the carry signal is not propagated to adjacent data column.The application eliminates the traditional binary serial carry chain through innovative 64 radix design and independent carry register architecture, and realizes the simultaneous parallel processing of 8 data columns.Compared with prior art, the performance of the application is improved by 8 times, the energy consumption is reduced by 87.5%, no need for SIMD instruction set support, compatible with all 64-bit CPUs, and can be widely applied in cryptography, big data processing and scientific computing field.

Arithmetic circuitry according one embodiment performs a first arithmetic operation by AND operations and XOR operations. The first arithmetic operation corresponds to p multiplications (p is an integer of 2 or more) to be performed in series. The p multiplications are respectively represented by p order-3 tensors each receiving two elements of a Galois field as inputs and outputting one element as a result of multiplication of the two elements. The AND operations calculate AND values of a plurality of elements used in the p multiplications. The XOR operations are based on a contracted tensor obtained by contraction of an order-3p tensor obtained by a direct product of the p order-3 tensors and the AND values.

The present invention relates to a self-diagnosis apparatus of an electronic device, including a vector memory configured to store a test function code for testing a device under test (DUT) equipped with a plurality of cores performing arithmetic operations, a function test expectation value corresponding to a function test according to the test function code, a design for test (DFT) test code for testing, a DFT test expectation value corresponding to a DFT test according to the DFT test code, and a non-test function code for general arithmetic operations or operations of the DUT, a test data memory configured to store test data, and a secure area test controller configured to select a test mode, control an environment variable of a test signal applied to the DUT and test the DUT, compare the function test expectation value with a test function code result value, and compare the DFT test expectation value with a DFT test code result value to output comparison result information.

Embodiments of the present disclosure relate to systems and methods for handling floating point hardware anomalies. A method includes receiving input data at an FP arithmetic operation unit, the FP arithmetic operation unit configured to perform an FP arithmetic operation on the input data. The method further includes determining whether the received input data generates an FP hardware exception in response to an FP arithmetic operation on the input data, wherein the determination occurs prior to performing the FP arithmetic operation. The method further includes, in response to determining that the received input data generates an FP hardware anomaly, converting a value of the received input data to a modified value, where the conversion eliminates generation of the FP hardware anomaly in response to an FP arithmetic operation on the input data.

A non-transitory computer-readable recording medium stores therein a mapping result verification program that causes a computer to execute a process including acquiring both of a data flow graph that represents predetermined calculation including a plurality of arithmetic operations and a mapping result obtained by mapping the data flow graph into a CGRA that includes a plurality of arithmetic operation units, and verifying, regarding each of first arithmetic operation units to which the arithmetic operations have been respectively allocated in the mapping result, based on an arithmetic operation result that has been obtained by performing the arithmetic operations, whether or not the mapping result matches the data flow graph.

A radio wave propagation simulation system is constituted with a computer including an arithmetic device that executes predetermined arithmetic processing and a storage device connected to the arithmetic device, and includes a model generation unit which generates a radio wave propagation model by the arithmetic processing of the arithmetic device, and the model generation unit generates a plurality of planes that simulate one surface of a structure, defines, as an attribute of each of the planes to be generated, a unit normal vector representing an orientation of each of the planes and generates a radio wave propagation model constituted with the generated planes.

Decoding of a merge-predicted block is carried out, for triangular partitions of the block, using a combination of inter-prediction and intra-prediction. The combination of inter-prediction and intra-prediction to be used is signalled on a received bitstream. Combination may be algorithmic, for example arithmetic.

Processing unit arrangement comprising a data source unit (10), a processing unit (20), and an actuation unit (30). The data source unit (10) is configured to provide the processing unit (20) with direct input data (D). DI ) to provide, wherein the data source unit (10) and the processing unit (20) are directly connected to each other via first data lines (W1). The processing unit (20) includes an arithmetic unit (22) configured to process direct actuation data (D DA ) to determine by performing arithmetic operations on the direct input data (D DI ) performs. The processing unit (20) is configured to process the direct actuation data (D DA) to provide the actuation unit (30), wherein the processing unit (20) and the actuation unit (30) are directly connected to each other via second data lines (W2). The actuation unit (30) is configured to operate an application using the direct actuation data (D DA ) to control.

The invention discloses an OAM mode multiplication and division operation method and system based on an optical diffraction neural network, and relates to the field of orbital angular momentum. Digital signals are represented through OAM mode coding, any 2n times of digital multiplication / division operation can be achieved, the operation function has the advantages of being high in expandability, flexible, controllable and the like, and the method and system can be applied to the field of orbital angular momentum. A basic framework is expected to be established for complex arithmetic operation in a high-dimensional optical space, and a potential solution is provided for practical application of optical digital calculation; the OAM mode serves as an operation physical dimension, mode parallel independent transformation is completed through the optical diffraction neural network to achieve OAM mode numerical value shifting, and therefore digital multiplication / division operation is completed, and the obtained output array has high mode purity.

According to the present invention, multiple parametrically encoded audio signals can be efficiently combined using an audio signal generator, which generates an audio output signal by combining the down-mix channels and the associated parameters of the audio signals directly within the parameter domain, i.e. without reconstructing or decoding the individual input audio signals prior to the generation of the audio output signal. This is achieved by direct mixing of the associated down-mix channels of the individual input signals. It is one key feature of the present invention that the combination of the down-mix channels is achieved by simple, computationally inexpensive arithmetic operations.

An accelerator control system includes an accelerator control device and a plurality of accelerators, wherein the accelerator control device includes first processing circuitry configured to store control data including a location of data which is an arithmetic processing target, information on an accelerator for performing arithmetic processing, and information specifying content of the arithmetic processing of the accelerator, and determine completion of the arithmetic processing by the accelerator when the control data which has been subjected to the arithmetic processing by the accelerator is stored in a storage, and each of the accelerators includes second processing circuitry configured to acquire the control data from the storage, and perform arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying the content of the arithmetic processing of the accelerator included in the acquired control data.