88results about How to "Eliminate parasitic capacitance" patented technology

The invention discloses an organic electroluminescence touch control panel, a driving method thereof and a display device. On the basis that an original organic electroluminescence structure is not changed, a cathode layer of the organic electroluminescence structure is divided into multiple cathodes independent and insulated from each other, in the touch control stage, the cathodes serve as touch control electrodes to sense external touch control, touch control signals are transmitted to a touch control and display integrated chip via leads, and thus, the touch control function is integrated into organic electroluminescence display of a display panel; and in the reset stage, a pixel driving circuit is used to initialize a control end of a driving module; in the compensation stage, the threshold voltage of the driving module is compensated to avoid influence of the threshold voltage change of the driving module on the luminescence brightness of the organic electroluminescence structure; and in the touch control stage, signals of signal lines and external touch control signals sensed by the touch control electrodes are modulated synchronously to eliminate the parasitic capacitance of the touch control electrodes and improve the touch control performance of the touch control panel.

The invention provides an optical-receiver preamplifier for receiving analog or digital optical signals. The preamplifier comprises a high-gain amplifier A1, an input circuit, a negative-feedback impedor Zf, a low-gain amplifier A2 adjustable in gain and a feedback capacitor Cff, wherein the input circuit takes a photoelectric converter as a main component; the negative-feedback impedor Zf is connected with the reverse input end and the output end of the A1; the feedback capacitor Cff connects the output end of the A2 with the reverse input end of the A1; and the output end of the A1 can be directly connected with the input end of the A2 or can be connected with the input end of the A2 through a buffer. Output signals of the preamplifier are taken out from the output end of the A1 or the output end of the buffer, and can be directly subjected to subsequent signal processing or be further amplified and then subjected to subsequent signal processing.

In a manufacturing process of a semiconductor device having a CMISFET, first, a silicon film and a first metal film made of a first metal are reacted with each other through heat treatment, thereby forming a gate electrode of a p-channel type MISFET and a dummy gate electrode of an n-channel type MISFET, which are formed of metal silicide. Subsequently, an insulating film is formed so as to cover the gate electrode but expose the dummy electrode, and then, a metal film formed of a second metal having a work function lower than that of the first metal. The metal film contacts with the dummy gate but not with the gate electrode due to the insulating film interposing therebetween. Thereafter, through heat treatment, the dummy gate electrode and the metal film are reacted with each other to form a gate electrode of the n-channel type MISFET.

A display having a touch sensor comprises: a plurality of pixel areas disposed in a matrix manner on a substrate; a routing line running along a first direction on the substrate; a first passivation layer covering the routing line; a touch electrode covering the routing line and corresponding to a grouped pixel areas on the first passivation layer; a touch contact hole exposing some portions of the routing line by penetrating the touch electrode and the first passivation layer; a second passivation layer covering the touch electrode; a passivation contact hole exposing the touch contact hole and some portions of the touch electrode around the touch contact hole by penetrating the second passivation layer; and a touch terminal connecting the touch electrode and the routing line on the second passivation layer.

A thin-film semiconductor device for a display apparatus according to the present disclosure includes: a gate electrode above a substrate; a gate insulating film above the gate electrode; a semiconductor layer on the gate insulating film; a first electrode above the semiconductor layer; a second electrode in a same layer as the first electrode; an interlayer insulating film covering the first electrode and the second electrode; a gate line above the interlayer insulating film; and a power supply line in a same layer as the gate line and adjacent to the gate line. Furthermore, the gate electrode and the gate line are electrically connected via a first conductive portion, and the second electrode and the power supply line are electrically connected via a second conductive portion.

A display panel drive circuit having a plurality of first and second electrodes for connecting to a display panel, a first drive circuit for driving the first electrodes, and a second drive circuit for driving the second electrodes. The second drive circuit is connected to drive all or a part of a plurality of the second electrodes, or interrupted to increase output impedance.

Three dimensional dynamically shielded high quality factor (Q) BEOL metal elements, such as inductor elements, are disclosed. Three dimensional shielding structures for the BEOL elements reduce or eliminate parasitic substrate capacitive coupling between the BEOL element and the conductive substrate, and parasitic shunt capacitance coupling between different adjacent shunt sections of the BEOL element. The reduction or elimination of the parasitic capacitive components provides high Q BEOL metal elements such as inductor elements. The three dimensional shield structure includes a lower shield surface having a width greater than the width of the BEOL element, and opposed side shield surfaces which extend upwardly from opposite side edges of the lower shield surface, such that the three dimensional shield element forms a U shaped shield around the BEOL element. The three dimensional shield element is dynamically driven to the same electrical potential as the BEOL element, to substantially eliminate the metal element's parasitic capacitances.

The invention discloses a touch display panel, a driving method and a touch display device. The touch display panel comprises a shift circuit, a control signal line, a control circuit, multiple scanning lines, multiple data lines, multiple touch driving electrodes, a switching control signal end and a switching control switch unit. During a touch period of a frame cycle, all switching control switches are switched on under the control of a first control signal output by the switching control signal end, so that all the touch driving electrodes are electrically connected with at least one data line through at least one switching control switch; the control circuit enables the scanning lines to be suspended based on the first control signal output by the switching control signal end and a signal at the output end of the shift circuit. Through the touch display panel, coupling between devices on the touch display panel is lowered, stray capacitance between the scanning lines and other devices is eliminated, and the signal detection precision of the touch display panel is improved.

The invention discloses an electric conducting plug and a forming method of the electric conducting plug. The forming method of the electric conducting plug comprises the steps that a semiconductor substrate is provided, a grid electrode is formed on the semiconductor substrate, a source region and a drain region are formed in the semiconductor substrate located on the two sides of the grid electrode respectively, a stress layer and an interlayer dielectric layer on the stress layer are formed on the semiconductor substrate, and the stress layer covers the grid electrode, the source region and the drain region; contact holes are formed in the interlayer dielectric layer and the stress layer; a liner layer is formed on the side walls of the contact holes; after the liner layer is formed, the contact holes are cleaned so as to eliminate polymers generated in the process that the contact holes are formed, the liner layer is used for preventing the stress layer from being corroded in the cleaning process of the contact holes, after the contact holes are formed, electric conducting materials are deposited in the contact holes, and the electric conducting plug is formed. Due to the liner layer, the stress layer is prevented from being corroded in the process that the polymers in the contact holes are cleaned later, contact of the grid electrode and the electric conducting plug is further prevented, and good performance of a semiconductor is guaranteed.

The invention relates to a semiconductor device with a height-controllable fin and a preparation method. The preparation method comprises the following steps: providing a semiconductor substrate; forming a first semiconductor material layer, a second semiconductor material layer and a hard mask layer on the substrate; etching the hard mask layer, a second semiconductor material layer and a first semiconductor material layer to form a trench and a fin pattern; performing isotropic etching to remove a part of the first semiconductor material layer in the fin pattern to form a virtual fin with reduced critical size; depositing dielectric layers to fill the trench and cover the fin pattern; etching the dielectric layers till the second semiconductor material layer below, in order to expose the second semiconductor material layer to form the fin. The preparation process of the fin is easy to control, and the obtained device is more stable.

Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure. The capacitance, and therefore thickness, of the gate dielectric capacitor is determined by subtracting the parasitic capacitances measured at the first and second dummy structures.

The invention discloses a capacity testing method in a multi-layer interconnection system which is used for increasing the accuracy of capacity test. The method comprises the following steps: according to a test signal applying manner, applying test signals to all interconnected wires in the multi-layer interconnection system; after applying the test signals each time, testing the overall capacity value of the multi-layer interconnection system; and calculating a to-be-tested capacity value, according to the tested overall capacity value and the quantitative relation between the overall capacity value and the to-be-tested capacity value.

In the TSC structure, a first dielectric layer is formed over the first major surface of the substrate. The substrate includes opposing second major surfaces. A TSC is formed in the first dielectric layer and the substrate such that the TSC passes through the first dielectric layer and extends into the substrate. A conductive plate electrically coupled to the TSC is formed over the first dielectric layer. An isolation trench is formed in the substrate to surround the conductive plate and is spaced apart from the conductive plate. A second dielectric layer is formed on the second major surfaceof the substrate. A plurality of first through holes extending into the substrate and connected to the TSC are formed in the second dielectric layer. A plurality of second through holes extending intothe substrate but not connected to the TSC are formed in the second dielectric layer.

A microelectromechanical microphone and method of manufacturing the same are disclosed. The microphone has a moveable diaphragm and a fixed backplate that create a variable capacitance. A fixed anchor electrically coupled to the diaphragm has an electrode that measures the variable capacitance, but also measures an unwanted, additive, parasitic capacitance. Various embodiments include a reference electrode, manufactured in the same deposition layer as the diaphragm or anchor, that measures only the parasitic capacitance. A circuit is provided either on-chip or off-chip that subtracts the capacitance measured at the reference electrode from that measured at the anchor, thereby producing only the desired variable capacitance as output. Because the reference electrode is deposited at the same time as the diaphragm or anchor, only minimal changes are required to existing manufacturing techniques.

The invention relates to a thin-film transistor and a liquid crystal display device using the thin-film transistor. The thin film transistor comprises a first drain electrode, a second drain electrode, a source electrode and a grid electrode, wherein a semi-close area is formed by the first drain electrode and the second drain electrode, and one end of the source electrode is positioned in the semi-close area. The thin-film transistor can reduce the parasitic capacitance generated between the source electrode and the grid electrode and improve the display quality of images.

A capacitive pressure sensor includes: a conductive silicon substrate having a diaphragm; an insulating substrate having a fixed electrode, the insulating substrate overlapping the conductive silicon substrate so as to be bonded thereto; and a sealed chamber formed between the diaphragm and the fixed electrode. A conductive silicon member is buried in a part of the insulating substrate, a portion of the conductive silicon member is exposed toward a surface of the insulating substrate facing the sealed chamber so as to form the fixed electrode, and another portion of the conductive silicon member is exposed toward the other surface of the insulating substrate not facing the sealed chamber so as to form a lead electrode of the fixed electrode.

A frequency divider is disclosed herein. The frequency divider includes a first latch circuit and a second latch circuit coupled to the first latch circuit. Each of the first latch circuit and the second latch circuit includes a first level for generating a source current, a second level for receiving a pair of input signals and for generating a pair of output signals, and a third level for receiving the source current and a pair of clock signals. The second level is coupled between the first level and the third level. The first level includes a first transistor having a source terminal and a substrate both coupled to a source voltage. The third level includes a plurality of transistors controlled by the pair of clock signals. Each transistor in the third level has a source terminal and a substrate both coupled to ground. Compared with current technique, the frequency divider provided in the invention removes transistor bias effect and parasitic capacitance, with the input signal having smaller value capable of conducting the input level thereof, which is capable of provided with relatively high output voltage amplitude free of buffer so as to enhance property thereof.

Two conducting wires are used in one embodiment of an inductor. Opposite ends of each of the conducting wires are connected to leader lines (terminals) shared by the conducting wires. Each of the conducting wires is wound to make half a round of an annular or ring-like magnetic substance. One of the conducting wires is wound around a lower half area of the magnetic substance to form one winding while the other conducting wire is wound around an upper half area of the magnetic substance to form another winding. In this manner, the distance between the leader lines can be increased to eliminate parasitic capacitance between the leader lines. The magnetic fluxes generated by current flowing in the two windings are in the same direction. Thus, it is possible to provide an inductor whose total parasitic capacitance is reduced. In other embodiments, additional conducting wires are used.

The invention relates to a glass-sealed voltage regulation diode, a tube core and a manufacturing method thereof. The tube core comprises a silicon wafer, a passivation protection layer, a first electrode and a second electrode. Arc-shaped gaps are formed around the front surface of the silicon wafer; an island area is formed in the center, a first electrode is attached to the center island area on the front face of a silicon wafer, a second electrode is attached to the back face of the silicon wafer, a passivation protection layer avoids the first electrode and is attached to an arc notch ofthe silicon wafer, and the passivation protection layer is of a three-layer composite structure and sequentially comprises a first silicon dioxide layer, a PSG layer and a second silicon dioxide layerfrom the silicon wafer to the outside. The diode further comprises a first tungsten column, a second tungsten column, a glass outer cover, a first lead end and a second lead end on the basis of the tube core, the first tungsten column and the second tungsten column are respectively welded with the first electrode and the second electrode, and the first lead end and the first lead end are respectively welded with the first tungsten column and the second tungsten column; the glass outer cover is packaged on the outer sides of the first tungsten column and the second tungsten column and used forprotecting the tube core. The diode is low in thermal resistance and high in reliability.