Transistor and forming method thereof

Abstract

The invention relates to a transistor and a forming method thereof. The forming method comprises the following steps that: a semiconductor substrate is provided; gate structures are formed at the semiconductor substrate, wherein the gate structures include gate dielectric layers formed at the semiconductor substrate and gate electrodes arranged at the gate dielectric layers and first side walls are formed at the semiconductor substrate around the gate structures; a sigma-shaped groove is formed in the semiconductor substrate at the two sides of the gate structures; a first stress liner layer is formed in the sigma-shaped groove, wherein the surface of the first stress liner layer is flush with the surface of the substrate; second side walls are formed around the first side walls; a second stress liner layer is formed on the first stress liner layer, wherein the thickness of the second stress liner layer is less than or equal to the height of the second side wall. Because of the second side walls, the distance between the second stress liner layer and the gate structures to be enlarged; the parasitic capacitance between the second stress liner layer and the gate structures is reduced or even eliminated; and the semiconductor device performance is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a transistor and the transistor. Background technique [0002] In the existing manufacturing process of semiconductor devices, since stress can change the energy gap and carrier mobility of silicon materials, it has become an increasingly common means to improve the performance of MOS transistors through stress. Specifically, by properly controlling the stress, the mobility of carriers (electrons in NMOS transistors and holes in PMOS transistors) can be increased, thereby increasing the driving current, thereby greatly improving the performance of MOS transistors. For PMOS transistors, embedded silicon germanium technology (Embedded SiGe Technology) can be used to generate compressive stress in the channel region of the transistor, thereby improving carrier mobility. The so-called embedded silicon germanium technology refers to embedding silicon germa...

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Problems solved by technology

[0010] The problem solved by the present invention is that the performance of transistors with stress liner layers formed by using embedded silicon germanium technology in the prior art is not good

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