Electric conducting plug and forming method of electric conducting plug

Abstract

The invention discloses an electric conducting plug and a forming method of the electric conducting plug. The forming method of the electric conducting plug comprises the steps that a semiconductor substrate is provided, a grid electrode is formed on the semiconductor substrate, a source region and a drain region are formed in the semiconductor substrate located on the two sides of the grid electrode respectively, a stress layer and an interlayer dielectric layer on the stress layer are formed on the semiconductor substrate, and the stress layer covers the grid electrode, the source region and the drain region; contact holes are formed in the interlayer dielectric layer and the stress layer; a liner layer is formed on the side walls of the contact holes; after the liner layer is formed, the contact holes are cleaned so as to eliminate polymers generated in the process that the contact holes are formed, the liner layer is used for preventing the stress layer from being corroded in the cleaning process of the contact holes, after the contact holes are formed, electric conducting materials are deposited in the contact holes, and the electric conducting plug is formed. Due to the liner layer, the stress layer is prevented from being corroded in the process that the polymers in the contact holes are cleaned later, contact of the grid electrode and the electric conducting plug is further prevented, and good performance of a semiconductor is guaranteed.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a conductive plug and a method for forming the conductive plug. Background technique [0002] The method for forming conductive plug in prior art: refer to figure 1 , providing a semiconductor substrate 10, on which a gate dielectric layer 11, a gate 12, and sidewalls 13 around the gate 12 are sequentially formed; on the semiconductor substrate 10, a source region and a drain region (not shown) are formed shown); see figure 1 , form a metal silicide (Silicide) 14 on the gate 12, the source region and the drain region, such as nickel silicide (Ni 2 Si); refer to figure 2 , use stress proximity technology (Stress Proximity Technology, SPT) to remove side wall 13; continue to refer to figure 2 , forming a stress layer 15 on the semiconductor substrate 10, the material of the stress layer 15 is silicon nitride; refer to image 3 , forming an interlayer dielectric layer ...

AI Technical Summary

Problems solved by technology

[0006] The problem solved by the present invention is to use the method of the prior art

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