Capacity testing method

Abstract

The invention discloses a capacity testing method in a multi-layer interconnection system which is used for increasing the accuracy of capacity test. The method comprises the following steps: according to a test signal applying manner, applying test signals to all interconnected wires in the multi-layer interconnection system; after applying the test signals each time, testing the overall capacity value of the multi-layer interconnection system; and calculating a to-be-tested capacity value, according to the tested overall capacity value and the quantitative relation between the overall capacity value and the to-be-tested capacity value.

Description

Technical field [0001] The invention relates to the field of semiconductors, and in particular to a capacitance testing method in a multilayer interconnection line system. Background technique [0002] With the development of integrated circuit technology, the number of interconnection lines on the same chip has become more and more, from three layers and four layers to nine layers and ten layers or more. What follows is that the interconnection delay gradually becomes an influence The bottleneck of integrated circuit development. Since interconnection line parasitic parameters such as interconnection capacitance and interconnection resistance have a decisive influence on interconnection delay, the test of interconnection line parasitic parameters has attracted increasing attention. [0003] At present, the test machines for capacitance testing in the industry are based on the principle of bridge measurement. There are only two ports on the test end of the machine, which output hi...

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Problems solved by technology

[0005] For example, if you want to test the interlayer capacitance C between the third layer interconnection line and the fourth layer interconnection line 43 (See figure 1 ), you can connect one port of the test machine test terminal to the interconnection line a 32, apply the H test signal to it, connect the other port to the interconnection line b 42, apply the L test signal to it, and then test the two The capacitance value between the two ports is taken as the interlayer capacitance C 43 capacitance value, but in this test scheme, because other interconnection lines outside the interconnection line a 32 and the interconnection line b 42 are in a floating state, when there are signals on the interconnection line a 32 and the interconnection line b 42, these The suspended interconnection wires will induce charges to the two signal-applied interconnection wires (i.e. interconnection line a 32 and interconnection line b 42 ), generating parasitic capacitance, so that the measured capacitance value of the testing machine includes no These expected parasitic capacitances cause large errors in the measured capacitance values, resulting in reduced test accuracy

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