192 results about "Charge sharing" patented technology

The invention relates to a low-noise fast duty cycle detector and a duty cycle detection method thereof. The duty cycle detector includes a current directing network to direct a first current to a second current to charge the first capacitance when the clock is in a first state of an even cycle and to direct the first current to a third current to charge the second capacitance when the clock is in a second state of the even cycle; the first charge sharing switch is used for promoting charge sharing between the first capacitor and the third capacitor when the clock is in the second state; the second charge sharing switch is used for promoting charge sharing between the second capacitor and the fourth capacitor when the clock is in the first state; the first discharge network is used for discharging the first capacitor when the clock is in a first state of an odd number period; and the second discharging network is used for discharging the second capacitor when the clock is in the second state of the odd number period.

Disclosed are a driver circuit for a display, which is capable of a two-stage charge sharing operation, and an operating method thereof.

A duty cycle detector includes a current steering network configured to steer a first current into a second current to charge a first capacitor when a clock is in a first state, and to steer the first current into a third current to charge a second capacitor when the clock is in a second state; a first charge sharing switch configured to enable charge sharing between the first capacitor and a third capacitor when the clock is in the second state; a second charge sharing switch configured to enable charge sharing between the second capacitor and a fourth capacitor when the clock is in the first state; a first discharging network configured to discharge the first capacitor when the clock is in a first state; and a second discharging network configured to discharge the second capacitor when the clock is in a second state.

An image sensor includes a logic die, including column readout circuits and bitlines connected to the column readout circuits. A sensor die is overlaid on the logic die. The image sensor includes an array of detector elements, each including a sensing circuit on the sensor die, which includes a photodiode, a floating diffusion node a charge sharing transistor coupled between the photodiode and the floating diffusion node, a reset transistor coupled to the floating diffusion node, and a source follower transistor. In each detector element, a pixel circuit on the logic die includes a select transistor, which has an input coupled to the output of the source follower and an output coupled to one of the bitlines. Two current memory circuits are coupled to the input of the select transistor and are configured to sense and output respective signals indicative of levels of noise in the detector element.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) circuit design, in particular to a sensitive amplifier, a reading circuit and a module based on capacitance and flip point compensation. The invention discloses a sensitive amplifier based on capacitors and flip point compensation. The sensitive amplifier comprises nine NMOS (N-channel Metal Oxide Semiconductor) tubes M1-M9, two PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P2 and two capacitors C1-C2. According to the invention, the CSCSA is designed, and corresponding control logic is matched, so that a pre-charging stage, an offset elimination stage, a charge sharing stage, a pre-sensing stage and an induction amplification stage are designed when the DRAM storage unit is read, the potential of a bit line BL or BLB can be correctly changed, and the reading amplification function of the CSCSA is ensured. Compared with the traditional DRAM sensitive amplifier, the CSCSA provided by the invention has the advantages that the offset voltage index is greatly reduced and the sensing yield is improved under the condition that the quantity of elements is not greatly increased.

A source driver for controlling charge sharing and a display device including the same are disclosed. A source driver according to at least one of various embodiments of the present disclosure may include: a first latch unit that stores first image data for each channel; a second latch unit that stores second image data input through the first latch unit; a charge sharing control unit that acquires a predefined bit of the first image data of the first latch unit and a predefined bit of the second image data of the second latch unit for a target channel among channels having the same polarity, and acquires a predefined bit of the first image data of the first latch unit and a predefined bit of the second image data of the second latch unit for an adjacent channel; the processor is used for acquiring predefined bits of the first image data of the first latch unit and predefined bits of the second image data of the second latch unit, and generating and outputting an MUX operation control signal based on data change; and an MUX that performs a charge sharing operation according to the MUX operation control signal.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) circuit design, in particular to a sense amplifier, a reading circuit and a module based on bit line switch and capacitance coupling. The invention discloses a DRAM (Dynamic Random Access Memory) sensitive amplifier based on bit line switch and capacitance coupling. The DRAM sensitive amplifier comprises nine NMOS (N-channel Metal Oxide Semiconductor) tubes N1-N9, two PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P2 and two capacitors Cc1-Cc2. The SCSA is designed and matched with corresponding control logic, so that a pre-charging stage, an offset calibration stage, a charge sharing stage, a pre-induction stage and a main induction stage are designed when the SCSA reads a DRAM storage unit, the potential of a bit line BLT or BLB can be correctly changed, and the SCSA reading amplification function is guaranteed. Compared with a traditional DRAM sensitive amplifier, the SCSA provided by the invention has the advantages that the offset voltage index is greatly reduced under the condition that the number of elements is not greatly increased, and the sensing margin is effectively increased.

An apparatus and method for efficiently routing a power signal across a semiconductor die. In various implementations, an integrated circuit includes micro-through-silicon vias (TSVs) traversing a silicon substrate layer to a backside metal layer. The integrated circuit also includes a power switch. The integrated circuit routes a power signal from an output of the power switch to a front-side power rail using the micro TSVs and the back-side metal layer. The integrated circuit also routes the power signal from the output of the power switch to the front-side power rail using a front-side metal layer. Thus, the front side metal layer and the back side metal layer provide power connection redundancy, which increases charge sharing, improves wafer yield, reduces voltage drop, and reduces on-die area. In addition, the process uses both a front-side power rail and a back-side power rail to route ground reference voltage levels.

The invention relates to an analog-to-digital converter of an embedded filter, a driving chip and electronic equipment, and the analog-to-digital converter comprises a first analog-to-digital conversion module which is a successive approximation type analog-to-digital converter with a plurality of sampling capacitors and a plurality of sampling periods, the first analog-to-digital conversion module realizes a finite impulse response (FIR) filtering effect on an input sampling signal through charge sharing among sampling capacitors; and while part of the sampling capacitors still perform the process of sampling the input signals, the successive approximation quantization process of the signals on part of the sampling capacitors which have already been sampled is started. The analog-to-digital converter provided by the embodiment of the invention has a filtering characteristic and also has the characteristics of high bandwidth, low power consumption and small area.

A communication method to discharge energy is enabled. For example, a vehicle can comprise a memory that stores computer executable components, and a processor that executes the computer executable components stored in the memory, wherein the computer executable components comprise a connection component that, based on receiving a connection from a first vehicle, establishes a communication link with the first vehicle, a communication component that, based on receiving the connection, receives a charge sharing request message, from the first vehicle, comprising charge transfer data, and a charge sharing determination component that, based on a charge sharing request message, determines a type of charge sharing request extracted from the charge sharing request message.

The invention relates to the technical field of analog and digital-analog hybrid integrated circuits, and discloses a bootstrap sampling switch circuit with a pre-charging function and an analog-to-digital converter. The circuit comprises a sampling switch module and a time sequence control module. The sampling switch module sequentially works at a holding phase, a pre-charging phase and a tracking phase under the control of a multi-phase clock signal generated by the time sequence control module, the pre-charging phase is added before the tracking phase, the grid voltage of a sampling switch is pre-boosted, and the pre-charging time is dynamically controlled by using an adjustable clock circuit, so that the pre-charging time of the sampling switch is dynamically controlled. Therefore, the charge sharing effect caused by the gate parasitic capacitance is effectively suppressed. The analog-to-digital converter comprises the sampling switch circuit. The linearity and the conduction characteristic of the sampling switch are remarkably improved, and the sampling switch has excellent time sequence configurability and is suitable for a high-speed and high-precision analog-to-digital conversion system.

Vehicle charge sharing and communication (e.g., using a computerized tool) are enabled. For example, a vehicle can comprise a memory that stores computer executable components, and a processor that executes the computer executable components stored in the memory, wherein the computer executable components comprise a charge sharing determination component that, based on a charge sharing request from another vehicle, other than the vehicle, determines whether a condition of a battery of the vehicle satisfies a charge sharing criterion applicable to the charge sharing request, and a communication component that, based on the condition of the battery being determined to satisfy the charge sharing criterion, establishes a communicative connection with the another vehicle.

A source driver includes: output amplifiers, supplying pixel drive voltages to source lines of a display device based on a video signal; a charge share line, having a charge share switch able to connect output lines outputting the pixel drive voltages; a common voltage line, connected to a common voltage electrode of the display device; a first power supply line, supplying a first voltage; a switch part, able to connect the charge share line and the common voltage line with the first power supply line; and a control part, including a power off detection circuit that detects stoppage of supply of the first voltage. When it is detected that the first power supply line is off, the control part short-circuits the source lines by the charge share line and connects the charge share line and the common voltage line with the first power supply line by the switch part.

The embodiment of the invention provides a LOFIC pixel circuit. The LOFIC pixel circuit comprises a photodiode, a transmission transistor, a floating diffusion node, a switch transistor, a first reset transistor, a first power supply, a first overflow charge storage capacitor, a second overflow charge storage capacitor and a charge sharing transistor, wherein the drain electrode of the switch transistor is connected with the upper electrode plate of the first overflow charge storage capacitor; the source electrode of the charge sharing transistor is connected with the upper electrode plate of the first overflow charge storage capacitor and the source electrode of the first reset transistor; the drain electrode of the charge sharing transistor is connected with the upper electrode plate of the second overflow charge storage capacitor; a lower pole plate of the first overflow charge storage capacitor and a lower pole plate of the second overflow charge storage capacitor are connected with a power supply or the ground. According to the LOFIC pixel circuit, a traditional LOFIC capacitor is divided into two parts, and dynamic range expansion can be effectively achieved through charge distribution and dynamic refreshing.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) circuit design, in particular to a sense amplifier based on flip point and current mirror compensation, a reading circuit and a chip. The invention designs a sensitive amplifier based on flip point and current mirror compensation. The sensitive amplifier comprises 11 NMOS (N-channel Metal Oxide Semiconductor) tubes M1-M11 and two PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P2. Corresponding control logic is provided in cooperation with the provided sensitive amplifier, so that a pre-charging stage, an offset elimination stage, an offset compensation stage, a charge sharing and reference voltage amplification stage and an induction amplification stage are designed when the sensitive amplifier reads the DRAM storage unit. The sensitive amplifier provided by the invention has the advantages that the number of elements is small, the circuit area is not greatly increased, the high sensing yield is ensured, the offset voltage index is greatly reduced, and the reading speed is increased.

The invention provides a control method of a source electrode driving circuit, a display panel driving circuit and a display device.In the control method of the source electrode driving circuit, a first charge sharing circuit in the source electrode driving circuit is controlled to share charges after driving of a corresponding frame is finished; gray scale voltage signals of the two data lines are compared with polarity reference voltage, when one voltage is larger than the polarity reference voltage, an input selection switch and an output selection switch in the source electrode driving circuit are controlled to be correspondingly switched in a next frame of display picture, a positive polarity gray scale voltage signal is output to the data line, and a negative polarity gray scale voltage signal is output to the data line; when the voltage is smaller than the polarity reference voltage, an input selection switch and an output selection switch in the source electrode driving circuit are controlled to be correspondingly switched in the next frame of display picture, so that a negative polarity gray scale voltage signal is output to the data line, the charging cross voltage is reduced, charging charges are reduced, and driving power consumption is reduced.

A bit line charge sharing precharge circuit is provided that precharges a bit line pair during a charge sharing period in which the bit line pair is isolated from a memory power supply voltage. Prior to the charge sharing period, one of the bit lines in the bit line pair was charged to the memory power supply voltage whereas a remaining one was either fully or partially discharged. Charge thus flows from the charged bit line to the discharge bit line during the charge sharing period to precharge the bit lines for a current read or write operation.

The present application relates to the field of analog integrated circuit technology, and particularly relates to a kind of sampling and holding circuit based on noise cancellation.The present application handles sampling noise by introducing noise cancellation technology, input signal is directly connected to the upper plate of C1, C1 samples during S1 switch is closed;The output end of operational amplifier is connected with the lower plate of C2 through S2 switch, C2 samples sampling noise during S2 switch is closed, C2 two ends are connected with C1 two ends through S3 switch, C1 and C2 share charge during S3 switch is closed;Dynamic operational amplifier output end is connected with latch at the same time, so as to use operational amplifier as the preamplifier of comparator.The present application effectively suppresses the deterioration of sampling noise under the condition of reducing sampling capacitor, and dynamic operational amplifier greatly reduces the power consumption and noise of sampling and holding after introducing operational amplifier, and C2=C3 can also be set to make the gain of dynamic operational amplifier in noise elimination stage and subsequent as comparator preamplifier be equal, further improve the precision of circuit.

The present invention provides a charge sharing circuit, method, display driver module, and display device. The charge sharing circuit includes a control unit and a switch unit. The control unit is electrically connected to the first output control terminals of two clock signal generation units, respectively, and is configured to provide an on control signal to the switch unit via the control signal output terminal when the first output module, under the control of the first output control signal, does not output a first voltage signal. Under the control of the on control signal, the switch unit controls the connection between the clock signal output terminals of the two clock signal generation units. The present invention can reduce the number of level conversion circuits used, saving chip area.

The invention provides a PLL loop bandwidth adjusting circuit, a control method and a circuit board. The PLL loop bandwidth adjusting circuit comprises a phase frequency detector, a charge sharing filter, a phase-locked loop proportional path module and an adjustable voltage-controlled oscillator. The input end of the phase frequency detector is connected with a reference signal; the first output end of the phase frequency detector is connected with the first input end of the adjustable voltage-controlled oscillator through the charge sharing filter; the second output end of the phase frequency detector is connected with the second input end of the adjustable voltage-controlled oscillator through the phase-locked loop proportional path module; the phase-locked source has the beneficial effects of high flexibility and low power consumption, and is suitable for the technical field of phase-locked sources.

The application discloses a source line abnormality detection circuit and method based on charge sharing. The circuit comprises a source drive array, a display panel, a comparator and a reference module. The application adds a reference capacitor with a capacitance not greater than the parasitic capacitance of the source line, and converts the size of the parasitic capacitance of the source line which is difficult to directly measure into a detection voltage which can be compared with a reference voltage by using the voltage division principle after charge sharing, so that the faults such as disconnection or short circuit with adjacent lines of the source line can be accurately judged. The application realizes online and non-invasive abnormality monitoring of the source line, and can effectively improve the reliability and maintainability of the display chip and the display panel.

The embodiment of the present application discloses a display panel and a display device, in the display panel, two columns of sub-pixels arranged adjacently are connected to one data line and receive data signals of opposite polarities respectively, two scanning lines arranged adjacently constitute a group of scanning lines and are connected to sub-pixels in the same row, during a frame image display period, the sub-pixels in the same row connected to the same group of scanning lines receive the scanning signals from the two scanning lines simultaneously during a first period before receiving the data signals, the sub-pixels in the same row connected to the same data line are electrically connected through the data line, and are adjusted to a first reference potential through charge sharing, thereby effectively improving the rate of the sub-pixels when loading the data signals subsequently while reducing the power consumption correspondingly. The embodiment of the present application also provides an image display method of the aforementioned display device.

The present disclosure provides a control method of a sense amplifier and a memory. The sense amplifier includes a pre-charge phase, an offset cancellation phase, a charge sharing phase and a sense amplification phase. In the offset cancellation phase, a first power terminal is controlled to be connected to a power voltage, a second power terminal is controlled to be connected to a ground voltage, and the sense amplifier is controlled to form a compensation voltage on a bit line and a complementary bit line; a duration of the offset cancellation phase is an optimal offset cancellation duration, and a sensing margin of the sense amplifier is a maximum value at the optimal offset cancellation duration. In the sense amplification phase, the first power terminal is controlled to be connected to the power voltage, the second power terminal is controlled to be connected to the ground voltage, and a time when the first power terminal is connected to the power voltage is later than a time when the second power terminal is connected to the ground voltage, and the sense amplifier is controlled to amplify a voltage difference on the bit line and the complementary bit line.

The invention provides a phase-locked loop rapid locking circuit structure and a control method thereof, the circuit structure comprises a voltage-controlled oscillator, a frequency divider, a phase discriminator and a rapid locking loop filter, and the rapid locking loop filter comprises a capacitive digital-to-analog conversion module. According to the invention, the capacitive digital-to-analog converter module is adopted, and the control voltage of the voltage-controlled oscillator can be rapidly and accurately set based on the charge sharing principle, so that rapid locking is realized; moreover, the structure multiplexes the capacitor in the loop filter, and does not need an extra area. The method has the advantages of high precision, low power consumption and low cost, and has extremely high application value and potential.

An SRAM cell includes a first pass gate transistor connected with a first word-line and a local bit-line, a first inverter that includes an output terminal connected with the first pass gate transistor and an input terminal, a second inverter that includes an input terminal connected with the first pass gate transistor and an output terminal, a second pass gate transistor connected with a second word line, the input terminal of the first inverter and the output terminal of the second inverter, and a complementary local bit-line, a first transistor connected with the second pass gate transistor, a local computing line, and a ground electrode, and a second transistor connected with a third word-line, the local computing line, and the ground electrode.

A data driver according to an embodiment and a display device including the same are disclosed. The data driver includes a voltage output circuit including a first amplifier configured to amplify input positive pixel data and output the amplified positive pixel data as a positive data voltage and a second amplifier configured to amplify negative pixel data and output the amplified pixel data as a negative data voltage; a selection circuit configured to alternately connect the first amplifier and the second amplifier to a first data line and a second data line, and connect the first and second data lines before polarities of data voltages that are applied to the first and second data lines are inverted; and a control circuit configured to vary a charge sharing time for connecting the first and second data lines and performing charge sharing according to change in grayscale of the input pixel data.

The present invention proposes a dynamic comparator offset calibration circuit based on an adjustable charge pump, comprising: a comparator, a charge pump circuit, and a logic control circuit. The calibration input of the comparator serves as the output of the circuit, the output of the comparator is connected to the input of the charge pump circuit, and the control end of the charge pump circuit is connected to the output of the logic control circuit. Whenever the output of the comparator changes, the logic control circuit generates a corresponding pulse to control the on / off switching of the charge pump circuit to adjust the charge and discharge rate of the charge pump. The present invention implements a novel calibration technique for high-speed dynamic comparators. The circuit utilizes an adjustable charge pump circuit based on capacitor charge sharing to control the calibration process, thereby reducing the offset voltage of the comparator. The selection of such a value provides a sufficient calibration range and generates negligible calibration noise.

A display driving circuit and a display driving method are provided. The display driving circuit includes a controller, a common voltage supply circuit, and a border voltage supply circuit. The controller generates a plurality of border voltage control signals and a plurality of common voltage control signals. The common voltage supply circuit outputs a common voltage to the display panel according to the plurality of common voltage control signals. The border voltage supply circuit outputs a border voltage to the display panel according to the plurality of border voltage control signals. When a voltage polarity of the common voltage is reversed, the common voltage supply circuit performs charge sharing by a common ground voltage.

The application provides an in-memory computing circuit and method and a resistance change type memory, the first transistor and the second transistor in the jth memory cell adopt a common gate and common source connection mode, so that the i bit line, the i complementary bit line and the i source line share charges, compared with the existing current convergence-based computing mode, the application provides no direct current in the computing process, solves the problem of excessive current convergence in the prior art, and reduces the power consumption of the in-memory computing circuit. The voltage on the i source line connected with the i voltage reading circuit is the result of the input value of the word line minus the positive and negative product of the memory cell, without the need to set more reading structures, thereby saving the occupied area and delay overhead of the in-memory computing circuit. Due to the connection mode of the memory cell and the bit line, the source line and the complementary bit line, the in-memory computing process is essentially equivalent to the calculation of a differential signal, thereby being able to suppress the influence of non-ideal factors such as process fluctuation on the calculation accuracy.

The present disclosure relates to a data driver and a display device including the same, the data driver including: a register unit configured to sample and output sequentially input image data in each horizontal period; a latch unit configured to latch the image data output from the register unit, and output the image data in synchronization with a latch output control signal; a digital-to-analog converter configured to convert the image data output from the latch unit into a gamma compensation voltage so as to generate a data voltage; a plurality of output buffers configured to sequentially output the data voltage generated by the digital-to-analog converter to a data line; buffer switching elements that connect the output buffers to the data lines, respectively, in response to source output enable signals; a charge sharing circuit configured to control a connection between at least one charge sharing line and the data line; and a calculation unit configured to generate a control signal based on a gradation value of the image data output by the latch unit, the control signal configured to control the charge sharing circuit.