79 results about "Charge sharing" patented technology

The invention relates to the technical field of analog and digital-analog hybrid integrated circuits, and discloses a bootstrap sampling switch circuit with a pre-charging function and an analog-to-digital converter. The circuit comprises a sampling switch module and a time sequence control module. The sampling switch module sequentially works at a holding phase, a pre-charging phase and a tracking phase under the control of a multi-phase clock signal generated by the time sequence control module, the pre-charging phase is added before the tracking phase, the grid voltage of a sampling switch is pre-boosted, and the pre-charging time is dynamically controlled by using an adjustable clock circuit, so that the pre-charging time of the sampling switch is dynamically controlled. Therefore, the charge sharing effect caused by the gate parasitic capacitance is effectively suppressed. The analog-to-digital converter comprises the sampling switch circuit. The linearity and the conduction characteristic of the sampling switch are remarkably improved, and the sampling switch has excellent time sequence configurability and is suitable for a high-speed and high-precision analog-to-digital conversion system.

A bit line charge sharing precharge circuit is provided that precharges a bit line pair during a charge sharing period in which the bit line pair is isolated from a memory power supply voltage. Prior to the charge sharing period, one of the bit lines in the bit line pair was charged to the memory power supply voltage whereas a remaining one was either fully or partially discharged. Charge thus flows from the charged bit line to the discharge bit line during the charge sharing period to precharge the bit lines for a current read or write operation.

The present application relates to the field of analog integrated circuit technology, and particularly relates to a kind of sampling and holding circuit based on noise cancellation.The present application handles sampling noise by introducing noise cancellation technology, input signal is directly connected to the upper plate of C1, C1 samples during S1 switch is closed;The output end of operational amplifier is connected with the lower plate of C2 through S2 switch, C2 samples sampling noise during S2 switch is closed, C2 two ends are connected with C1 two ends through S3 switch, C1 and C2 share charge during S3 switch is closed;Dynamic operational amplifier output end is connected with latch at the same time, so as to use operational amplifier as the preamplifier of comparator.The present application effectively suppresses the deterioration of sampling noise under the condition of reducing sampling capacitor, and dynamic operational amplifier greatly reduces the power consumption and noise of sampling and holding after introducing operational amplifier, and C2=C3 can also be set to make the gain of dynamic operational amplifier in noise elimination stage and subsequent as comparator preamplifier be equal, further improve the precision of circuit.

The invention provides a PLL loop bandwidth adjusting circuit, a control method and a circuit board. The PLL loop bandwidth adjusting circuit comprises a phase frequency detector, a charge sharing filter, a phase-locked loop proportional path module and an adjustable voltage-controlled oscillator. The input end of the phase frequency detector is connected with a reference signal; the first output end of the phase frequency detector is connected with the first input end of the adjustable voltage-controlled oscillator through the charge sharing filter; the second output end of the phase frequency detector is connected with the second input end of the adjustable voltage-controlled oscillator through the phase-locked loop proportional path module; the phase-locked source has the beneficial effects of high flexibility and low power consumption, and is suitable for the technical field of phase-locked sources.

The application discloses a source line abnormality detection circuit and method based on charge sharing. The circuit comprises a source drive array, a display panel, a comparator and a reference module. The application adds a reference capacitor with a capacitance not greater than the parasitic capacitance of the source line, and converts the size of the parasitic capacitance of the source line which is difficult to directly measure into a detection voltage which can be compared with a reference voltage by using the voltage division principle after charge sharing, so that the faults such as disconnection or short circuit with adjacent lines of the source line can be accurately judged. The application realizes online and non-invasive abnormality monitoring of the source line, and can effectively improve the reliability and maintainability of the display chip and the display panel.

The embodiment of the present application discloses a display panel and a display device, in the display panel, two columns of sub-pixels arranged adjacently are connected to one data line and receive data signals of opposite polarities respectively, two scanning lines arranged adjacently constitute a group of scanning lines and are connected to sub-pixels in the same row, during a frame image display period, the sub-pixels in the same row connected to the same group of scanning lines receive the scanning signals from the two scanning lines simultaneously during a first period before receiving the data signals, the sub-pixels in the same row connected to the same data line are electrically connected through the data line, and are adjusted to a first reference potential through charge sharing, thereby effectively improving the rate of the sub-pixels when loading the data signals subsequently while reducing the power consumption correspondingly. The embodiment of the present application also provides an image display method of the aforementioned display device.

The invention provides a phase-locked loop rapid locking circuit structure and a control method thereof, the circuit structure comprises a voltage-controlled oscillator, a frequency divider, a phase discriminator and a rapid locking loop filter, and the rapid locking loop filter comprises a capacitive digital-to-analog conversion module. According to the invention, the capacitive digital-to-analog converter module is adopted, and the control voltage of the voltage-controlled oscillator can be rapidly and accurately set based on the charge sharing principle, so that rapid locking is realized; moreover, the structure multiplexes the capacitor in the loop filter, and does not need an extra area. The method has the advantages of high precision, low power consumption and low cost, and has extremely high application value and potential.

A data driver according to an embodiment and a display device including the same are disclosed. The data driver includes a voltage output circuit including a first amplifier configured to amplify input positive pixel data and output the amplified positive pixel data as a positive data voltage and a second amplifier configured to amplify negative pixel data and output the amplified pixel data as a negative data voltage; a selection circuit configured to alternately connect the first amplifier and the second amplifier to a first data line and a second data line, and connect the first and second data lines before polarities of data voltages that are applied to the first and second data lines are inverted; and a control circuit configured to vary a charge sharing time for connecting the first and second data lines and performing charge sharing according to change in grayscale of the input pixel data.

A display driving circuit and a display driving method are provided. The display driving circuit includes a controller, a common voltage supply circuit, and a border voltage supply circuit. The controller generates a plurality of border voltage control signals and a plurality of common voltage control signals. The common voltage supply circuit outputs a common voltage to the display panel according to the plurality of common voltage control signals. The border voltage supply circuit outputs a border voltage to the display panel according to the plurality of border voltage control signals. When a voltage polarity of the common voltage is reversed, the common voltage supply circuit performs charge sharing by a common ground voltage.

The application provides an in-memory computing circuit and method and a resistance change type memory, the first transistor and the second transistor in the jth memory cell adopt a common gate and common source connection mode, so that the i bit line, the i complementary bit line and the i source line share charges, compared with the existing current convergence-based computing mode, the application provides no direct current in the computing process, solves the problem of excessive current convergence in the prior art, and reduces the power consumption of the in-memory computing circuit. The voltage on the i source line connected with the i voltage reading circuit is the result of the input value of the word line minus the positive and negative product of the memory cell, without the need to set more reading structures, thereby saving the occupied area and delay overhead of the in-memory computing circuit. Due to the connection mode of the memory cell and the bit line, the source line and the complementary bit line, the in-memory computing process is essentially equivalent to the calculation of a differential signal, thereby being able to suppress the influence of non-ideal factors such as process fluctuation on the calculation accuracy.

The present disclosure relates to a data driver and a display device including the same, the data driver including: a register unit configured to sample and output sequentially input image data in each horizontal period; a latch unit configured to latch the image data output from the register unit, and output the image data in synchronization with a latch output control signal; a digital-to-analog converter configured to convert the image data output from the latch unit into a gamma compensation voltage so as to generate a data voltage; a plurality of output buffers configured to sequentially output the data voltage generated by the digital-to-analog converter to a data line; buffer switching elements that connect the output buffers to the data lines, respectively, in response to source output enable signals; a charge sharing circuit configured to control a connection between at least one charge sharing line and the data line; and a calculation unit configured to generate a control signal based on a gradation value of the image data output by the latch unit, the control signal configured to control the charge sharing circuit.

The application relates to the technical field of liquid crystal display panels, and discloses a driving method of an asymmetric gamma liquid crystal display panel, wherein for a certain source chip, the gray scale data transmitted to the adjacent two rows of pixel units by a certain source line of the source chip are D1 and D2 respectively; if D1 is not equal to D2, the source line CH1 is called a gray scale change source line; an external charge sharing judgment condition is that the gray scale change source lines of the source chip CH account for more than one third of all the source lines of the source chip CH; if the external charge sharing judgment condition is met, the following charge sharing action is performed: charge sharing is performed between all the source lines of the source chip CH, and charge sharing is performed with the source lines of other source chips; and the asymmetric gamma liquid crystal display panel can achieve better charge sharing effect.

The invention provides a display device and a display driving device and an operation method thereof. The display equipment comprises a display panel, a touch driving device and a display driving device. The touch driving device drives the display panel to detect a touch event. The display driving device generates a plurality of gate clocks for a gate driving circuit of the display panel. The display driving device generates these gate clocks in a first scan sub-period of the same frame period to deactivate the charge sharing function. The display driving device generates these gate clocks while enabling a charge sharing function in a second scan sub-period of the same frame period.

The invention relates to the technical field of integrated circuit design, in particular to a charge domain linear weighting circuit based on a capacitor network. According to the invention, the capacitor network meeting the binary proportion is constructed to cooperate with sequential control, weighting is directly realized in a charge sharing mode, a complex analog weighting process is converted into a series of charge sharing operations, the output analog voltage can be directly sent to a quantization module, and a final digital result is obtained. A high-area and high-power-consumption DAC circuit does not need to be integrated, the weighting process is completed in a charge domain, the physical principle is based on the linear charge conservation and distribution law, and high precision of multi-bit MAC operation is further guaranteed; and N groups of multiplication operations can be synchronously completed in one clock period by the SRAM row and column partition, so that the operation efficiency of the multi-bit MAC is greatly improved. The method is particularly suitable for in-memory calculation scenes of multi-bit multiply-accumulate (MAC) operation, and can be applied to the fields of edge AI equipment, neural network acceleration chips and the like.

A driving circuit is provided, including first to second output stage circuits that output, respectively, first and second voltages of a first polarity. The driving circuit further includes a first switch having a first terminal receiving the first voltage from the first output stage circuit and a second terminal coupled to a first output channel through a switching circuit, and a second switch having a first terminal receiving the second voltage from the second output stage circuit and a second terminal coupled to a second output channel through the switching circuit. The driving circuit further includes a first charge sharing circuit having a first terminal coupled to the first output channel and a second terminal coupled to the second output channel. The first charge sharing circuit is turned on to provide charge sharing between the first output channel and the second output channel.

The invention provides a sensitive amplification circuit and a control method thereof, a storage device and electronic equipment, relates to the technical field of storage, and can amplify a voltage difference delta V generated after a storage unit performs charge sharing on a bit line so as to reduce the probability that stored data in the storage unit is read by mistake. The sensitive amplification circuit comprises a sensitive amplifier, a pre-amplification circuit, a first switching circuit, a second switching circuit and an amplification input node. The sensitive amplifier comprises a first input end, a second input end, a first output end and a second output end. The amplification input node is connected to a bit line through a pre-amplification circuit. The pre-amplification circuit can amplify a voltage difference generated on a bit line and output the amplified voltage difference to an amplification input node. The first switching circuit can control on-off between the first input end and the amplification input node and on-off between the second input end and the amplification input node, and the second switching circuit can control on-off between the first input end and the first output end and on-off between the second input end and the second output end.

An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit includes, at a first node that receives a power supply reference, a first micro through silicon via (TSV) that traverses through a silicon substrate layer to a backside metal layer. The integrated circuit includes, at a second node that receives the power supply reference, a second micro TSV that physically contacts at least one source region. The integrated circuit includes a first power rail that connects the first micro TSV to the second micro TSV. This power rail replaces contacts between the micro TSVs and a second power rail such as the frontside metal zero (M0) layer. Each of the first power rail, the second power rail, and the backside metal layer provides power connection redundancy that increases charge sharing, improves wafer yield, and reduces voltage droop.

The invention relates to the technical field of electronics, in particular to a device and a method for improving resolution through a combined DAC (Digital-to-Analog Converter). According to the invention, through combination and cooperative control of a plurality of low-resolution DACs, significant resolution jump is realized through a simple logic architecture. The method has the core advantages that the universality is high, the precision of the DAC with any initial resolution can be improved, and the method is not limited by a specific model or framework. Compared with a direct design of a high-resolution DAC, according to the scheme, through capacitor charge sharing and precise time sequence control, the output precision is improved through a simpler circuit structure, the integration difficulty is greatly reduced, a mature module of an existing low-resolution DAC can be directly reused, and the adaptability is excellent. Meanwhile, the scheme omits a complex calibration algorithm and control logic, can stably work by virtue of the charge conservation characteristic of hardware, has the characteristics of low cost, easiness in integration and high reliability while ensuring high resolution, and is suitable for various scenes with high requirements on analog output precision.

The invention provides a high-energy-efficiency digital-analog hybrid CMOS Boolean satisfiability problem solver chip which comprises a solver core, an SRAM peripheral read-write drive circuit and a parallel-to-serial read-out circuit, the SRAM peripheral read-write drive circuit is connected with a processor core and used for reading and writing data, the parallel-to-serial read-out circuit is used for reading a final solution, and the solver core comprises a 218 * 50 processing unit array. The processing units in each column are interconnected through charge sharing lines so as to complete accumulation operation in a charge domain. The processing units in each row are interconnected through TCAM matching lines, and the word and sentence evaluation operation is completed. In addition, a graph coloring circuit is also integrated for grouping Boolean variables. In each iteration, the Boolean variables in the same group can be updated at the same time, so that the parallel computing capability of the solver is improved. The energy efficiency is improved by using a digital-analog hybrid calculation mode, and the degree of parallelism is improved by using a packet updating strategy.

The embodiment of the invention provides a method for performing logical operation based on a memory and the memory. Wherein the logic operation comprises AND logic operation or OR logic operation, and when the AND logic operation or the OR logic operation is executed, the method comprises the following steps: step S11, pre-charging a first bit line and a second bit line to a reference voltage; s12, performing charge sharing on the 3m first storage units and the first bit line, and performing charge sharing on the 3n second storage units and the second bit line at the same time, so as to form a first voltage difference on the first bit line and the second bit line; wherein m + n > = 2, m is a positive integer, and n is a non-negative integer; and step S13, amplifying the first voltage difference on the first bit line and the second bit line through a sense amplifier so as to obtain the AND logic operation or the target result of the logic operation on the first bit line or the second bit line.

The invention provides a circuit and method for modulating PLL loop bandwidth based on a VCO adjustable capacitor and a circuit board. The circuit comprises a phase frequency detector, a charge sharing filter, a phase-locked loop proportional path charge pump and a capacitor adjustable voltage-controlled oscillator. The input end of the phase frequency detector is connected with a reference signal; the first output end of the phase frequency detector is connected with the first input end of the capacitance-adjustable voltage-controlled oscillator through the charge sharing filter; a second output end of the phase frequency detector is connected with a second input end of the capacitance-adjustable voltage-controlled oscillator through the phase-locked loop proportional path charge pump; the capacitance-adjustable voltage-controlled oscillator comprises a capacitor bank and a VCO circuit module which are connected in parallel, the parallel connection point of the capacitor bank and the VCO circuit module is connected with the positive and negative output ends VOUT + and VOUT-of the capacitor adjustable voltage-controlled oscillator; the phase-locked source has the beneficial effects of high flexibility and low power consumption, and is suitable for the technical field of phase-locked sources.

The present application relates to the technical field of DRAM circuit design, and particularly relates to a sensitive amplifier, a reading circuit and a module based on capacitance and turnover point compensation. The present application discloses a sensitive amplifier based on capacitance and turnover point compensation, comprising: 9 NMOS tubes M1-M9, 2 PMOS tubes P1-P2, and 2 capacitors C1-C2. The present application designs a CSCSA and cooperates with corresponding control logic, so that when reading a DRAM storage unit, the present application designs a pre-charge stage, an offset elimination stage, a charge sharing stage, a pre-sense stage and a sense amplification stage, so that the potential of a bit line BL or BLB can be correctly changed, and the reading amplification function of the CSCSA is ensured. Compared with the traditional DRAM sensitive amplifier, the CSCSA provided by the present application can greatly reduce the offset voltage index and improve the sensing yield under the condition that the number of components is not greatly increased.

The invention discloses an anti-radiation linear voltage regulator and an anti-radiation electronic device. A first sensitive node and a second sensitive node in an amplifier module and a third sensitive node in a bias mirror current module are respectively provided with at least two split branches; split branches in each sensitive node area are arranged in a discrete layout mode in a physical space, and a single event effect is reduced or eliminated through a circuit split multipath and physical space charge sharing technology mode, so that the single event effect is reduced or eliminated under the state that redundant circuits are not increased and the chip area is not sacrificed; and the reinforcement design work of the anti-radiation linear voltage regulator is completed.

Embodiments of the present application provide a method for performing a logic operation based on a memory, and a memory; wherein the logic operation includes an AND logic operation or an OR logic operation; when performing the AND logic operation or the OR logic operation, the method comprises: step S11, pre-charging a first bit line and a second bit line to a reference voltage; step S12, causing 3m first storage units to perform charge sharing with the first bit line, and simultaneously causing 3n second storage units to perform charge sharing with the second bit line, to form a first voltage difference on the first bit line and the second bit line; wherein m+n≥2, m is a positive integer, and n is a non-negative integer; step S13, amplifying the first voltage difference on the first bit line and the second bit line by a sense amplifier, to obtain a target result of the AND logic operation or the OR logic operation on the first bit line or the second bit line.

A gate driver circuit and an operating method thereof are provided. The gate driver circuit includes a charge sharing circuit including a first resistor, a second resistor, a first capacitor, a second capacitor, a first switching transistor, and a second switching transistor. A first terminal of the first resistor is coupled to a first working voltage. A first terminal of the first capacitor is coupled to a second terminal of the first resistor, and a second terminal is coupled to a second working voltage. A first terminal of the first switching transistor is coupled to the second terminal of the first resistor and the first terminal of the first capacitor, and a second terminal is coupled to a circuit node. A first terminal of the second switching transistor is coupled to the circuit node.

A data driver according to an embodiment and a display device including the data driver are disclosed. The data driver includes: a voltage output circuit including a first amplifier and a second amplifier, the first amplifier being configured to amplify input positive pixel data and output the amplified positive pixel data as a positive data voltage, and the second amplifier being configured to amplify negative pixel data and output the amplified negative pixel data as a negative data voltage; a selection circuit configured to selectively connect the first amplifier and the second amplifier to a first data line and a second data line, and to connect the first data line and the second data line before the polarity of the data voltage applied to the first data line and the second data line is reversed; and a control circuit configured to change the charge sharing time for connecting the first data line and the second data line and performing charge sharing according to the grayscale change of the input pixel data.

The application discloses a kind of based on floating space dynamic amplifier and charge sharing's switched capacitor integrator, including the sampling module, integral module and charge sharing module connected in turn, wherein, sampling module is according to from the first enable signal, second enable signal, third enable signal and fourth enable signal from outside in sampling stage collection differential signal from outside, store differential signal, and in integral stage differential signal is output to integral module;Integral module is according to the first enable signal and fourth enable signal control operational amplifier in integral module in sampling stage charging and stop running, in integral stage differential signal is integrated;Charge sharing module is according to from the fifth enable signal from outside, in integral stage integral differential signal is stored and in next sampling stage output.The application is by designing operational amplifier, the circuit structure of charge sharing module and corresponding enable signal, reduce the overall power consumption of device and guarantee the precision of integrator.

The power voltage generator includes a voltage sensor and a power circuit breaker. The voltage sensor is configured to sense a first voltage during a first charge-sharing period of the gate clock signal and a second voltage during a second charge-sharing period of the gate clock signal. The power circuit breaker is configured to disconnect power based on the first and second voltages.

This invention relates to the field of DRAM circuit design technology, specifically to a sensitive amplifier, readout circuit, and module based on bit-line switches and capacitive coupling. The invention discloses a DRAM sensitive amplifier based on bit-line switches and capacitive coupling, comprising: nine NMOS transistors N1-N9, two PMOS transistors P1-P2, and two capacitors Cc1-Cc2. This invention designs a Selective Sensing Amplifier (SCSA) and, with corresponding control logic, incorporates a pre-charge phase, offset calibration phase, charge sharing phase, pre-sensing phase, and main sensing phase during DRAM memory cell readout. This ensures that the bit line BLT or BLB potential changes correctly, guaranteeing the SCSA readout amplification function. Compared to traditional DRAM sensitive amplifiers, the SCSA provided by this invention achieves a significant reduction in offset voltage and effectively increases sensing margin with only a small increase in the number of components.