845 results about "Charge sharing" patented technology

A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time, thereby to generate a Boolean function output of the data of the at least two cells, wherein each of the at least two cells includes at least a storage capacitor, a storage transistor and a read line, where the storage transistor is connected to the read line and subject to activation by a charge in the storage capacitor.

An enhanced frame buffer pixel circuit with two control transistors and a separate capacitor put in as a memory capacitor before the memory transistor yields a high contrast ratio by removing induced charge and solving a charge sharing problem between the memory capacitor and the liquid crystal display (LCD) capacitor. The memory transistor may be made of either CMOS or PMOS. The frame buffer pixel can be used to drive binary displays which expresses ON and OFF only if a comparator is put in after the pixel electrode circuit to represent gray levels with reduced sub-frame frequency.

The invention is a capacitance fingerprint access chip, it includes capacitance sensing array which is arranged with planar type and a dynamic random access memory peripheral circuit. The device usesDRAM charge sharing theory to examine the apex and the vale of the fingerprint. The peripheral circuit outputs the result of each capacitance sensor. The manufacturing method belongs to integrate circuit craft, especially the CMOS craft. The invention can be biological identification of people, applies to notebook PC, personal digital assistant and mobile.

A capacitive fingerprint sensor includes a plurality of capacitive sensing members arranged in a 2D array. A charge-sharing principle is utilized to read signals in the capacitive sensing member. Each capacitive sensing member includes an insulating surface layer, a sense electrode, a reference electrode, a reference capacitor, and a signal reading circuit. The sense electrode is below the insulating surface layer. When a finger contacts the insulating surface layer, a sense capacitor is formed therebetween. The reference capacitor is connected between the reference and sense electrodes. The signal reading circuit is connected to the sense and reference electrodes, repeatedly provides control signals to charge the reference capacitor and then enable the reference and sense capacitor to share charges. Finally, the sense voltage of the sense electrode may be read.

According to different embodiments of the present invention, various methods, devices and systems are described for managing power in charge pumps in a non-volatile memory system having a high voltage charge pump and associated regulator. A method includes the following operations, receiving an operation command corresponding to an operation, pumping up a charge pump output voltage to a desired output voltage, turning off the regulator and the charge pump when the output voltage is approximately the desired output voltage compensating for charge sharing by turning on the charge pump and setting a pump clock rate to a slow clock rate in order to avoid overshooting the desired output voltage by the charge pump while the operation is being carried out, and compensating for junction leakage by turning on the regulator and the charge pump until the charge pump output voltage is the desired output voltage.

A liquid crystal display device with a charge sharing function is suitable for reducing the power consumption below a predetermined limit. In the liquid crystal display device, a pair of pixels adjacent along the data line is charged with pixel data voltages of polarity opposite to that of another pair of pixels adjacent to the pair of the pixels. A charge sharing unit selectively allows the data lines to share charges at intervals between periods in which the pixel data voltages are supplied to the pair of the pixels adjacent along the data line.

A method for correcting at least one of pileup effects or charge sharing effects in multi-cell photon counting detectors includes determining a correction coefficient using a count rate of an entire spectrum and applying the determined correction to the counts recorded in an energy window of interest.

A liquid crystal display having data driving apparatus comprising first and second output switches, a charge sharing line, and first and second charge sharing switches. The first output switch switches an electrical connection between a first amplifier providing a positive gradation voltage and a first data line in response to a control signal. The second output switch switches an electrical connection between a second amplifier providing a negative gradation voltage and a second data line in response to the control signal. The first charge sharing switch switches an electrical connection between the first data line and the charge sharing line in response to the control signal. The second charge sharing switch switches an electrical connection between the second data line and the charge sharing line in response to the control signal.

A hybrid Analog-to-Digital Converter (ADC) has a binary-weighted capacitor array and a sub-voltage capacitor array that are coupled together by a coupling capacitor. The sub-voltage capacitor array uses a minimum capacitor size that matches the minimum capacitor size of the binary-weighted capacitor array. The coupling capacitor is double the minimum size and reduces a voltage effect on a charge sharing line by half. Second coupling capacitors in the sub-voltage capacitor array each reduce the voltage effect by half, so that first, second, and third sub-voltage capacitors in the sub-voltage capacitor array produce ½, ¼, and ⅛ voltage swings using the minimum size capacitance. Only MSB capacitors in the binary-weighted capacitor array sample the analog input voltage. During conversion, MSB's from a Successive-Approximation-Register (SAR) are applied to binary-weighted capacitors while LSB's are applied to sub-voltage capacitors. The total capacitance is reduced by applying the LSB's only to the sub-voltage capacitor array.

A voltage generating circuit for a semiconductor memory device. The voltage generating circuit includes a multi-boosting unit for stepping up a power supply voltage, a transfer transistor connected to a final boosting node of the multi-boosting unit and an output node, and a charge-sharing element, electrically connected to the final boosting node and a gate node of the transfer transistor, enabled during at least a part of the period the power supply voltage is stepped-up by the multi-boosting unit and performing charge sharing between the final boosting node and the gate node of the transfer transistor.

A circuit and method are given, to realize a high efficiency voltage multiplier for integrated circuits generating an internal and flexible positive or negative high voltage on-chip supply voltage from low external positive or negative supply voltages or ground. Applying multi-phase control signals to voltage boost internal nodes allows for eliminating threshold voltage drop losses and thus improves the voltage pumping gain compared to circuits with diode-configured FETs of prior art. Making use of voltage signals from antecedent stages in order to bias the bulk of MOS transistors fabricated in triple-well technology enables relaxing of the gate oxide stress within high order stage MOS transistors. Such a method, called leap-frog bulk potential tracking method, makes MOS transistors from different stages exhibit about the same body effect, which is very important because MOS transistors of higher order stages now show the same performance as MOS transistors from lower order stages. Important also in terms of efficiency as the charge sharing speed of high order MOS transistors always dominates the total charge pump performance and the driving force of pumped currents, thus also allowing for a greater number of serially connectable stages overall or a smaller number necessary for a certain targeted output voltage.

An image sensor including an array of pixel elements is operated according to two operation modes to modulate the conversion gain of the pixel to operate the image sensor based on the impinging light conditions. More specifically, an image sensor pixel element is operated in a high conversion gain mode for low light conditions and in a low conversion gain mode for bright light conditions. The low conversion gain mode implements charge sharing between the floating diffusion and the photodiode. The low conversion gain mode further implements partial reset where the photodiode and the floating diffusion are reset to the same potential and to a potential slightly less than the pinning voltage of the photodiode.

This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal3 global bit lines (GBLs), divided metal2 Segment bit lines (SBLs), and divided metal1 block bit lines (BBLs) laid out in parallel to each other respectively for a plurality of NAND Strings. All other source lines or power lines connected to bottoms of corresponding String capacitances of GBLs, SBLs, and BBLs are associated with metal0 line laid out perpendicular to those BLs. Under the HiNAND array scheme, conventional one-WL Read and Program-Verify operations are replaced by multiple-WL and All-BL Read and Program-Verify operations executed with charge capacitance of SBLs being reduced to 1 / 10- 1 / 20 of capacitance of GBLs to achieve DRAM-like faster operation, less operation stress, and lower power consumption. A preferred set of program biased voltages on the selected WL and remaining non-selected WLs associated with a Multiplier and a DRAM-like charge-sharing Latch Sensing Amplifier is proposed.

A liquid crystal display includes first and second gate lines, a data line crossing the first and second gate lines, a pixel electrode including first and second sub-pixel electrodes electrically disconnected from each other, a first thin film transistor connected to the first gate line, the data line, and the first sub-pixel electrode, a second thin film transistor connected to the first gate line, the data line, and the second sub-pixel electrode, and a third thin film transistor connected to the second gate line, the second sub-pixel electrode, and a charge sharing capacitor including a first and second electrode. A data voltage applied to the second sub-pixel electrode and to a first electrode swings between a negative voltage and a positive voltage with respect to a common voltage, and a voltage smaller than an average value of the negative voltage and the positive voltage is applied to a second electrode.

The disclosure provides a gate driving circuit on array applied to a display panel with charge sharing pixel structure. In particular, the gate driving circuit is adapted to receive multi-phase clock signal and includes a plurality of shift registers. Each shift register includes a driving circuit including a first driving transistor and a second driving transistor, a pull-down unit and at least one pull-up unit, so that is capable of generating mutually non-overlapped main gate driving signal and sub gate driving signal. Furthermore, the advantage of the disclosure is to provide a gate driving circuit with simplified circuit structure and circuit layout.

A method is provided for driving a liquid crystal display having a multi-channel single-amplifier structure, where the number of times of coupling according to video signals transmitted to adjacent source lines while the source lines are floated is 3 and it is equal for the respective source lines for 6 frames, noise aspects of the respective source lines are similarly repeated for every 6 frames, kick-back noise compensation is uniformly applied to the source lines S_r, S_g and S_b with noise of the 6 frames averaged, and charge sharing time of parasitic capacitors between the source lines and charge sharing time of capacitors of liquid crystal cells become similar to each other.

There is provided a TFT-LCD using multi-phase charge sharing, in which odd-numbered source lines and even-numbered source line are connected to an external capacitor through a switching element during a period of multi-phase charge sharing time, to share the charges charged in the source lines. The TFT-LCD includes: a source driver for outputting video data signals each of which corresponds to one pixel through a plurality of source lines; switching elements for multi-phase charge sharing; and an external capacitor, connected between a liquid crystal panel and the source driver, for collecting charges of a source line having a voltage higher than a common electrode voltage and supplying them to a source line having a voltage lower than the common electrode voltage when the source lines are connected thereto.

A pixel structure includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first switching transistor and a first liquid crystal capacitor, wherein when the first switching transistor is turned on, the first liquid crystal capacitor is biased to a first gray level voltage. The second sub-pixel includes a second switching transistor, a second liquid crystal capacitor, a third switching transistor, a charge sharing capacitor and a fourth switching transistor, wherein when the second switching transistor is turned on, the second liquid crystal capacitor is biased to the first gray level voltage; when the fourth switching transistor is turned on, the charge sharing capacitor is reset to a predetermined voltage; and when the third switching transistor is turned on, the second liquid crystal capacitor and the charge sharing capacitor are charge-shared to a second gray level voltage through the third switching transistor.

The invention provides a liquid crystal display pixel drive circuit and a TFT (thin film transistor) substrate. The liquid crystal display pixel drive circuit comprises a plurality of sub-pixels in array arrangement, wherein each sub-pixel comprises a main area TFT, a main area charge-sharing thin-film transistor, a secondary area TFT, a secondary area charge-sharing TFT, a main area storage capacitor, a secondary area first storage capacitor, a main area liquid crystal capacitor and a secondary area liquid crystal capacitor, wherein the main area charge-sharing TFT and the secondary area charge-sharing TFT are connected to first array substrate and second array substrate common voltage separately; the common voltage of the liquid crystal display is adjusted through the size of the first array substrate and second array substrate common voltage, so that the optimum common voltage adjustment difficulty and accuracy of the liquid crystal display can be reduced, and the optimum common voltage adjustment difficulty and display effect of the liquid crystal display are improved.

A method for charge sharing between source lines of a pixel array. The method includes the steps of grouping the source lines into pairs, implementing charge sharing if data polarities of a currently and a last scanned row are different; otherwise, in each pair of the source lines, estimating a first and second energy driving the two source lines respectively with and without a preliminary charge sharing, and implementing charge sharing only if the first energy is smaller than the second energy.

A radiation detector system is provided including a semiconductor detector, plural pixelated anodes, and at least one processor. At least one of the pixelated anodes is configured to generate a collected charge signal corresponding to charge collected by the pixelated anode and to generate a non-collected charge signal corresponding to charge collected by an adjacent anode. The at least one processor includes a tangible and non-transitory memory having stored thereon instructions configured to direct the at least one processor to determine a collected value for the collected charge signal, to determine a non-collected value for the non-collected charge signal, determine a calibrated value for the non-collected charge signal, determine a total charge produced by a charge sharing event using the collected value and the calibrated value, and count the charge sharing event as a single event if the total charge exceeds a predetermined value.

A liquid crystal display includes first and second gate lines arranged in parallel to each other and sequentially transmitting a gate voltage, a data line crossing the first and second gate lines and transmitting a data voltage, a pixel electrode constituted by first and second sub-pixel electrodes and electrically disconnected from each other, a first switching element connected to the first gate line, the data line, and the first sub-pixel electrode, a second switching element connected to the first gate line, the data line, and the second sub-pixel electrode, a third switching element connected to the first sub-pixel electrode across a charge-sharing capacitor, and a fourth switching element connected to the second gate line and the second sub-pixel electrode and connected to the first sub-pixel electrode across the charge-sharing capacitor.

The present invention relates to a technique for outputting threshold voltages by properly changing the threshold voltages such that the threshold voltages can protect low-voltage driving elements within an analog to digital converter when the threshold voltages of an OLED display panel are sensed and outputted to the analog to digital converter. The present invention comprises: a sampling capacitor which samples threshold voltages sensed and inputted from an organic light-emitting diode on a display panel; a charge-sharing capacitor which charges and shares the threshold voltages sampled from the sampling capacitor, or solely charges the threshold voltages to bypass the threshold voltages; and a sample-and-hold unit which has a plurality of switches for performing switching operations for the sampling operation of the sampling capacitor and the charging and the sharing of the charge-sharing capacitor, and scales the threshold voltages to threshold voltage areas having a certain value or less.

The present invention provides an internal voltage generator including a high efficient charge pump. The internal voltage generator includes an oscillation signal generator for receiving a reference voltage and a pumping voltage to thereby output an oscillation signal, a pump control logic for outputting a pumping control signal and a precharge signal in response to the oscillation signal, and a charge pump for precharging the pair of bootstrapping node by connecting the pair of bootstrapping node in response to the precharge signal to thereby generate the pumping voltage of a predetermined level after precharging the pair of bootstrapping node into a level of the power supply voltage and charge sharing the pair of bootstrapping node and the pumping voltage in response to the precharge signal. Herein, the pumping control signal controls a pumping operation and the precharge signal precharges a pair of bootstrapping node for generating the pumping voltage by pumping a power supply voltage.

In at least one embodiment of the present invention, deterioration of display quality is prevented from occurring in a display device provided with an active matrix substrate even when a larger size or a higher resolution is employed and a drive frequency is increased. In an active matrix substrate of a liquid crystal display device, a charge sharing control signal line is disposed so as to be arranged along each gate line and charge sharing TFTs are provided for each source line in numbers equal to the number of the gate lines. The gate terminal of the charge sharing TFT is connected to the charge sharing control signal line and the source and drain terminals are connected with neighboring source lines via connection electrode portions, respectively. Each of the charge sharing control signal lines is provided with a signal which turns on the charge sharing TFT for a predetermined period of every one horizontal period.

A liquid crystal display includes a liquid crystal display panel having a plurality of data lines, a plurality of gate lines crossing the plurality of data lines, and a plurality of liquid crystal cells, a timing controller to determine gray levels of input digital video data and a time at which a polarity of a data voltage to be supplied to the data lines is inverted, to activate a dynamic charge share control signal to indicate a time at which the gray level of the data voltage is changed from a white gray level to a black gray level and a time at which the polarity of the data voltage is inverted, to detect weakness patterns in which the data of the white gray level and the black gray level are regularly arranged in the input digital video data, and to activate a dot inversion control signal for widening a horizontal polarity inversion period of data voltages to be supplied to the data lines when the weakness patterns are input, a data driving circuit to convert the digital video data from the timing controller into the data voltage, to convert the polarity of the data voltage, to supply any one of a common voltage and a charge share voltage between a positive data voltage and a negative data voltage to the data lines in response to the dynamic charge share control signal, and to widen the horizontal polarity inversion period of the data voltages in response to the dot inversion control signal, and a gate driving circuit to sequentially supply a scan pulse to the gate lines under the control of the timing controller.

There is provided a method for driving the TFT-LCD using multi-phase charge sharing, in which odd-numbered source lines and even-numbered source lines are connected to an external capacitor through a switching element during a period of multi-phase charge sharing time, to share the charges charged in the source lines. The method includes: a first charge sharing step in which even-numbered capacitors, which have been discharged with a voltage VL during a period of (N-1)th gradation expressing time, are charged with the voltage of an external capacitor, VL+(1 / 3)Vswing, according to a second selection signal; a second charge sharing step in which odd-numbered capacitors, which have been charged with a voltage VH during the period of the (N-1)th gradation expressing time, are charged with a voltage VL+(2 / 3)Vswing through charge sharing with the even-numbered capacitors charged with VL+(1 / 3)Vswing by the first charge sharing, according to a third selection signal; and a third charge sharing step in which the odd-numbered capacitors, which should be discharged with VL during a period of the Nth gradation expressing time, are charged with the voltage of the external capacitor, VL+(1 / 3)Vswing, according to a first selection signal.

An add-on adapter 110 enables a single charging port 102 of an electric vehicle charging station 100 to simultaneously charge two electric vehicles. An adapter controller 120 determines the available charging rate offered by the charging station. Electric vehicle charging handles 150A, 150B are determined to be connected to the electric vehicles. A charge sharing control circuit 300 in the adapter controller, determines modified available charging rates to be offered for simultaneously charging the electric vehicles. The modified available charging rates are based on the connection states of the electric vehicles and the available charging rate offered by the charging station. The adapter controller controls two contactors 130A, 130B to switchably connect a charging station power socket to the electric vehicle charging handles, to provide shared power at the determined modified available charging rate to the electric vehicles, for simultaneous charging.

The invention discloses an integrated panel type grid drive circuit applicable for charge sharing pixels. According to the invention, the grid drive circuit on a liquid crystal panel comprises a plurality of shift registers. Each of the shift registers can output non-overlapped main grid drive signals and sub-grid drive signals. Meanwhile, the integrated panel type grid drive circuit is simple in structure and circuit layout.