Semiconductor device and method for fabricating the same

Abstract

Methods for forming semiconductor memory structures including air gaps between adjacent gate structures are provided. The volume of the air gaps is maximized and the width thereof made uniform in order to minimize the parasitic capacitance and any variance therein between the gate structures. The methods include forming an insulation layer between adjacent gate structures and subsequently etching the insulation layer to leave an air gap. Devices fabricated in accordance with the methods are also provided.

Description

[0001] This U.S. non-provisional application claims benefit of priority under 35 U.S.C.§119 from Korean Patent Application No. 2005-0103107, filed on Oct. 31, 2005, the entire contents of which are incorporated herein by reference. BACKGROUND [0002] 1. Technical Field [0003] This disclosure generally relates to semiconductor devices and, more particularly, to semiconductor devices such as memory devices having an air gap defined between adjacent gate structures and methods of fabricating the same. [0004] 2. Description of the Related Art [0005] Among semiconductor devices, non-volatile memory devices are commonly used in consumer electronic devices because information can be retained in the device even when no power is supplied. Advances in consumer electronics cause demand for ever higher density memory devices. Efforts to manufacture devices meeting this demand often involve scaling down the sizes of gate structures and minimizing the space between adjacent gate structures. [0006]...

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Benefits of technology

[0017] As a result, the volume of the air gaps is maximized and the width thereof made uniform in order to minimize the parasitic capacitance and any variance therein between the gate structures.

Problems solved by technology

Unfortunately, these efforts often result in increased parasitic capacitance between adjacent structures in the memory cell regions.

Such increases in parasitic capacitance reduce the speed of the memory devices.

Also, variation in parasitic capacitance between gate structures causes a variation in the threshold voltage for each gate structure, thereby degrading the reliability of memory devices.

One disadvantage of these approaches is that the area between adjacent gates is largely filled with an oxide dielectric layer with a relatively small air pocket.

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