82 results about "Crossbar array" patented technology

The invention relates to a matrix decomposition device and method based on a memristor cross array, which are suitable for efficient hardware implementation of singular value decomposition (SVD), the memristor cross array receives a conductance value mapped by a Grubrum matrix constructed by a to-be-decomposed matrix and a bit line input voltage converted by a bit line column vector, and outputs a corresponding current; converting the corresponding current into a voltage vector; performing normalization processing on the voltage vector to obtain a normalized vector; judging whether convergence occurs or not; performing normalization processing on the steady-state voltage vector to obtain a final output vector; and according to the final output vector, main characteristic values are extracted based on a first normalization circuit, and main singular values and corresponding singular matrixes are calculated. Compared with the prior art, the high parallel computing characteristic of the memristor cross array is utilized, efficient operation and hardware acceleration of matrix decomposition are achieved, the method has the advantages of being low in power consumption, high in speed and good in expansibility, and the method is suitable for application scenes such as artificial intelligence, signal processing and large-scale matrix operation.

The invention is directed to solving an optimization problem. The method operates a photonic crossbar array structure including N input lines and M output lines, which are interconnected at junctions via N×M photonic memory devices, where N≥2 and M≥2. The photonic memory devices are programmed to store respective weights in accordance with the optimization problem. The photonic crossbar array structure is operated as follows. First, the method determines values of L input vectors of N components each, where L≥2. Second, based on the determined values, N electromagnetic signals are generated, where each of the generated signals multiplexes L input signals encoded at respective wavelengths, so as for the N electromagnetic signals to map the L input vectors of N components each. Third, the N electromagnetic signals generated are applied to the N input lines of the photonic crossbar array structure.

The invention is notably directed to a hardware system (1) designed to implement an artificial neural network (ANN). The hardware system basically includes a neural processing apparatus (15), e.g., involving as crossbar array structure, one or more lookup table circuits (17), and one or more processing units (18). The neural processing apparatus is configured to implement M artificial neurons, where M≥1. The lookup table circuits are configured to implement a lookup table (LUT). The system further includes M′ processing units, where M≥M′≥1. Each processing unit is connected by at least one neuron, in order to be able to access a first value outputted by each connected neuron. In addition, each processing unit is connected to a LUT circuit, in order to efficiently access parameter values of a set of parameters from the LUT. Finally, each processing unit is configured to output a second value, corresponding to a value of a mathematical function taking said first value as argument. The mathematical function is otherwise determined by the set of parameters, the parameter values of which are accessed by each processing unit from the LUT, in operation. I.e., the mathematical function is defined (and thus determined) by a set of parameters, the values of which are efficiently retrieved from the hardware-implemented LUT. This results in a substantial acceleration of the computations of the function outputs, beyond the acceleration that may already be achieved within the neural processing apparatus and the processing units themselves. As a result, the neuron outputs can be more efficiently processed, prior to being passed to a next neuron layer. The invention is further directed to a method of operating such a hardware system.

In certain examples, a method may include receiving a privacy parameter and selecting an electrical property range for cells in a crossbar array based on the privacy parameter. The cells in the crossbar array may then be programmed based on the selected electrical property range, which may provide a certain level of differential privacy.

A crossbar circuit including a crossbar array and a periphery circuit is provided. A resistive random-access memory (RRAM) device of the crossbar array includes a bottom electrode fabricated on a first interconnect layer; a top electrode; and a filament-forming layer fabricated between the bottom electrode and the top electrode. A portion of the filament-forming layer and a portion of the top electrode are fabricated in a via in a first etch stop layer. The crossbar circuit further includes a second etch stop layer fabricated on the top electrode and a dielectric layer fabricated on the second etch stop layer. The top electrode is connected to a first metal via of a second interconnect layer fabricated in the second etch stop layer and the dielectric layer. The periphery circuit includes a metal via of the second interconnect layer that is fabricated in the dielectric layer and the first etch stop layer.

A method is presented for artificial neural network training. The method includes storing weight values in an array of resistive processing unit (RPU) devices, wherein the array of RPU devices represents a weight matrix, defining the weight matrix to have an output dimension that is smaller than the input dimension such that the weight matrix has a rectangular configuration, and converting the weight matrix from a rectangular configuration to a more square-shaped configuration by repeating or concatenating the rectangular configuration of the weight matrix to increase a signal strength of a backward pass signal by copying an input of repeated weight elements during a forward cycle pass, summing output computations from the repeated weight elements, updating each of the repeated weight elements according to a backpropagated error or alternatively updating only one of the repeated weight elements by setting all forward values except one to zero during an update pass.

Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a first NMOS transistor; a second PMOS transistor; and an RRAM device. The first NMOS transistor and the second PMOS transistor are in parallel as a pair, wherein the pair connects in series with the RRAM device. The apparatus may further include an inverter, via which the second gate terminal of the second PMOS transistor is connected to the first gate terminal.

The invention proposes a crossbar array with a plurality of vertical and horizontal lines, wherein signals are applied to the horizontal lines that determine the magnitudes of time delays of voltage-controlled time delay elements based on RRAM elements, the delays of which are set by the RRAM elements and by the magnitude of the signals on the horizontal lines, wherein a trigger signal (excitation signal) applied to the time delay element chain of a vertical line is transmitted with a time delay to the other end of said vertical line in order to be measured there by means of a time delay measuring element (for example, TDC), thus making the vertical line readable.

The invention discloses a time-space fusion detector double-reservoir network system based on multi-frame-in-one calculation, and relates to the technical field of bionic intelligent vision and brain-like calculation. The system comprises a photoelectric reservoir layer and an electrical readout layer, and the photoelectric reservoir layer comprises a retina-shaped MoS2 photoelectric detector array and is used for constructing the photoelectric reservoir layer by using the nonlinear continuous photoconduction characteristic of a two-dimensional MoS2 photoelectric detector. Detecting an optical signal and projecting the optical signal into an electrical readout layer with increased dimensions in a photocurrent form of a multi-frame-in-one pattern; the electrical readout layer includes a memristor cross array for processing an input signal in a parallel manner and generating an output result in real time. The system has the advantages of low power consumption, low delay, high recognition precision and the like, and is particularly suitable for complex application scenes such as infrared dynamic moving target recognition.

A crossbar circuit including a crossbar array and a periphery circuit is provided. A resistive random-access memory (RRAM) device of the crossbar array includes a bottom electrode fabricated on a first interconnect layer; a top electrode; and a filament-forming layer fabricated between the bottom electrode and the top electrode. A portion of the filament-forming layer and a portion of the top electrode are fabricated in a via in a first etch stop layer. The crossbar circuit further includes a second etch stop layer fabricated on the top electrode and a dielectric layer fabricated on the second etch stop layer. The top electrode is connected to a first metal via of a second interconnect layer fabricated in the second etch stop layer and the dielectric layer. The periphery circuit includes a metal via of the second interconnect layer that is fabricated in the dielectric layer and the first etch stop layer.

A field programmable computing architecture includes a programmable crossbar array structure including a set of memory components and a control plane coupled to a plurality of inputs and a plurality of outputs of the programmable crossbar array structure, the control plane to configure the programmable crossbar array to perform one or more in-memory arithmetic operations.

The application provides a configurable cross switch circuit and a convolution operation circuit based on the same, the configurable cross switch circuit comprising a read cross switch array in front of an operation unit array and a write cross switch array in front of the operation unit array; input feature maps are introduced into an input memory stack, input into the operation unit array through the read cross switch array, and output feature maps calculated by the operation unit array are written into an output memory stack through the write cross switch; in each cycle, at most only one switch is closed for the same column read switch and the same row write switch. The two-dimensional convolution operation circuit based on the application only needs to introduce the input feature map data into the on-chip memory once, and the two-dimensional convolution operation can be completed, without the need of repeatedly introducing the input feature map data into the memory or transmitting the input feature map data between the memories, so that the performance of the two-dimensional convolution calculation is improved and the energy consumption is reduced.

A wireless radio-frequency receiver (500) comprising multiple antenna elements (511-514) for receiving a radio signal, an analogue beamforming radio circuit (520), a digital baseband processor (530), a first signal path (531) and a second signal path (532) from the multiple antenna elements (511-514) to the digital baseband processor (530), wherein the first signal path comprises the analogue beamforming radio circuit (520) and wherein the second signal path (532), which is at least partly parallel to the first signal path (531), comprises an analogue crossbar array (540), wherein a respective antenna element (511-514) is connected to a corresponding input of the analogue crossbar array (540), the analogue crossbar array (540) being configured to provide output signals that is the result of a matrix multiplication of input signals of the analogue crossbar array (540).

Described herein are techniques to enable tracking circuits for crossbar circuits. One embodiment provides an apparatus including a crossbar array comprising: a plurality of bit lines intersecting with a plurality of word lines; and a plurality of cross-point devices, wherein each of the cross-point devices is connected to at least one of the word lines and at least one of the bit lines; a read-out circuit selectively connected to at least one of the bit lines, wherein the read-out circuit is to generate an output representative of the memristor conductance; a tracking circuit comprising a first replica cell that emulates at least one of the cross-point devices, wherein the tracking circuit is to produce a reference voltage; and a converter configured to convert the output of the read-out circuit into a digital output or a pulse-width-modulated signal, wherein the reference voltage is provided to the converter as an input.

Technologies for reducing series resistance are disclosed. An example method may include: forming a first layer on a temporary substrate; forming a second layer on the first layer; etching the first layer and the second layer to form a trench; electroplating a top electrode via the trench, wherein the top electrode partially formed on a top surface of the second layer; removing the first layer and the second layer; forming a curable layer on the temporary substrate and the top electrode; removing the temporary substrate from the curable layer and the top electrode; forming a cross-point device on the curable layer and the top electrode; forming a bottom electrode on the cross-point device; and forming a flexible substrate on the bottom electrode.

Technologies relating to RRAM crossbar array circuits with specialized interface layers for the low current operations are disclosed. An example apparatus includes: a substrate; a bottom electrode formed on the substrate; a first layer formed on the bottom electrode; an RRAM oxide layer formed on the first layer and the bottom electrode; and a top electrode formed on the RRAM oxide layer. The first layer may be a continuous layer or a discontinuous layer. The apparatus may further comprise a second layer formed between the RRAM oxide layer and the top electrode. The second layer may be a continuous layer or a discontinuous layer.

The present invention discloses a synaptic array, an operation circuit, and an operation method for neural network learning, belonging to the field of neural network operation technology. The synaptic array comprises an upper and lower double-layer crossbar array structure. The upper crossbar array comprises upper basic units connected between word lines, bit lines, and word lines located on the upper layer. Each upper basic unit comprises a series-connected switch device and a fixed resistor. The lower crossbar array comprises lower basic units connected between word lines, bit lines, and word lines located on the lower layer. Each lower basic unit comprises a series-connected memristor and a transistor. Interconnect lines extend from the connection ends of the switch devices and the fixed resistors and are connected to the gates of the transistors. The conductance of each memristor is used to calculate weights. Based on the synaptic array of the present invention, neural network learning operations can be implemented without occupying a large amount of off-chip computing resources.

A computer implemented method includes performing a gradient update for a stochastic gradient descent (SGD) of a deep neural network (DNN) using a first set of hidden weights stored in a first matrix

The present disclosure provides memristor-based crossbar circuits. A crossbar circuit may include a crossbar array of cross-point devices connecting to intersecting word lines and bit lines. The crossbar circuit further includes a first readout circuit configured to generate an output voltage representing a sum of currents flowing through a bit line connecting to one or more of the cross-point devices. The crossbar circuit further includes a voltage replica circuit connected to the first readout circuit. The voltage replica circuit includes a replica cell configured to produce a reference cell current, an operational amplifier, and a second readout circuit connected to the replica cell and the operational amplifier. The output of the operational amplifier is connected to the first readout circuit to provide a bias voltage to the first readout circuit.

A hybrid analog / digital in-memory computing device implements matrix vector multiplication with reduced noise for use by a deep neural network (DNN). For each row of the crossbar array, the multiplier is split into at least a most significant (MS) portion and a least significant (LS) portion and preloaded into at least two cells of the same row and at least two different columns of the crossbar array. Input activation (IA) values are driven onto the input conductors of each row, and an analog-to-digital converter (ADC) converts output signals from the two columns into a truncated MS partial sum and a truncated LS partial sum. A gain is applied to the truncated MS part sum and added to the truncated LS part sum to form a result value for one node of the DNN.

The present invention relates to a system and method for memristor crossbar array neural network with defective synaptics repair. There is provided a memristor circuit including a primary memristor crossbar array, a redundant memristor crossbar array; and a connection switching circuit for switching inputs from the primary memristor crossbar array to the redundant memristor crossbar array when a defective synaptic is detected in the primary memristor crossbar array.

Input digital bits are split into a first part and a second part. Digital-to-analog converter (DAC) is configured to encode the first part and the second part into analog form as an activation pulse having width equivalent to magnitude of the first part in time units and a delay of a duration that is a fraction of one time unit of the time units, where the fraction is equivalent to magnitude of the second part divided by two raised to power of number of bits in the second part. Crossbar array coupled with the DAC stores weights encoded as analog conductance on resistive memory devices, and is configured to generate analog computation output responsive to the analog form of the input digital bits applied to the crossbar array. Analog-to-digital converter (ADC) coupled with the crossbar array, is configured to digitize the analog computation output from the crossbar array.

Matrix inversion systems and methods are implemented using an analog resistive processing unit (RPU) array for hardware accelerated computing. A request is received from an application to compute an inverse matrix of a given matrix, and a matrix inversion process is performed in response to the received request. The matrix inversion process includes storing a first estimated inverse matrix of the given matrix in an array RPU cells, performing a first iterative process on the first estimated inverse matrix stored in the array of RPU cells to converge the first estimated inverse matrix to a second estimated inverse matrix of the given matrix, and reading the second estimated inverse matrix from the array of RPU cells upon completion of the first iterative process. An inverse matrix is returned to the application, wherein the returned inverse matrix is based, at least in part, on the second estimated inverse matrix.

The invention relates to the technical field of camera shooting, and discloses a hundred-million-pixel high-definition video acquisition module, which performs delay measurement on trigger signals of output channels connected with nodes, executes path reconfiguration operation through a crossbar switch array when obvious delay deviation between the channels is detected, and performs path reconfiguration operation through the crossbar switch array after a topological structure is stable. The phase difference of trigger signals of all output channels is continuously monitored, when it is detected that the phase drift between adjacent channels exceeds a threshold value, a phase compensation signal is generated, time compensation is applied to the corresponding channel, and therefore time compensation is achieved through cooperative work of delay self-balancing and phase fine adjustment. The delay equalization of a trigger path level and the phase synchronization of a clock level can be realized at the same time, so that synchronous exposure and time sequence consistent acquisition of a multi-channel video acquisition unit in a high-resolution state are ensured, and stable frame-level alignment and image fusion quality can still be kept under the conditions of high resolution and ultra-wide field of view; therefore, the definition and the space continuity of panoramic video output are improved.

A full-scale convolution calculator based on a memristor crossbar array is characterized by comprising a convolution kernel matrix, an input array, and an output circuit that outputs the convolution result. A convolution method for a full-scale convolution calculator is described. The convolution kernel matrix acquires input data, which then transmits a pulse voltage signal below the memristor threshold voltage to the positive input of the convolution kernel. After passing through an arithmetic circuit, m data are obtained. Each data is connected to the input array and accumulated and summed within F convolution calculation units with the input data stored in the memristor crossbar array. The result is then output. This method significantly accelerates convolution calculations by increasing storage area, leveraging the high integration and size advantages of the memristor array. The convolver can perform convolution calculations on all convolution areas tiled on the convolution matrix in parallel, significantly increasing computational efficiency. The larger the input data, the more significant the effect.

Provided are method of fabricating a dual damascene crossbar array. The method includes forming a bottom electrode layer on a substrate and forming a first memory device on the bottom electrode layer.

Technologies relating to RRAM crossbar array circuits with specialized interface layers for the low current operations are disclosed. An example apparatus includes: a substrate; a bottom electrode formed on the substrate; a first layer formed on the bottom electrode; an RRAM oxide layer formed on the first layer and the bottom electrode; and a top electrode formed on the RRAM oxide layer. The first layer may be a continuous layer or a discontinuous layer. The apparatus may further comprise a second layer formed between the RRAM oxide layer and the top electrode. The second layer may be a continuous layer or a discontinuous layer.

In a method for operating a hardware implementation of a neural network system, a neural network system is provided that includes a controller, a memory, and an interface connecting the controller to the memory, where the controller includes a processing unit configured to execute a neural network and the memory includes a neuromorphic memory device having a crossbar array structure including input lines and output lines interconnected at cross points via electronics. The electronics of the neuromorphic memory device are programmed to incrementally change states by coupling write signals to the input lines based on write instructions received from the controller and write vectors generated by the interface. Data is retrieved from the neuromorphic memory device by coupling read signals to one or more of the input lines of the neuromorphic memory device based on read instructions from the controller and read vectors generated by the interface in accordance with a multiply-accumulate operation.

This patent declaration discloses a crossbar array having self-formed channels in IMT and self-alignment of channels with filaments in RRAM. An example crossbar array includes: a bottom electrode; a filament formation layer formed on the bottom electrode; a channel formation layer formed on the filament formation layer; and a top electrode formed on the channel formation layer, wherein the filament formation layer is configured to form a filament within the filament formation layer, and the channel formation layer is configured to form a channel within the channel formation layer when a switching voltage is applied on the filament formation layer and the channel formation layer.

The present disclosure provides for a semiconductor device with integrated sensing and processing functionalities. The semiconductor device includes a sensing module configured to generate a plurality of analog sensing signals; and a machine learning (ML) processor. The sensing module and the ML processor are fabricated on a single wafer. The ML processor includes crossbar arrays that processes the analog sensing signals to generate analog preprocessed sensing data; an analog-to-digital converter (ADC) to convert the analog preprocessed sensing data into digital preprocessed sensing data; and a machine learning processing unit to process the digital preprocessed sensing data utilizing one or more machine learning model.