40 results about "Crossbar array" patented technology

In certain examples, a method may include receiving a privacy parameter and selecting an electrical property range for cells in a crossbar array based on the privacy parameter. The cells in the crossbar array may then be programmed based on the selected electrical property range, which may provide a certain level of differential privacy.

Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a first NMOS transistor; a second PMOS transistor; and an RRAM device. The first NMOS transistor and the second PMOS transistor are in parallel as a pair, wherein the pair connects in series with the RRAM device. The apparatus may further include an inverter, via which the second gate terminal of the second PMOS transistor is connected to the first gate terminal.

The invention proposes a crossbar array with a plurality of vertical and horizontal lines, wherein signals are applied to the horizontal lines that determine the magnitudes of time delays of voltage-controlled time delay elements based on RRAM elements, the delays of which are set by the RRAM elements and by the magnitude of the signals on the horizontal lines, wherein a trigger signal (excitation signal) applied to the time delay element chain of a vertical line is transmitted with a time delay to the other end of said vertical line in order to be measured there by means of a time delay measuring element (for example, TDC), thus making the vertical line readable.

A crossbar circuit including a crossbar array and a periphery circuit is provided. A resistive random-access memory (RRAM) device of the crossbar array includes a bottom electrode fabricated on a first interconnect layer; a top electrode; and a filament-forming layer fabricated between the bottom electrode and the top electrode. A portion of the filament-forming layer and a portion of the top electrode are fabricated in a via in a first etch stop layer. The crossbar circuit further includes a second etch stop layer fabricated on the top electrode and a dielectric layer fabricated on the second etch stop layer. The top electrode is connected to a first metal via of a second interconnect layer fabricated in the second etch stop layer and the dielectric layer. The periphery circuit includes a metal via of the second interconnect layer that is fabricated in the dielectric layer and the first etch stop layer.

The application provides a configurable cross switch circuit and a convolution operation circuit based on the same, the configurable cross switch circuit comprising a read cross switch array in front of an operation unit array and a write cross switch array in front of the operation unit array; input feature maps are introduced into an input memory stack, input into the operation unit array through the read cross switch array, and output feature maps calculated by the operation unit array are written into an output memory stack through the write cross switch; in each cycle, at most only one switch is closed for the same column read switch and the same row write switch. The two-dimensional convolution operation circuit based on the application only needs to introduce the input feature map data into the on-chip memory once, and the two-dimensional convolution operation can be completed, without the need of repeatedly introducing the input feature map data into the memory or transmitting the input feature map data between the memories, so that the performance of the two-dimensional convolution calculation is improved and the energy consumption is reduced.

A wireless radio-frequency receiver (500) comprising multiple antenna elements (511-514) for receiving a radio signal, an analogue beamforming radio circuit (520), a digital baseband processor (530), a first signal path (531) and a second signal path (532) from the multiple antenna elements (511-514) to the digital baseband processor (530), wherein the first signal path comprises the analogue beamforming radio circuit (520) and wherein the second signal path (532), which is at least partly parallel to the first signal path (531), comprises an analogue crossbar array (540), wherein a respective antenna element (511-514) is connected to a corresponding input of the analogue crossbar array (540), the analogue crossbar array (540) being configured to provide output signals that is the result of a matrix multiplication of input signals of the analogue crossbar array (540).

Described herein are techniques to enable tracking circuits for crossbar circuits. One embodiment provides an apparatus including a crossbar array comprising: a plurality of bit lines intersecting with a plurality of word lines; and a plurality of cross-point devices, wherein each of the cross-point devices is connected to at least one of the word lines and at least one of the bit lines; a read-out circuit selectively connected to at least one of the bit lines, wherein the read-out circuit is to generate an output representative of the memristor conductance; a tracking circuit comprising a first replica cell that emulates at least one of the cross-point devices, wherein the tracking circuit is to produce a reference voltage; and a converter configured to convert the output of the read-out circuit into a digital output or a pulse-width-modulated signal, wherein the reference voltage is provided to the converter as an input.

Technologies relating to RRAM crossbar array circuits with specialized interface layers for the low current operations are disclosed. An example apparatus includes: a substrate; a bottom electrode formed on the substrate; a first layer formed on the bottom electrode; an RRAM oxide layer formed on the first layer and the bottom electrode; and a top electrode formed on the RRAM oxide layer. The first layer may be a continuous layer or a discontinuous layer. The apparatus may further comprise a second layer formed between the RRAM oxide layer and the top electrode. The second layer may be a continuous layer or a discontinuous layer.

The present invention relates to a system and method for memristor crossbar array neural network with defective synaptics repair. There is provided a memristor circuit including a primary memristor crossbar array, a redundant memristor crossbar array; and a connection switching circuit for switching inputs from the primary memristor crossbar array to the redundant memristor crossbar array when a defective synaptic is detected in the primary memristor crossbar array.

Input digital bits are split into a first part and a second part. Digital-to-analog converter (DAC) is configured to encode the first part and the second part into analog form as an activation pulse having width equivalent to magnitude of the first part in time units and a delay of a duration that is a fraction of one time unit of the time units, where the fraction is equivalent to magnitude of the second part divided by two raised to power of number of bits in the second part. Crossbar array coupled with the DAC stores weights encoded as analog conductance on resistive memory devices, and is configured to generate analog computation output responsive to the analog form of the input digital bits applied to the crossbar array. Analog-to-digital converter (ADC) coupled with the crossbar array, is configured to digitize the analog computation output from the crossbar array.

Matrix inversion systems and methods are implemented using an analog resistive processing unit (RPU) array for hardware accelerated computing. A request is received from an application to compute an inverse matrix of a given matrix, and a matrix inversion process is performed in response to the received request. The matrix inversion process includes storing a first estimated inverse matrix of the given matrix in an array RPU cells, performing a first iterative process on the first estimated inverse matrix stored in the array of RPU cells to converge the first estimated inverse matrix to a second estimated inverse matrix of the given matrix, and reading the second estimated inverse matrix from the array of RPU cells upon completion of the first iterative process. An inverse matrix is returned to the application, wherein the returned inverse matrix is based, at least in part, on the second estimated inverse matrix.

The invention relates to the technical field of camera shooting, and discloses a hundred-million-pixel high-definition video acquisition module, which performs delay measurement on trigger signals of output channels connected with nodes, executes path reconfiguration operation through a crossbar switch array when obvious delay deviation between the channels is detected, and performs path reconfiguration operation through the crossbar switch array after a topological structure is stable. The phase difference of trigger signals of all output channels is continuously monitored, when it is detected that the phase drift between adjacent channels exceeds a threshold value, a phase compensation signal is generated, time compensation is applied to the corresponding channel, and therefore time compensation is achieved through cooperative work of delay self-balancing and phase fine adjustment. The delay equalization of a trigger path level and the phase synchronization of a clock level can be realized at the same time, so that synchronous exposure and time sequence consistent acquisition of a multi-channel video acquisition unit in a high-resolution state are ensured, and stable frame-level alignment and image fusion quality can still be kept under the conditions of high resolution and ultra-wide field of view; therefore, the definition and the space continuity of panoramic video output are improved.

Provided are method of fabricating a dual damascene crossbar array. The method includes forming a bottom electrode layer on a substrate and forming a first memory device on the bottom electrode layer.

In a method for operating a hardware implementation of a neural network system, a neural network system is provided that includes a controller, a memory, and an interface connecting the controller to the memory, where the controller includes a processing unit configured to execute a neural network and the memory includes a neuromorphic memory device having a crossbar array structure including input lines and output lines interconnected at cross points via electronics. The electronics of the neuromorphic memory device are programmed to incrementally change states by coupling write signals to the input lines based on write instructions received from the controller and write vectors generated by the interface. Data is retrieved from the neuromorphic memory device by coupling read signals to one or more of the input lines of the neuromorphic memory device based on read instructions from the controller and read vectors generated by the interface in accordance with a multiply-accumulate operation.

The present disclosure provides for a semiconductor device with integrated sensing and processing functionalities. The semiconductor device includes a sensing module configured to generate a plurality of analog sensing signals; and a machine learning (ML) processor. The sensing module and the ML processor are fabricated on a single wafer. The ML processor includes crossbar arrays that processes the analog sensing signals to generate analog preprocessed sensing data; an analog-to-digital converter (ADC) to convert the analog preprocessed sensing data into digital preprocessed sensing data; and a machine learning processing unit to process the digital preprocessed sensing data utilizing one or more machine learning model.

Predefined concepts are represented by codebooks. Each codebook includes candidate code hypervectors that represent items of a respective concept of the predefined concepts. A neuromorphic memory device with a crossbar array structure includes row lines and column lines stores a value of respective code hypervectors of an codebook. An input hypervector is stored in an input buffer. A plurality of estimate buffers are each associated with a different subset of row lines and a different codebook and initially store estimated hypervectors. An unbound hypervector is computed using the input hypervector and all the estimated hypervectors. An attention vector is computed that indicates a similarity of the unbound hypervector with one estimated hypervector. A linear combination of the one estimated hypervector, weighted by the attention vector, is computed and is stored in the estimate buffer that is associated with the one estimated hypervector.

Technologies for reducing series resistance are disclosed. An example method may include: forming a first layer on a temporary substrate; forming a second layer on the first layer; etching the first layer and the second layer to form a trench; electroplating a top electrode via the trench, wherein the top electrode partially formed on a top surface of the second layer; removing the first layer and the second layer; forming a curable layer on the temporary substrate and the top electrode; removing the temporary substrate from the curable layer and the top electrode; forming a cross-point device on the curable layer and the top electrode; forming a bottom electrode on the cross-point device; and forming a flexible substrate on the bottom electrode.

A neural network device performing floating point operations and an operating method thereof are provided. The neural network device performs a multiply-accumulate (MAC) operation for a product of a fraction of a weight and an input activation in a block floating point format by using an analog crossbar array, performs an addition operation for a shared exponent of the weight and the input activation in the block floating point format by using a digital computing circuit, and outputs a partial sum of a floating point output activation by combining a result of the MAC operation with a result of the addition operation.

The invention relates to moiré synaptic transistors and crossbar array comprising M columns and N rows of moiré synaptic transistors. The moiré synaptic transistor comprises a top gate, a bottom gate, and an asymmetric moiré heterostructure disposed between the top gate and the bottom gate; and a source and a drain spatial-apart formed on the asymmetric moiré heterostructure to define a conductance channel in the asymmetric moiré heterostructure therebetween, and wherein the top gate and the bottom gate are capacitively coupled with the conductance channel.

Techniques are provided for noise and bound management for DNN training on an RPU crossbar array using a worst-case based scaling factor. A method for noise and bound management includes obtaining an input vector value x of an analog crossbar array of an RPU device, where a weight matrix is mapped to the analog crossbar array of the RPU device, and scaling the input vector value x based on a worst case to provide a scaled input vector value x' to use as an input to the analog crossbar array of the RPU device, where the worst case includes a sum of an assumed maximum weight of the weight matrix multiplied by an absolute value from the input vector value x.

The invention discloses an array operation implementation system and method based on a memristor, and belongs to the technical field of integrated circuit chip design and storage and calculation integration. According to the technical scheme, the array operation implementation method based on the memristor comprises an improved memristor circuit structure, an MOS circuit is added on the basis of an original FEIX method, the input end of a Schmitt trigger is connected with a common node of the memristor, the output end of the Schmitt trigger is connected with an output memristor Z, an original output memristor Y serves as a load resistor, and the output memristor Y serves as a load resistor. The width-to-length ratio of the added MOS circuit is adjusted to adjust the center voltage of the overturning point and the voltage of the output end; noise interference is suppressed through the improved memristor circuit structure, complex arithmetic operation is realized by using the reconfigurable bidirectional Crossbar array, data handling overhead is reduced through modular design, and the method has the advantages of improving operation reliability, supporting complex arithmetic operation and optimizing operation efficiency.

The present invention is particularly directed to an information processing device (10) substantially comprising a vector processing unit (VPU) and an in-memory computing unit (IMC unit). The VPU (14) has a vector register designed to store vector components. The IMC unit (15) has a crossbar array structure adapted to store values (referred to as weights). The IMC unit is connected to a vector register (148) of the VPU. The information processing apparatus is configured to perform a number of operations including a vector transfer operation, a vector feed operation, and a vector read-out operation. In operation, a vector transfer operation causes a vector component of an input vector to be stored in a vector register of the VPU. When corresponding instructions are received from a main processing unit (12) to which the VPU is connected, these components are typically fetched from neighboring memories (11). A vector feed operation feeds an input vector component as an input from a vector register to an IMC unit. This in turn causes the IMC unit to perform a matrix-vector multiplication based on the weight and the input vector component to obtain an output vector accordingly. Finally, the vector readout operation writes an output vector component of the output vector to the vector register. Starting from this time, the output vector component may be transferred to a memory or a main processing unit (for further processing), or further processed in the VPU prior to being transferred to the memory or the main processing unit. The invention also relates to related systems and methods.

The invention is notably directed to a method of processing data. The method relies on a memory device having a crossbar array structure. The latter includes K×L cells, which interconnect K rows and Z columns. The cells include respective memory systems, which store respective A-bit weights. The memory systems are connected to respective compute units, which are configured as interleaved switched-capacitor analogue multipliers and adders. According to the proposed method, input signals encoding respective M-bit input words are synchronously applied to respective ones of the K rows. The compute units are operated according to a 3-phase clocking scheme, with a view to obtaining MAC results for each of the L columns, where K≥2, L>2, N≥2, and M≥2. Remarkably, the 3-phase clocking scheme is here set to perform n×m partial multiplications, in the analogue domain, according to a specific bit partition, so as to obtain n×m partial output signals in output of each of the compute units. This partition decomposes each of the N-bit weights into n groups of bits and each of the M-bit input words into m groups of bits. Each of the n groups and the m groups includes at least one bit. However, at least one of the n groups and / or the m groups includes at least two bits, whereby N+M>n+m≥3. Moreover, the MAC results are obtained by summing the partial output signals obtained by the compute units for each of the Z columns. The summed output signals are converted into digital signals encoding partial values. The partial values are shifted according to corresponding bit positions, which are set in accordance with the bit partition, and the shifted values are finally added, so as to recompose the desired output vector components. The invention is further directed to related apparatuses and systems.

A system and method for autonomous machine identity succession utilize a hardware-rooted semantic sentinel and an analog neuromorphic audit engine to ensure state integrity. The system detects micro-architectural threat signatures through continuous asynchronous voltage monitoring and gates cryptographic signatures via a low-impedance analog interlock circuit physically interposed on a processor signature-enable line. Behavioral integrity is verified through an adversarial “Proof of Logical Alignment” handshake, where proposed action vectors are audited via an analog memristor crossbar array utilizing physical current summation replicated through a high-impedance Wilson Current Mirror isolation barrier. The invention ensures the atomic migration of identities across heterogeneous hardware architectures through a “Handshake-and-Zeroize” protocol, utilizing a series-pass isolation switch and crowbar MOSFET circuit to provide irreversible thermodynamic destruction of the source state.

A crossbar circuit is provided. The crossbar circuit includes one or more bit lines, one or more word lines, one or more cell devices connected between the bit lines and the word lines, one or more analog-to-digital converters (ADCs) connected to the one or more bit lines, one or more digital-to-analog converters (DACs) connected to the one or more word lines, one or more access controls connected to the one or more cell devices and configured to select a cell device in the one or more cell devices and to program the selected cell device, and a slew rate controller connected to the one or more bit lines. The first slew rate controller is configured to receive an input signal or a bias and output a slew-rate controlled signal.

An electronic device and an operating method thereof are provided. The electronic device can include a crossbar array including a plurality of first memory cells, a plurality of second memory cells, a plurality of row lines, a plurality of first column lines, and a second column line, and a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines, each of the plurality of analog-to-digital converters receiving a reference voltage. Each of the plurality of analog-to-digital converters determines an allowed maximum value of an analog signal voltage based on the reference voltage.

Systems and methods are disclosed for deep learning solutions with analog AI. Analog AI systems can outperform their digital counterparts in speed and energy efficiency since computations are conducted directly in memory and analog processors inherently support parallel operations. An analog AI system may comprise a DAC, a programming module, row / column switches, a crossbar array and an ADC. The DAC provides an analog signal to the row / column switches, which along with the programming module, select a phase of operation, i.e., a forward, backward, or update path. A crossbar array is a trainable neural network that operates in the analog domain and comprises a matrix of programmable resistors, e.g., memristor devices. The crossbar array couples an output in the analog domain to the ADC. The result is a digital output from the crossbar array processing architecture.

Systems and methods are disclosed for analog-to-digital-converter (ADC) solutions supporting analog AI deep learning systems. These systems can outperform their digital counterparts in speed and energy efficiency since computations are conducted directly in memory and analog processors inherently support parallel operations. ADCs play a crucial role in analog AI deep learning because they serve as the bridge between the analog and digital worlds. An analog AI deep learning system may comprise a DAC, a programming module, row / column switches, a crossbar array and an ADC. The ADC may comprise switches for time interleaving of an analog neural network output signal, received from the row / column switches associated with the crossbar array. The time interleaved signals are separately ported between two capacitive paths, and are subsequently coupled to separate inverters. A frequency signal is generated by a logic gate, which is coupled to a digital filter that generates an n-bit digital word.