124 results about "Crossbar array" patented technology

An electronic decoder for decoding of block coded wireless communications signals. The electronic decoder comprises at least two electrically interconnected analogue crossbar arrays (1110, 1120) of memristors. An electrical interconnection (1115) between a column (1111) of an analogue crossbar array of the at least two electrically 5 interconnected analogue crossbar arrays (1110, 1120) and a row (1121) of a following analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays (1110, 1120) comprises a current-to-voltage converter (1101). A first analogue crossbar array (1110) of the at least two analogue crossbar arrays (1110, 1120) comprises at least a first row of memristors (1112a) with a single input and a 10 respective output for each column of memristors.

A matrix-vector multiplication device includes an input encoder that encodes an input vector into a binary complement format value and a binary true format value; a pulse generator that converts each encoded bit of the binary complement format value and each encoded bit of the binary true format value into a corresponding pulse signal; a crossbar array of weights, wherein each weight is encoded as a differential analog conductance of resistive memory devices, wherein the pulse generator simultaneously applies a pulse signal corresponding to a given encoded bit of the binary complement format value and a pulse signal corresponding to a given encoded bit of the binary true format value to corresponding resistive memory devices; an analog-to-digital converter that digitizes outputs of the crossbar array of weights to generate partial dot-product results; and a digital counter that computes a final dot-product result from the partial dot-product results.

The invention is particularly directed to a hardware system (1) designed for implementing an artificial neural network (ANN). The hardware system substantially includes a neural processing device (15) (e.g., involving a crossbar array structure), one or more lookup table circuits (17), and one or more processing units (18). The neural processing device is configured to implement M artificial neurons, where M > = 1. The lookup table circuit is configured to implement a lookup table (LUT). The system also includes M'processing units, where M > = M '> = 1. Each processing unit is connected by at least one neuron so as to be able to access a first value output by each connected neuron. In addition, each processing unit is connected to the LUT circuitry so as to efficiently access parameter values of the parameter set from the LUT. Finally, each processing unit is configured to output a second value corresponding to a value of a mathematical function with the first value as an argument. The mathematical function is additionally determined by a set of parameters whose parameter values are accessed in operation from the LUT by each processing unit. That is, the mathematical function is defined (and thus determined) by a set of parameters, the values of which can be efficiently retrieved from a hardware-implemented LUT. This results in a significant acceleration of the calculation of the function output beyond the acceleration that may have been achieved within the neural processing devices and processing units themselves. Thus, neuron outputs can be processed more efficiently before passing to the next neuron layer. The invention is also directed to a method of operating such a hardware system.

The invention relates to a matrix decomposition device and method based on a memristor cross array, which are suitable for efficient hardware implementation of singular value decomposition (SVD), the memristor cross array receives a conductance value mapped by a Grubrum matrix constructed by a to-be-decomposed matrix and a bit line input voltage converted by a bit line column vector, and outputs a corresponding current; converting the corresponding current into a voltage vector; performing normalization processing on the voltage vector to obtain a normalized vector; judging whether convergence occurs or not; performing normalization processing on the steady-state voltage vector to obtain a final output vector; and according to the final output vector, main characteristic values are extracted based on a first normalization circuit, and main singular values and corresponding singular matrixes are calculated. Compared with the prior art, the high parallel computing characteristic of the memristor cross array is utilized, efficient operation and hardware acceleration of matrix decomposition are achieved, the method has the advantages of being low in power consumption, high in speed and good in expansibility, and the method is suitable for application scenes such as artificial intelligence, signal processing and large-scale matrix operation.

The invention is directed to solving an optimization problem. The method operates a photonic crossbar array structure including N input lines and M output lines, which are interconnected at junctions via N×M photonic memory devices, where N≥2 and M≥2. The photonic memory devices are programmed to store respective weights in accordance with the optimization problem. The photonic crossbar array structure is operated as follows. First, the method determines values of L input vectors of N components each, where L≥2. Second, based on the determined values, N electromagnetic signals are generated, where each of the generated signals multiplexes L input signals encoded at respective wavelengths, so as for the N electromagnetic signals to map the L input vectors of N components each. Third, the N electromagnetic signals generated are applied to the N input lines of the photonic crossbar array structure.

The invention is notably directed to a hardware system (1) designed to implement an artificial neural network (ANN). The hardware system basically includes a neural processing apparatus (15), e.g., involving as crossbar array structure, one or more lookup table circuits (17), and one or more processing units (18). The neural processing apparatus is configured to implement M artificial neurons, where M≥1. The lookup table circuits are configured to implement a lookup table (LUT). The system further includes M′ processing units, where M≥M′≥1. Each processing unit is connected by at least one neuron, in order to be able to access a first value outputted by each connected neuron. In addition, each processing unit is connected to a LUT circuit, in order to efficiently access parameter values of a set of parameters from the LUT. Finally, each processing unit is configured to output a second value, corresponding to a value of a mathematical function taking said first value as argument. The mathematical function is otherwise determined by the set of parameters, the parameter values of which are accessed by each processing unit from the LUT, in operation. I.e., the mathematical function is defined (and thus determined) by a set of parameters, the values of which are efficiently retrieved from the hardware-implemented LUT. This results in a substantial acceleration of the computations of the function outputs, beyond the acceleration that may already be achieved within the neural processing apparatus and the processing units themselves. As a result, the neuron outputs can be more efficiently processed, prior to being passed to a next neuron layer. The invention is further directed to a method of operating such a hardware system.

According to various aspects, a memristive crossbar array is provided including: first control lines and second control lines in a crossbar configuration defining a plurality of cross-point regions, a memristive material portion disposed in each of the plurality of cross-point regions between a corresponding pair of one of the first control lines and one of the second control lines to form a corresponding memristive structure. Each memristive material portion may have a thickness in a predefined range such that each corresponding memristive structure has a symmetric read characteristic and / or at least one curvature change in the read characteristic.

In certain examples, a method may include receiving a privacy parameter and selecting an electrical property range for cells in a crossbar array based on the privacy parameter. The cells in the crossbar array may then be programmed based on the selected electrical property range, which may provide a certain level of differential privacy.

A neural network apparatus performs multiply-accumulate (MAC) operations with respect to fractions of weights and input activations in a block floating-point format by using an analog crossbar array, performs addition operations with respect to shared exponents of weights and input activations in a block floating-point format by using a digital computing circuit, and outputs a partial sum of floating-point output activations by combining the result of the MAC operations and the result of the addition operations.

A crossbar circuit including a crossbar array and a periphery circuit is provided. A resistive random-access memory (RRAM) device of the crossbar array includes a bottom electrode fabricated on a first interconnect layer; a top electrode; and a filament-forming layer fabricated between the bottom electrode and the top electrode. A portion of the filament-forming layer and a portion of the top electrode are fabricated in a via in a first etch stop layer. The crossbar circuit further includes a second etch stop layer fabricated on the top electrode and a dielectric layer fabricated on the second etch stop layer. The top electrode is connected to a first metal via of a second interconnect layer fabricated in the second etch stop layer and the dielectric layer. The periphery circuit includes a metal via of the second interconnect layer that is fabricated in the dielectric layer and the first etch stop layer.

A method is presented for artificial neural network training. The method includes storing weight values in an array of resistive processing unit (RPU) devices, wherein the array of RPU devices represents a weight matrix, defining the weight matrix to have an output dimension that is smaller than the input dimension such that the weight matrix has a rectangular configuration, and converting the weight matrix from a rectangular configuration to a more square-shaped configuration by repeating or concatenating the rectangular configuration of the weight matrix to increase a signal strength of a backward pass signal by copying an input of repeated weight elements during a forward cycle pass, summing output computations from the repeated weight elements, updating each of the repeated weight elements according to a backpropagated error or alternatively updating only one of the repeated weight elements by setting all forward values except one to zero during an update pass.

The invention relates to an online learning system based on a memristor cross array, and belongs to the technical field of machine learning. The system comprises a forward calculation subsystem, a memristor resistance value online adjustment subsystem and a visualization subsystem, the forward calculation subsystem comprises a memristor cross array simulation device and a computer module, and derivative calculation in neural network training and memristor resistance value dynamic adjustment are combined through a simulation platform. A memory resistor is used for achieving storage and calculation integration, a computer module completes derivative calculation in a differential mode, a differential derivative calculation mechanism of the computer module directly obtains a derivative through actual response of a physical device, the defect that a storage and calculation integration framework cannot store intermediate variables is overcome, and calculation autonomy and efficiency are remarkably improved. Meanwhile, an introduced resistance updating mechanism combining coarse adjustment and fine adjustment can realize efficient and accurate control of the resistance of the memristor. Finally, the neural network learning efficiency and performance based on the memristor cross array are improved.

An electronic filter (200a) for band stop or band pass filtering of an electrical input signal. The electronic filter (200a) comprises a memristive low-pass filter (210) comprising a first crossbar array of memristors (211, 212). Each memristor (211, 212) of the first crossbar array is configured to represent a respective filter coefficient of a low-pass filter implemented as a filter matrix. The electronic filter (200a) further comprises a memristive high-pass filter (220) comprising a second crossbar array of memristors (221, 222). Each memristor of the second crossbar array is configured to represent a respective filter coefficient of a high-pass filter function implemented as a filter matrix.

Provided is an analog-to-digital converter and a neuromorphic computing device including the analog-to-digital converter. The analog-to-digital converter is connected to a crossbar switch array including a plurality of resistive memory cells. Each of the plurality of resistive memory cells includes a resistive element. The analog-to-digital converter includes a voltage generator and a processing circuit. The voltage generator includes at least one resistive memory element having the same resistive material as the resistive elements included in the crossbar switch array. The voltage generator is configured to generate a first voltage based on a reference voltage and the at least one resistive memory element, and divide the first voltage to generate at least one divided voltage. The processing circuit is configured to: compare a signal voltage generated from the crossbar switch array with the at least one divided voltage to generate at least one comparison signal; and generate at least one digital signal corresponding to the signal voltage based on the at least one comparison signal.

The invention belongs to the related technical field of memory architecture design, and discloses a storage pool computing system based on reconfigurable memristors and a storage pool computing control method.The system comprises memristor-transistor units arranged in a crossed array, each memristor-transistor unit comprises a reconfigurable memristor and a transistor, and the reconfigurable memristor and the transistor are arranged in a staggered array mode. The transistor is connected with the reconfigurable memristor, the reconfigurable memristor can realize reversible conversion between volatility and non-volatility under the control of an input voltage of the transistor, the reconfigurable memristor is controlled to present volatility to realize a feature extraction process of a time sequence signal, and the reconfigurable memristor is controlled to present non-volatility to realize an identification and classification process. According to the invention, the reconfigurable memristor is utilized, and the working modes are dynamically switched through regulation and control of the transistor, so that the synergistic effect of short-term memory and long-term weight storage can be realized, and real-time and efficient reserve pool calculation can be realized; the complexity in the traditional hardware design is reduced, and the system architecture is simplified.

Crossbar arrays with reduced disturbance and methods for programming the same are disclosed. In some implementations, an apparatus comprises: a plurality of rows; a plurality of first columns; a plurality of second columns; a plurality of devices. Each of the plurality of devices is connected among one of the plurality of rows, one of the plurality of first columns, and one of the plurality of second columns. The device further comprises a shared end on the plurality of first columns or the plurality of the second columns connecting to the plurality of the devices in the same row or column; the shared end is grounding or holds a stable voltage potential. In some implementations, one of the devices is: a RRAM, a floating date, a phase change device, an SRAM, a memristor, or a device with tunable resistance. In some implementations the stable voltage potential is a constant DC voltage.

Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a first NMOS transistor; a second PMOS transistor; and an RRAM device. The first NMOS transistor and the second PMOS transistor are in parallel as a pair, wherein the pair connects in series with the RRAM device. The apparatus may further include an inverter, via which the second gate terminal of the second PMOS transistor is connected to the first gate terminal.

The invention proposes a crossbar array with a plurality of vertical and horizontal lines, wherein signals are applied to the horizontal lines that determine the magnitudes of time delays of voltage-controlled time delay elements based on RRAM elements, the delays of which are set by the RRAM elements and by the magnitude of the signals on the horizontal lines, wherein a trigger signal (excitation signal) applied to the time delay element chain of a vertical line is transmitted with a time delay to the other end of said vertical line in order to be measured there by means of a time delay measuring element (for example, TDC), thus making the vertical line readable.

The invention discloses a time-space fusion detector double-reservoir network system based on multi-frame-in-one calculation, and relates to the technical field of bionic intelligent vision and brain-like calculation. The system comprises a photoelectric reservoir layer and an electrical readout layer, and the photoelectric reservoir layer comprises a retina-shaped MoS2 photoelectric detector array and is used for constructing the photoelectric reservoir layer by using the nonlinear continuous photoconduction characteristic of a two-dimensional MoS2 photoelectric detector. Detecting an optical signal and projecting the optical signal into an electrical readout layer with increased dimensions in a photocurrent form of a multi-frame-in-one pattern; the electrical readout layer includes a memristor cross array for processing an input signal in a parallel manner and generating an output result in real time. The system has the advantages of low power consumption, low delay, high recognition precision and the like, and is particularly suitable for complex application scenes such as infrared dynamic moving target recognition.

A crossbar circuit including a crossbar array and a periphery circuit is provided. A resistive random-access memory (RRAM) device of the crossbar array includes a bottom electrode fabricated on a first interconnect layer; a top electrode; and a filament-forming layer fabricated between the bottom electrode and the top electrode. A portion of the filament-forming layer and a portion of the top electrode are fabricated in a via in a first etch stop layer. The crossbar circuit further includes a second etch stop layer fabricated on the top electrode and a dielectric layer fabricated on the second etch stop layer. The top electrode is connected to a first metal via of a second interconnect layer fabricated in the second etch stop layer and the dielectric layer. The periphery circuit includes a metal via of the second interconnect layer that is fabricated in the dielectric layer and the first etch stop layer.

A field programmable computing architecture includes a programmable crossbar array structure including a set of memory components and a control plane coupled to a plurality of inputs and a plurality of outputs of the programmable crossbar array structure, the control plane to configure the programmable crossbar array to perform one or more in-memory arithmetic operations.

The application provides a configurable cross switch circuit and a convolution operation circuit based on the same, the configurable cross switch circuit comprising a read cross switch array in front of an operation unit array and a write cross switch array in front of the operation unit array; input feature maps are introduced into an input memory stack, input into the operation unit array through the read cross switch array, and output feature maps calculated by the operation unit array are written into an output memory stack through the write cross switch; in each cycle, at most only one switch is closed for the same column read switch and the same row write switch. The two-dimensional convolution operation circuit based on the application only needs to introduce the input feature map data into the on-chip memory once, and the two-dimensional convolution operation can be completed, without the need of repeatedly introducing the input feature map data into the memory or transmitting the input feature map data between the memories, so that the performance of the two-dimensional convolution calculation is improved and the energy consumption is reduced.

The present invention relates to hydroxyaminophosphinic acid derivatives of formula I, in which the groups and parameters occurring have the meanings defined in claim 1, to processes for the preparation of said compounds, and to the use thereof in the production of self-assembled monolayers (SAM), in particular in the production of switchable SAMs for electronic devices. The invention also relates to an electronic device comprising said SAM, preferably in the field of organic electronics, in particular for memories, sensors, in addition for organic light emitting diodes (OLEDs), photovoltaics (OPVs), field effect transistors (OFETs) and Josephson junctions, very particularly for memristive components such as memristive crossbar arrays. # imgabs0 #

A wireless radio-frequency receiver (500) comprising multiple antenna elements (511-514) for receiving a radio signal, an analogue beamforming radio circuit (520), a digital baseband processor (530), a first signal path (531) and a second signal path (532) from the multiple antenna elements (511-514) to the digital baseband processor (530), wherein the first signal path comprises the analogue beamforming radio circuit (520) and wherein the second signal path (532), which is at least partly parallel to the first signal path (531), comprises an analogue crossbar array (540), wherein a respective antenna element (511-514) is connected to a corresponding input of the analogue crossbar array (540), the analogue crossbar array (540) being configured to provide output signals that is the result of a matrix multiplication of input signals of the analogue crossbar array (540).

Technologies relating to crossbar array circuits with parallel ground lines are disclosed. An example crossbar array circuit may include a plurality of transistors. The crossbar array circuit may include an RRAM device connected in series with a first transistor and a second transistor; a first bit line connected to the RRAM device; and a grounding line connected to a body terminal of the first transistor. The grounding line is parallel to the first bit line. In some embodiments, the first transistor is an NMOS transistor. The second transistor is a PMOS transistor.

In some embodiments, an apparatus for performing convolution operations is provided. The apparatus may include multiple crossbar arrays and select circuits. The select circuits are configured to select a first plurality of cross-point devices and a second plurality of cross-point devices in response to receiving a control signal indicating that a regular convolution is to be performed, and to select the first plurality of cross-point devices and a third plurality of cross-point devices in response to receiving a control signal indicating that a depthwise convolution is to be performed. The first plurality of cross-point devices is connected to a first plurality of word lines and a first bit line. The second plurality of cross-point devices is connected to the first plurality of word lines and a second bit line. The third plurality of cross-point devices is connected to a second plurality of word lines and the second bit line.

Described herein are techniques to enable tracking circuits for crossbar circuits. One embodiment provides an apparatus including a crossbar array comprising: a plurality of bit lines intersecting with a plurality of word lines; and a plurality of cross-point devices, wherein each of the cross-point devices is connected to at least one of the word lines and at least one of the bit lines; a read-out circuit selectively connected to at least one of the bit lines, wherein the read-out circuit is to generate an output representative of the memristor conductance; a tracking circuit comprising a first replica cell that emulates at least one of the cross-point devices, wherein the tracking circuit is to produce a reference voltage; and a converter configured to convert the output of the read-out circuit into a digital output or a pulse-width-modulated signal, wherein the reference voltage is provided to the converter as an input.

Technologies for reducing series resistance are disclosed. An example method may include: forming a first layer on a temporary substrate; forming a second layer on the first layer; etching the first layer and the second layer to form a trench; electroplating a top electrode via the trench, wherein the top electrode partially formed on a top surface of the second layer; removing the first layer and the second layer; forming a curable layer on the temporary substrate and the top electrode; removing the temporary substrate from the curable layer and the top electrode; forming a cross-point device on the curable layer and the top electrode; forming a bottom electrode on the cross-point device; and forming a flexible substrate on the bottom electrode.

A computer-implemented method comprises performing a gradient update for stochastic gradient descent (SGD) of a deep neural network (TNN) using a first set of hidden weights stored in a first matrix comprising a resistive processing unit (RPU) crossbar array. A second matrix comprising a second set of hidden weights is stored in a digital medium. A third matrix comprising a set of reference values is calculated after a transfer cycle of the first set of weights from the first matrix to the second matrix, taking into account a sign change (chopper). The third matrix is stored in the digital medium.A third set of weights is updated for the TNN from the second matrix when a threshold for the second set of weights is reached in a fourth matrix comprising an RPU crossbar array.

Technologies relating to RRAM crossbar array circuits with specialized interface layers for the low current operations are disclosed. An example apparatus includes: a substrate; a bottom electrode formed on the substrate; a first layer formed on the bottom electrode; an RRAM oxide layer formed on the first layer and the bottom electrode; and a top electrode formed on the RRAM oxide layer. The first layer may be a continuous layer or a discontinuous layer. The apparatus may further comprise a second layer formed between the RRAM oxide layer and the top electrode. The second layer may be a continuous layer or a discontinuous layer.