146results about "Analogue processes for specific applications" patented technology

A memory cell capable of reversing magnetization on the basis of voltage drive is achieved without providing a selector element in the memory cell. A storage device includes: a memory cell provided with a magnetoresistive effect element; a word line connected to one end of the magnetoresistive effect element; and a bit line connected to another end of the magnetoresistive effect element. The magnetoresistive effect element may have a voltage controlled magnetic anisotropy (VCMA) effect. A driver configured to apply a reversing voltage for reversing a magnetization direction of the magnetoresistive effect element on the basis of the VCMA effect may be included. The driver may switch a voltage applied to the memory cell such that a reversing voltage is applied to a selected cell while a non-reversing voltage is applied to a non-selected cell, in which the non-reversing voltage does not reverse a magnetization direction of the magnetoresistive effect element.

A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes a first arithmetic portion that performs a digital arithmetic operation and a second arithmetic portion that performs an analog arithmetic operation. In an arithmetic operation of a convolutional neural network, the first arithmetic portion executes an arithmetic operation of a convolution layer, and the second arithmetic portion executes an arithmetic operation of a fully connected layer. The convolution layer often uses the same filter value repeatedly; thus, the first arithmetic portion is configured to execute a plurality of product-sum operations at the same time with single input of the same filter value and with input of a plurality of pieces of data to be subjected to convolution processing. Since the fully connected layer needs weight coefficients as many as the product of the number of pieces of input data and the number of pieces of output data, the second arithmetic portion has a structure in which arithmetic cells arranged in a matrix retain the weight coefficients and the input data is transmitted in the row directions, whereby the output data is output in the column directions.

This solution addresses the challenges of reduced learning accuracy and reproducibility in the integration of short-term plasticity (STP) and long-term plasticity (LTP) at the single-element level, due to adjacent element interference and difficulties in non-destructive readout. [Solution] This system utilizes a neuromorphic circuit array based on single elements capable of expressing STP and LTP, and reduces adjacent element interference through interference suppression circuits and common electrode control. The internal state of a single element can be read non-destructively, enabling STP→LTP transitions and spike timing-dependent plasticity (STDP) control according to input pulse conditions. This enables stable and highly reproducible learning operations even in large-scale arrays, improving neuromorphic computation performance.

To provide a semiconductor device that restores degraded data.SOLUTION: A semiconductor device includes a first circuit, a storage unit, and a calculation unit, in which the first circuit has a current source and a first switch, the storage unit has a first transistor and a first capacitor, and the calculation unit has a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch, a first terminal of the first switch is electrically connected to an output terminal of the current source, and a second terminal of the first switch is electrically connected to a first terminal of the second transistor. Upon restoring data held in the storage unit, the first transistor is turned into an ON state to provide the data held in the storage unit to the control terminal of the first switch via the first transistor. The first switch turns into either of an ON state and an OFF state depending on the data and applies the current to the calculation unit from the current source via the second transistor to replenish electric charges to a holding unit of the calculation unit.SELECTED DRAWING: Figure 1

To detect anomalies in an excellent-accuracy and high-speed manner with a simplified configuration.SOLUTION: An anomaly detection device comprises an input unit, a reservoir unit, an output unit, and a determination unit. The input unit outputs a plurality of intermediary signals in accordance with a time-series input signal detected by observing an observation target device. The reservoir unit acquires the plurality of intermediary signals, and outputs a plurality of output signals each having a waveform having reproducibility in respect to a waveform of the input signal. The output unit generates a plurality of multiplication signals by multiplying output weights preset with respect to each of the plurality of output signals, and generates an integral signal obtained by time integration through adding up the plurality of multiplication signals. The determination unit determines whether the observation target device is normal or abnormal based on a result of comparison between the integral signal and a preset threshold, and outputs a determination signal representing a determination result. The output weights represent a positive prescribed value or a negative prescribed value, and are respectively set for the plurality of output signals.SELECTED DRAWING: Figure 2

A spiking neuron circuit system 100 includes: a charging circuit 10 that, when an input voltage is applied, starts charging of a capacitor 12 by an output current I of a field effect transistor 11; a pulse generation circuit 20 that generates and outputs a pulse signal when a charging voltage of the capacitor 12 reaches a first threshold value; and a control circuit 50 that controls the output current I of the field effect transistor 11 by controlling a bulk voltage and / or a gate voltage of the field effect transistor 11.

To provide an information storage system which simulates a neural network on a silicon chip without using a bit.SOLUTION: A neural network has: a plurality of islands periodically disposed in a first axis direction and a second axis direction on a surface of a semiconductor device; a first link and a second link disposed between two islands adjacent to each other in the first direction and the second direction among the plurality of islands; and a first word line in a third axis direction; and a second word line in a fourth axis direction. Each of the plurality of islands has a diffusion layer formed on the surface of the semiconductor device. The first link is a first selection gate for bridging the two islands adjacent to each other in the first direction among the plurality of islands. The second link is a second selection gate for bridging the two islands adjacent to each other in the second direction among the plurality of islands. The first selection gate and the second selection gate have respective selection gate contacts. The selection gate contact is selected by the first word line and the second word line.SELECTED DRAWING: Figure 7

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

The invention provides a non-common-ground attack angle signal acquisition and calculation circuit and method. The non-common-ground attack angle signal acquisition and calculation circuit comprises a step-down follower circuit, an isolation operational amplifier circuit, an isolation power supply circuit and an A / D acquisition and MCU calculation circuit, an isolation operational amplifier circuit is used for isolating and collecting a tap voltage signal and an excitation positive voltage signal which are output by the attack angle alarm system passing through the step-down follower circuit, and outputting the tap voltage signal and the excitation positive voltage signal to an A / D collection and MCU resolving circuit, so that collection of non-common ground attack angle signals is realized; the isolation power supply circuit provides reference voltage for the input ends of the voltage reduction follower circuit and the isolation operational amplifier circuit; the reference voltage of the output end of the isolation operational amplifier circuit is connected to the A / D acquisition and MCU resolving circuit; the A / D acquisition and MCU resolving circuit is used for resolving a local attack angle and a true attack angle; non-common-ground attack angle signals can be effectively collected under the condition that an original system is not affected.

A semiconductor device capable of performing product-sum operations with reduced power consumption is provided. [Solution] A semiconductor device has first and second cells, a first circuit, and first to third wirings. Each of the first and second cells has a capacitance, and a first terminal of each capacitance is electrically connected to a third wiring. Each of the first and second cells has a function of flowing a current corresponding to a potential held at a second terminal of the capacitance to the first and second wirings. The first circuit is electrically connected to the first and second wirings, and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wire changes, the amount of current in the first wire changes from I1 to I3, and the amount of current in the second wire changes from I2 to I4, the first circuit generates a current of I1-I2-I3+I4. Note that the change in the third wire is achieved by first inputting a reference potential to the third wire, and then inputting a potential corresponding to internal data or information obtained by a sensor.

This system provides a mechanism for calibrating electrical parameters in deep learning artificial neural networks. [Solution] The system comprises a digital-to-analog converter for receiving k bits of input and generating a first analog output, a mapping scalar for converting the first analog output to a second analog output, and an analog-to-digital converter for generating an n-bit output from the second analog output, where n is a different value from k.

The present invention improves learning accuracy in a semiconductor device that performs machine learning.　This semiconductor device includes a prescribed number of memory cells, a driver, and a control circuit. In the semiconductor device, the driver supplies a write pulse to each of the memory cells. Further, the control circuit sequentially performs course tuning for controlling, to a prescribed value, a statistical amount of a change amount of the reciprocal of the impedance of the memory cell for each write pulse, and fine tuning for controlling the statistical amount to a value smaller than the prescribed value.

To generate a model for detecting biological signals and to detect abnormal biological signals using the model with a monitor of the biological signal.SOLUTION: A device 1 for detecting abnormal biological signals can communicate with a sensor 2 and one or more external control devices 31, 32, 33, 34. The device 1 receives input data collected by the sensor 2. The sensor 2 emits radio waves toward a human body being the monitoring object, receives radio waves reflected from the surface of the object, and thereby collects characteristics relating to the shape or movement of the object. Thus, the sensor 2 collects changes in the thorax caused by respiration or heartbeat of the human body being the monitoring object. The obtained data is input to a neural network learned on the basis of predetermined learning data in a neuromorphic device that implements the neural network for detecting abnormal biological signals, thereby detecting abnormal biological signals.SELECTED DRAWING: Figure 5

Electronic circuit for implementing a Bayesian neural network The invention relates to an electronic circuit (10) for implementing a Bayesian neural network, comprising bit, source and word lines;and - at least one primary branch (15), each comprising a primary cell (30) connected between source and bit lines and including a primary memory component (32) and a primary switch (34) connected in series, - at least one secondary branch (20), each comprising a secondary cell (50) connected between source and bit lines and including a secondary memory component (52) and a secondary switch (54) connected together, - an accumulation device (25) configured to accumulate a total quantity being the sum of a primary quantity of charges from a primary cell and a secondary quantity of charges from a secondary cell, the primary and secondary quantities being accumulated independently of each other. Figure for the abstract: Figure 1;

To provide a semiconductor device that can perform multiply-accumulate operations with low power consumption. [Solution] An arithmetic circuit having circuits MC and MCr, wherein circuit MC has a holding node nd1, and circuit MCr has a holding node nd1r. Circuits MC and MCr are electrically connected to input wirings X1L and X2L and wirings OL and OLB, respectively, and each of circuits MC and MCr holds first and second potentials corresponding to first data in its respective holding node. When a potential corresponding to second data is input to input wirings X1L and X2L, circuit MC outputs a current to one of wirings OL or OLB, and circuit MCr outputs a current to the other of wirings OL or OLB. The current that circuits MC and MCr output to wirings OL or OLB is determined according to the first and second potentials held in the holding nodes nd1 and nd1r.

A system and method for accelerating a multiply-accumulate (MAC) floating-point unit during training of a deep learning network is disclosed. The method includes receiving a first input data stream A and a second input data stream B, adding pairs of exponents of the first data stream A and the second data stream B to generate a product exponent, identifying a maximum exponent using a comparator, identifying a number of bits to shift for each mantissa of the second data stream before accumulation by adding a product exponent delta to the corresponding term of the first data stream, reducing the operands of the second data stream to a single partial sum using an adder tree, adding the partial sum to a corresponding alignment value using the maximum exponent to identify an accumulation value, and outputting the accumulation value.

The present invention relates to a method, at a ground combat vehicle (V), for passive target distance measurement, the method being performed by means of: a master image sensor device (10) for observing a target (T); and a slave image sensor device (20), said master image sensor device (10) and said slave image sensor device (20) being arranged spaced apart by an offset distance (OD) from each other, said method comprising: controlling an orientation of said at least one slave image sensor device (20); determining whether a line-of-sight (L2) of said slave image sensor device (20) intersects a line-of-sight (L1 ) of said master image sensor device (10) at a location of a target (T); and, if so, receiving: first angular data representing orientation of the master image sensor device (10); and second angular data representing orientation of the slave image sensor device (20). The method further comprises determining a target distance (TD), representing a distance between the combat vehicle and the target, based on the offset distance (OD) and the received angular data. The invention also relates to a system and a ground combat vehicle.

An apparatus for performing vector x vector multiplication in the optical domain, the apparatus including: a plurality of optical signal generators, each optical signal generator arranged to emit a beam of light having a different respective carrier wavelength modulated by an input signal that models a respective variable of a vector of variables; one or more sets of optical modulator elements, each optical modulator element in each set arranged to receive the beam of light modulated by a different one of the input signals and to apply a corresponding weighting from the vector of weights to generate a weighted optical signal; each set of optical sensor elements of the sets; and one or more optical combiner elements arranged to direct each set of weighted optical signals onto a respective optical sensor element, thereby generating a respective output in the form of an analog electronic signal that sums the weighted optical signals of each set.

To realize a reservoir computing device at low cost.SOLUTION: The reservoir computing device includes: an optical medium which propagates in different times according to frequencies; generation means for generating plural continuous lights with different frequencies; modulation means for generating plural modulation lights by modulating the continuous lights with data and outputting signal light including the modulation lights to the optical medium; and photoelectric conversion means for photoelectrically converting the signal light received by the optical medium.SELECTED DRAWING: Figure 4

A system is provided.SOLUTION: The neural network system includes a neural network circuit 510 including first memory cells arranged in an array, and a self-reference circuit 500 electrically connected to a row line or a column line of the neural network circuit and configured to apply a current to a row line or a column line to which a plurality of target memory cells are connected to have a preset target weight, wherein the target memory cells are all memory cells located in the row line or the column line to which the self-reference circuit is connected.SELECTED DRAWING: Figure 5

Systems and methods for executing automated model generation and scenario-based evaluation operations at a resource site are presented. The systems may be used to generate a first framework and a second framework associated with a plurality of domains comprising a plurality of specialization areas associated with developing the resource site. In one embodiment, the systems facilitate generating one or more models and executing one or more simulations on said models based on one or more development scenarios. In one embodiment, the systems and methods enable generation of output data (e.g., well design data, subsea design data, subsurface production data) in response to executing the simulations. The output data according to some embodiments, used to generate one or more visualizations that are displayed on a graphical user interface.

To provide a split-array architecture for an analog neural memory in a deep learning artificial neural network to split the array of non-volatile memory cells in the analog neural memory in the deep learning artificial neural network into a plurality of parts and operate them in parallel.SOLUTION: In a vector matrix multiplication (VMM) system 3500, specified operations are divided among different sets of circuits. An array 3501a is operated by a column decoder 3505 and an output circuit 3509, an array 3501b is operated by a column decoder 3507 and an output circuit 3511, an array 3501c is operated by a column decoder 3506 and an output circuit 3510, and an array 3501d is operated by a column decoder 3508 and an output circuit 3512. This enables a plurality of read operations and / or program operations to be performed simultaneously on all four arrays at once.SELECTED DRAWING: Figure 35

To provide semiconductor and electronic devices with small circuit area and low power consumption. [Solution] The arithmetic circuit MAC1 is a circuit that performs a sum-of-products operation on a plurality of first data held in a plurality of memory cells described later and a plurality of input second data, and performs an activation function operation using the result of the sum-of-products operation, and comprises a memory cell array CA, a circuit CMS, a circuit WDD, a circuit XLD, a circuit WLD, a circuit INT, and a circuit ACTV. The memory cell array CA comprises memory cells AMx[1] to AMx[m] (where m is an integer of 1 or more), memory cells AMw[1] to AMw[m], memory cells AMu[1] to AMu[m], and memory cells AMR[1] to AMr[m]. In the memory cell array CA, each memory cell is arranged in a matrix of 2m rows and 2 columns.

To provide a semiconductor device equipped with a three-dimensional neural network using a three-dimensional silicon circuit network and independent of bits, and a method for manufacturing the same.SOLUTION: One module containing three units in the Z-axis direction reproduces an information processing mechanism of a human brain by switching the electrical connection of non-volatile memory cells distributed in a three-dimensional array, at the top, there is a Y-direction bit line BLY(i, k+1), at the bottom, there is an X-direction bit line BLX(j, k-2), and cell gates CG(i, j, k+1), CG(i,j,k), and CG(i, j, k-1) are sandwiched between them. Furthermore, an X-direction bit line BLX(j, k) is provided between CG(i, j, k+1) and CG(i, j, k), and a Y-direction bit line BLY(i, k-1) is provided between CG(i, j, k) and CG(i, j, k-1).SELECTED DRAWING: Figure 9

The present invention provides a physical quantity change detection device, a robot system, and a physical quantity change detection method that can reduce the processing load and increase the processing speed. [Solution] The physical quantity change detection device 1 comprises a structure 3 that outputs a speckle pattern of light L when light L is incident on it, and a structure 3 whose output speckle pattern changes when a physical quantity related to the structure 3 changes due to the external environment, and an optical neural network unit 21 that performs neural network calculations on the input light and outputs output light representing the calculation result, and a processing unit 4 that acquires a value corresponding to the change in the physical quantity by an acquisition process that includes inputting at least a part of the speckle pattern to the optical neural network unit 21.

Various embodiments include systems, methods, architectures, mechanisms, and apparatus for providing programmable or pre-programmed in-memory computation (IMC) operations via an array of configurable IMC cores interconnected by a configurable on-chip network to support scalable execution and data flow of applications mapped to the IMC cores.

This invention provides a portable NRD neural response signal generator, comprising: a shell, a display screen, a microcontroller control circuit board, side control buttons, and an input / output connector; the display screen shows the current amplitude of the neural response signal, the output status of the neural response signal, and the battery level; the microcontroller control circuit board acquires the output voltage signal of the electrodes of the cochlear implant and outputs a corresponding simulated neural response signal based on the output voltage signal; the side control buttons are used for power-on operation and selection and confirmation of the neural response signal waveform; the input / output connector is used for programming, battery charging, and signal output. This invention provides equipment support for verifying the accuracy of measuring neural response signals in cochlear implants, solving the problems of high signal interference and insufficient amplitude in existing general-purpose telemetry equipment for measuring neural responses; the waveform shape can be customized, the minimum output waveform amplitude reaches ±50μV, and the waveform is stable and free from external interference.

Minimize the loss of information transmitted. [Solution] The neural network device according to the embodiment comprises a plurality of synaptic circuits and a plurality of neuron circuits. The first neuron circuit among the plurality of neuron circuits is supplied with synaptic current to its first terminal from each of the first synaptic circuits among the plurality of synaptic circuits. The first neuron circuit has a charge storage circuit, a spike output circuit and a cutoff circuit. The charge storage circuit stores charge according to the synaptic current and generates a membrane potential according to the stored charge. The spike output circuit outputs a spike signal when the membrane potential is greater than a preset threshold potential. The cutoff circuit stops the supply of synaptic current from the first terminal to the charge storage circuit during a cutoff period, which is a predetermined time after the spike signal is output.

An oscillation circuit (1) includes diodes (D1, D2, and D3), inductors (L1 and L2), and a power supply unit (V1). The diodes (D1, D2, and D3) are non-linear passive elements having negative differential resistances. In the oscillation circuit (1), the diode (D1) having a first negative differential resistance and a composite inductor (11) are connected in series so as to form an oscillation unit (10). The composite inductor (11) includes the inductors (L1) and (L2) connected in series. The diode (D2) having a second negative differential resistance is connected to the inductor (L1) in parallel. The diode (D3) having a third negative differential resistance is connected to the diode (D1) in series and is connected to the composite inductor (11) in parallel. Then, a burst pulse is output from a common connection point (Vout) of the inductors (L1 and L2) and the diode (D2).

The invention relates to a method for passive target distance measurement at a ground combat vehicle (V), carried out by means of a master image sensor device (10) and a slave image sensor device (20) for observing a target (T), said master image sensor device (10) and said slave image sensor device (20) being arranged at a distance from each other by an offset distance (OD), the method comprises: controlling an orientation of the at least one slave image sensor device (20); determining whether the line-of-sight (L2) of the slave image sensor device (20) intersects the line-of-sight (L1) of the master image sensor device (10) at the position of the target (T); and if intersecting, receiving first angle data representing the orientation of the master image sensor device (10) and second angle data representing the orientation of the slave image sensor device (20). The method further includes determining a target distance (TD) representing a distance between the combat vehicle and the target based on the offset distance (OD) and the received angle data. The invention also relates to a system and a ground combat vehicle.