527results about "Analogue processes for specific applications" patented technology

In a neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation on input data and connection weight coefficients, a computation circuit unit that expresses one connection weight coefficient includes a plurality of selection transistors and a plurality of nonvolatile variable resistance elements. The nonvolatile variable resistance elements each express a weight coefficient with a different weight. Each of the nonvolatile variable resistance elements holds information of an upper digit of an absolute value of a positive weight coefficient, information of a lower digit of the absolute value of the positive weight coefficient, information of an upper digit of an absolute value of a negative weight coefficient, or information of a lower digit of the absolute value of the negative weight coefficient.

The disclosure provides systems and methods for performing analog computing. In one arrangement, an input data stream comprises a plurality of input data units. An analog computational operation is performed on the input data stream to generate an output data stream comprising output data units. Each output data unit comprises a sequence of computed values corresponding to a sequence of symbols of an input data unit corresponding to the output data unit. An output value corresponding to each output data unit is generated by applying encoding functions to the computed values to generate respective encoding waveforms that decay. The output value is generated by sampling a combination of the encoding waveforms at a sampling time. Positions of the encoding waveforms in the sequence represent significances of the symbols of the corresponding input data unit.

A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes first to fourth cells, first and second circuits, and first to fourth current generation circuits. The first cell is electrically connected to the third cell through a first wiring and the first current generation circuit, and is electrically connected to the first circuit through a second wiring. The second cell is electrically connected to the fourth cell through a third wiring and the second current generation circuit, and is electrically connected to the second circuit through a fourth wiring. The third cell is electrically connected to the second cell through the third current generation circuit and the fourth wiring. The fourth cell is electrically connected to the first cell through the fourth current generation circuit and the second wiring. The first and second current generation circuits each function as a current mirror circuit, and the third and fourth current generation circuits each function as an arithmetic circuit of a function system. The first and second cells perform an arithmetic operation of a product, and the third and fourth cells retain the result of the arithmetic operation.

The present invention provides a novel semiconductor device. The present invention uses a comparison unit for comparing two current values, a control unit, and a current output type digital-analog conversion unit to convert an analog signal into a digital signal. The control unit has the function of generating a sign bit indicating the magnitude relation between the two current values, the function of converting, by successive approximation, the difference between the two current values into the digital signal, and the function of outputting the sign bit and the digital signal.

A nervous system emulator engine includes working computational models of the vertebrate nervous system to generate lifelike animal behavior in a robot. These models include functions representing several anatomical features of the vertebrate nervous system, such as spinal cord, brainstem, basal ganglia, thalamus, and cortex. The emulator engine includes a hierarchy of controllers in which controllers at higher levels accomplish goals by continuously specifying desired goals for lower-level controllers. The lowest levels of the hierarchy reflect spinal cord circuits that control muscle tension and length. Moving up the hierarchy into the brainstem and midbrain / cortex, progressively more abstract perceptual variables are controlled. The nervous system emulator engine may be used to build a robot that generates the majority of animal behavior, including human behavior. The nervous system emulator engine may also be used to build working models of nervous system functions for clinical experimentation.

The basis of calculating memory capacity of modern computing is bit. Thus, the number of bits is the unit of information quantity of modern communication. The number of neurons (node number) in the neural networks in human brain is not the unit of the memory capacity of the human being. The complexity of neural network is much greater than the bit capacity. Hence, the current AI, which tries to imitate the human brain using computing with the basis on bits, performs inherently different processing of information from the human brain. In addition, computing based on bit number is always facing the limitation of integration. The present disclosure provides a system of information memory without relying on bits using three-dimensional neural networks. By replacing the electrical connection of non-volatile memory cells, which are distributed in a three-dimensional array, the mechanism of the information processing of the human brain can be imitated.

A neural network computation circuit holds a plurality of connection weight coefficients in one-to-one correspondence with a plurality of input data items, and outputs output data according to a result of a multiply-accumulate operation on the plurality of input data items and the plurality of connection weight coefficients in one-to-one correspondence, and includes at least two bits of semiconductor storage elements provided for each of the plurality of connection weight coefficients, the at least two bits of semiconductor storage elements including a first semiconductor storage element and a second semiconductor storage element that are provided for storing the connection weight coefficient. Each of the plurality of connection weight coefficients corresponds to a total current value that is a sum of a current value of current flowing through the first semiconductor storage element and a current value of current flowing through the second semiconductor storage element.

A method for simulating a photodetector behavior includes: receiving an input waveform for an photodetector; receiving an input optical power and a reverse bias voltage for the photodetector; searching for, in a lookup-table library, model parameters for a photodetector behavior model based on the input optical power and the reverse bias voltage; and outputting a second waveform from the photodetector behavior model, where the second waveform is indicative of an electrical response of the photodetector receiving the input waveform.

To provide a semiconductor device having a novel configuration.SOLUTION: A first storage circuit unit includes a first storage circuit that holds a plurality of pieces of first weight data. A second storage circuit unit includes a second storage circuit that holds a plurality of pieces of second weight data. A first arithmetic circuit unit includes a first arithmetic circuit, a first switching circuit, and a third switching circuit. A second arithmetic circuit unit includes a second arithmetic circuit, a second switching circuit, and a fourth switching circuit. The first switching circuit includes a function of providing any one of the plurality of pieces of first weight data to first wiring. The second switching circuit includes a function of providing any one of the plurality of pieces of second weight data to second wiring. The third switching circuit includes a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the first arithmetic circuit. The fourth switching circuit includes a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the second arithmetic circuit.SELECTED DRAWING: Figure 1

To provide a node and a reservoir element excellent in short-term storage performance.SOLUTION: The node comprises a first input terminal, a second input terminal, a first signal holding circuit, and a first output terminal. The first input terminal is configured to be connectable to an input source transmitting an input signal to a reservoir element. The second input terminal is configured to be connectable to at least one or more other nodes. A first terminal of the first signal holding circuit is connected to the first input terminal and the second input terminal. A second terminal of the first signal holding circuit is connected to the first output terminal. The first output terminal is configured to be connectable to the at least one or more other nodes. The first signal holding circuit holds and converts a confluent signal obtained by joining the input signal and a propagation signal from the second input terminal.SELECTED DRAWING: Figure 4

A memory cell capable of reversing magnetization on the basis of voltage drive is achieved without providing a selector element in the memory cell. A storage device includes: a memory cell provided with a magnetoresistive effect element; a word line connected to one end of the magnetoresistive effect element; and a bit line connected to another end of the magnetoresistive effect element. The magnetoresistive effect element may have a voltage controlled magnetic anisotropy (VCMA) effect. A driver configured to apply a reversing voltage for reversing a magnetization direction of the magnetoresistive effect element on the basis of the VCMA effect may be included. The driver may switch a voltage applied to the memory cell such that a reversing voltage is applied to a selected cell while a non-reversing voltage is applied to a non-selected cell, in which the non-reversing voltage does not reverse a magnetization direction of the magnetoresistive effect element.

An operation method of a semiconductor device that performs data writing and correction processing is provided. The operation method is for a semiconductor device including a control circuit, a first circuit, a second circuit, a wiring, a cell, and a converter circuit. In the operation method, first, the control circuit transmits, to the first circuit, a first signal corresponding to the value of first data. Next, the first circuit outputs, to the wiring, a first current with an amount corresponding to the first signal. Moreover, the cell retains a first potential corresponding to the amount of first current. Then, the cell makes a second current corresponding to the first potential flow from the wiring, and the converter circuit outputs a second signal corresponding to the amount of second current. Next, the second circuit obtains a difference value between a value corresponding to the second signal and the value of the first data. If the difference value is 0, the operation is terminated. If the difference value is not 0, the control circuit generates an update value obtained by adding the difference value to a value corresponding to the first signal previously transmitted. The first circuit obtains the first signal corresponding to the update value and outputs the updated first current to the cell.

A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes a first arithmetic portion that performs a digital arithmetic operation and a second arithmetic portion that performs an analog arithmetic operation. In an arithmetic operation of a convolutional neural network, the first arithmetic portion executes an arithmetic operation of a convolution layer, and the second arithmetic portion executes an arithmetic operation of a fully connected layer. The convolution layer often uses the same filter value repeatedly; thus, the first arithmetic portion is configured to execute a plurality of product-sum operations at the same time with single input of the same filter value and with input of a plurality of pieces of data to be subjected to convolution processing. Since the fully connected layer needs weight coefficients as many as the product of the number of pieces of input data and the number of pieces of output data, the second arithmetic portion has a structure in which arithmetic cells arranged in a matrix retain the weight coefficients and the input data is transmitted in the row directions, whereby the output data is output in the column directions.

An artificial neuron unit for processing a signal is presented, comprising: a fiber-based optical processing unit having first and second optical input ports and first and second optical output ports, configured and operative to controllably apply optical processing to incoherent input optical signals to generate first and second weighted combined optical signals; and an electro-optical processing unit configured and operative to process the first and second weighted combined optical signals, the electro-optical processing unit configured and operative to generate a weighted sum output of the artificial neuron unit by successively performing the steps of applying a predetermined mathematical function to the first and second weighted combined optical signals corresponding to positive and negative weights to generate a resultant signal, and applying nonlinear processing to the resultant signal to convert the resultant signal into an optical output signal indicative of the weighted sum output of the artificial neuron unit.

Numerous embodiments are disclosed for reading or verifying values ​​stored in selected memory cells in a vector matrix multiplication (VMM) array in an artificial neural network. In one embodiment, the input includes a set of input bits resulting in a series of input signals applied to terminals of the selected memory cells, which are further digitized and shifted based on the bit locations of corresponding input bits in the set of input bits, resulting in a series of output signals that are summed to generate an output indicative of the value stored in the selected memory cells.

This solution addresses the challenges of reduced learning accuracy and reproducibility in the integration of short-term plasticity (STP) and long-term plasticity (LTP) at the single-element level, due to adjacent element interference and difficulties in non-destructive readout. [Solution] This system utilizes a neuromorphic circuit array based on single elements capable of expressing STP and LTP, and reduces adjacent element interference through interference suppression circuits and common electrode control. The internal state of a single element can be read non-destructively, enabling STP→LTP transitions and spike timing-dependent plasticity (STDP) control according to input pulse conditions. This enables stable and highly reproducible learning operations even in large-scale arrays, improving neuromorphic computation performance.

To provide an analog neural memory system and method that has an input block and an output block which are configurable and a physical layout and that uses a nonvolatile memory cell.SOLUTION: In a vector matrix multiplication (VMM) system 3400, an input circuit block 3409 (3410) supports different numbers of arrays 3401, 3402 (3403, 3404) arranged in a horizontal direction, and an output circuit block 3411 (3412) supports different numbers of arrays 3401, 3403 (3402, 3404) arranged in a vertical direction.SELECTED DRAWING: Figure 34

To provide arithmetic unit and method capable of performing a multiplication operation on input data with different data types.SOLUTION: An arithmetic unit in an embodiment can include a controller that receives first input data of a first data type and second input data of a second data type different from the first data type, and outputs a first signal expressing the first data type, a second signal expressing the second data type, and a clock signal based on the number of bits of the first input data and the second input data, and an arithmetic circuit that generates output data by performing a multiplication operation on the first input data and the second input data on the basis of the first signal, the second signal, and the clock signal.SELECTED DRAWING: Figure 6

[Problem] To provide a quantum circuit that performs arithmetic operations for changing propositions by making the flow of positive calculations reversible. [Solution] A quantum circuit used in a quantum computer, the quantum circuit being characterized in that an inverse-function space is generated with a function obtained from an intersection of an arbitrary string and a rev function as an axis, and the inverse-function space is used for calculation.

To provide a semiconductor device that restores degraded data.SOLUTION: A semiconductor device includes a first circuit, a storage unit, and a calculation unit, in which the first circuit has a current source and a first switch, the storage unit has a first transistor and a first capacitor, and the calculation unit has a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch, a first terminal of the first switch is electrically connected to an output terminal of the current source, and a second terminal of the first switch is electrically connected to a first terminal of the second transistor. Upon restoring data held in the storage unit, the first transistor is turned into an ON state to provide the data held in the storage unit to the control terminal of the first switch via the first transistor. The first switch turns into either of an ON state and an OFF state depending on the data and applies the current to the calculation unit from the current source via the second transistor to replenish electric charges to a holding unit of the calculation unit.SELECTED DRAWING: Figure 1

Oil or gas fields and associated facilities are computer simulated by solving linear algebraic equations using a Schwarz method with at least one well node included in the overlap. According to another aspect, equations for the wellbore nodes are processed to eliminate some non-pressure variables, e.g. component compositions. Other features are also provided.

To provide a system and method, which greatly increase speed, resolution, and power efficiency as compared to digital spatial convolutions for optically processing images.SOLUTION: A photonic neural network system 10 for convolving and adding frames of data includes a first sensor display device 14 and a second sensor display device 26. Each sensor display device comprises an array of transmit-receive modules. Each transmit-receive module comprises a light sensor element, a light transmitter element, and a memory bank. A radial modulator device 20 is positioned where transmission of light fields including frames of data are Fourier transformed. Filters implemented by modulator elements of the radial modulator device 20 convolve fields of light including the frames of data, which are then sensed on a pixel-by-pixel basis by the light sensor elements, which accumulate charges, thus sum pixel values of sequential convolved frames of data.SELECTED DRAWING: Figure 1

To provide an improved decoding system and physical layout for an analog neural memory system which uses a non-volatile memory cell.SOLUTION: An analog neural memory system includes a plurality of vector matrix multiplication arrays, a plurality of low voltage row decoders, and a plurality of global high voltage row decoders. Each of the low voltage row decoders provides a row decoder function for one of the plurality of vector matrix multiplication arrays, and each of the global high voltage row decoders is shared by two of the plurality of vector matrix multiplication arrays and provides a high voltage signal to two of the plurality of low voltage row decoders.SELECTED DRAWING: None

The thermodynamic computing platform samples multivariate distributions (e.g., multivariate Gaussian distributions) using a network of coupled analog unit cells controlled by a digital processor. The analog unit cells are capacitively, resistively, and / or inductively coupled to each other. Each analog unit cell contains an adjustable resistor, capacitor, inductor, current source, and / or voltage source. The digital processor sets initial values ​​for these components. These values, or input parameters, represent the multivariate distribution. The network of coupled analog unit cells is then evolved through a series of time steps until thermal equilibrium is reached. As the network evolves, the digital processor samples voltages at nodes in the network at each time step. These voltages represent samples of the multivariate distribution.

To detect anomalies in an excellent-accuracy and high-speed manner with a simplified configuration.SOLUTION: An anomaly detection device comprises an input unit, a reservoir unit, an output unit, and a determination unit. The input unit outputs a plurality of intermediary signals in accordance with a time-series input signal detected by observing an observation target device. The reservoir unit acquires the plurality of intermediary signals, and outputs a plurality of output signals each having a waveform having reproducibility in respect to a waveform of the input signal. The output unit generates a plurality of multiplication signals by multiplying output weights preset with respect to each of the plurality of output signals, and generates an integral signal obtained by time integration through adding up the plurality of multiplication signals. The determination unit determines whether the observation target device is normal or abnormal based on a result of comparison between the integral signal and a preset threshold, and outputs a determination signal representing a determination result. The output weights represent a positive prescribed value or a negative prescribed value, and are respectively set for the plurality of output signals.SELECTED DRAWING: Figure 2

A motor selection device (10) comprising: a speed calculation unit (16) configured to calculate a motor selection speed from a speed waveform of a motor configured to drive a specific driven object, taking into account iron losses generated in a target motor serving as an object to be selected, the speed waveform being obtained when the driven object is made to perform a prescribed operation, a storage unit (22) configured to store a motor characteristic associated with a speed of the target motor serving as the object to be selected, and a determination unit (24) configured to determine whether or not the prescribed operation is possible by the target motor, wherein the motor characteristic is used at the motor selection speed.

A spiking neuron circuit system 100 includes: a charging circuit 10 that, when an input voltage is applied, starts charging of a capacitor 12 by an output current I of a field effect transistor 11; a pulse generation circuit 20 that generates and outputs a pulse signal when a charging voltage of the capacitor 12 reaches a first threshold value; and a control circuit 50 that controls the output current I of the field effect transistor 11 by controlling a bulk voltage and / or a gate voltage of the field effect transistor 11.