255results about "Analogue processes for specific applications" patented technology

A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes first to fourth cells, first and second circuits, and first to fourth current generation circuits. The first cell is electrically connected to the third cell through a first wiring and the first current generation circuit, and is electrically connected to the first circuit through a second wiring. The second cell is electrically connected to the fourth cell through a third wiring and the second current generation circuit, and is electrically connected to the second circuit through a fourth wiring. The third cell is electrically connected to the second cell through the third current generation circuit and the fourth wiring. The fourth cell is electrically connected to the first cell through the fourth current generation circuit and the second wiring. The first and second current generation circuits each function as a current mirror circuit, and the third and fourth current generation circuits each function as an arithmetic circuit of a function system. The first and second cells perform an arithmetic operation of a product, and the third and fourth cells retain the result of the arithmetic operation.

The basis of calculating memory capacity of modern computing is bit. Thus, the number of bits is the unit of information quantity of modern communication. The number of neurons (node number) in the neural networks in human brain is not the unit of the memory capacity of the human being. The complexity of neural network is much greater than the bit capacity. Hence, the current AI, which tries to imitate the human brain using computing with the basis on bits, performs inherently different processing of information from the human brain. In addition, computing based on bit number is always facing the limitation of integration. The present disclosure provides a system of information memory without relying on bits using three-dimensional neural networks. By replacing the electrical connection of non-volatile memory cells, which are distributed in a three-dimensional array, the mechanism of the information processing of the human brain can be imitated.

A method for simulating a photodetector behavior includes: receiving an input waveform for an photodetector; receiving an input optical power and a reverse bias voltage for the photodetector; searching for, in a lookup-table library, model parameters for a photodetector behavior model based on the input optical power and the reverse bias voltage; and outputting a second waveform from the photodetector behavior model, where the second waveform is indicative of an electrical response of the photodetector receiving the input waveform.

To provide a semiconductor device having a novel configuration.SOLUTION: A first storage circuit unit includes a first storage circuit that holds a plurality of pieces of first weight data. A second storage circuit unit includes a second storage circuit that holds a plurality of pieces of second weight data. A first arithmetic circuit unit includes a first arithmetic circuit, a first switching circuit, and a third switching circuit. A second arithmetic circuit unit includes a second arithmetic circuit, a second switching circuit, and a fourth switching circuit. The first switching circuit includes a function of providing any one of the plurality of pieces of first weight data to first wiring. The second switching circuit includes a function of providing any one of the plurality of pieces of second weight data to second wiring. The third switching circuit includes a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the first arithmetic circuit. The fourth switching circuit includes a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the second arithmetic circuit.SELECTED DRAWING: Figure 1

A memory cell capable of reversing magnetization on the basis of voltage drive is achieved without providing a selector element in the memory cell. A storage device includes: a memory cell provided with a magnetoresistive effect element; a word line connected to one end of the magnetoresistive effect element; and a bit line connected to another end of the magnetoresistive effect element. The magnetoresistive effect element may have a voltage controlled magnetic anisotropy (VCMA) effect. A driver configured to apply a reversing voltage for reversing a magnetization direction of the magnetoresistive effect element on the basis of the VCMA effect may be included. The driver may switch a voltage applied to the memory cell such that a reversing voltage is applied to a selected cell while a non-reversing voltage is applied to a non-selected cell, in which the non-reversing voltage does not reverse a magnetization direction of the magnetoresistive effect element.

A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes a first arithmetic portion that performs a digital arithmetic operation and a second arithmetic portion that performs an analog arithmetic operation. In an arithmetic operation of a convolutional neural network, the first arithmetic portion executes an arithmetic operation of a convolution layer, and the second arithmetic portion executes an arithmetic operation of a fully connected layer. The convolution layer often uses the same filter value repeatedly; thus, the first arithmetic portion is configured to execute a plurality of product-sum operations at the same time with single input of the same filter value and with input of a plurality of pieces of data to be subjected to convolution processing. Since the fully connected layer needs weight coefficients as many as the product of the number of pieces of input data and the number of pieces of output data, the second arithmetic portion has a structure in which arithmetic cells arranged in a matrix retain the weight coefficients and the input data is transmitted in the row directions, whereby the output data is output in the column directions.

An artificial neuron unit for processing a signal is presented, comprising: a fiber-based optical processing unit having first and second optical input ports and first and second optical output ports, configured and operative to controllably apply optical processing to incoherent input optical signals to generate first and second weighted combined optical signals; and an electro-optical processing unit configured and operative to process the first and second weighted combined optical signals, the electro-optical processing unit configured and operative to generate a weighted sum output of the artificial neuron unit by successively performing the steps of applying a predetermined mathematical function to the first and second weighted combined optical signals corresponding to positive and negative weights to generate a resultant signal, and applying nonlinear processing to the resultant signal to convert the resultant signal into an optical output signal indicative of the weighted sum output of the artificial neuron unit.

This solution addresses the challenges of reduced learning accuracy and reproducibility in the integration of short-term plasticity (STP) and long-term plasticity (LTP) at the single-element level, due to adjacent element interference and difficulties in non-destructive readout. [Solution] This system utilizes a neuromorphic circuit array based on single elements capable of expressing STP and LTP, and reduces adjacent element interference through interference suppression circuits and common electrode control. The internal state of a single element can be read non-destructively, enabling STP→LTP transitions and spike timing-dependent plasticity (STDP) control according to input pulse conditions. This enables stable and highly reproducible learning operations even in large-scale arrays, improving neuromorphic computation performance.

[Problem] To provide a quantum circuit that performs arithmetic operations for changing propositions by making the flow of positive calculations reversible. [Solution] A quantum circuit used in a quantum computer, the quantum circuit being characterized in that an inverse-function space is generated with a function obtained from an intersection of an arbitrary string and a rev function as an axis, and the inverse-function space is used for calculation.

To provide a semiconductor device that restores degraded data.SOLUTION: A semiconductor device includes a first circuit, a storage unit, and a calculation unit, in which the first circuit has a current source and a first switch, the storage unit has a first transistor and a first capacitor, and the calculation unit has a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch, a first terminal of the first switch is electrically connected to an output terminal of the current source, and a second terminal of the first switch is electrically connected to a first terminal of the second transistor. Upon restoring data held in the storage unit, the first transistor is turned into an ON state to provide the data held in the storage unit to the control terminal of the first switch via the first transistor. The first switch turns into either of an ON state and an OFF state depending on the data and applies the current to the calculation unit from the current source via the second transistor to replenish electric charges to a holding unit of the calculation unit.SELECTED DRAWING: Figure 1

To provide a system and method, which greatly increase speed, resolution, and power efficiency as compared to digital spatial convolutions for optically processing images.SOLUTION: A photonic neural network system 10 for convolving and adding frames of data includes a first sensor display device 14 and a second sensor display device 26. Each sensor display device comprises an array of transmit-receive modules. Each transmit-receive module comprises a light sensor element, a light transmitter element, and a memory bank. A radial modulator device 20 is positioned where transmission of light fields including frames of data are Fourier transformed. Filters implemented by modulator elements of the radial modulator device 20 convolve fields of light including the frames of data, which are then sensed on a pixel-by-pixel basis by the light sensor elements, which accumulate charges, thus sum pixel values of sequential convolved frames of data.SELECTED DRAWING: Figure 1

The thermodynamic computing platform samples multivariate distributions (e.g., multivariate Gaussian distributions) using a network of coupled analog unit cells controlled by a digital processor. The analog unit cells are capacitively, resistively, and / or inductively coupled to each other. Each analog unit cell contains an adjustable resistor, capacitor, inductor, current source, and / or voltage source. The digital processor sets initial values ​​for these components. These values, or input parameters, represent the multivariate distribution. The network of coupled analog unit cells is then evolved through a series of time steps until thermal equilibrium is reached. As the network evolves, the digital processor samples voltages at nodes in the network at each time step. These voltages represent samples of the multivariate distribution.

To detect anomalies in an excellent-accuracy and high-speed manner with a simplified configuration.SOLUTION: An anomaly detection device comprises an input unit, a reservoir unit, an output unit, and a determination unit. The input unit outputs a plurality of intermediary signals in accordance with a time-series input signal detected by observing an observation target device. The reservoir unit acquires the plurality of intermediary signals, and outputs a plurality of output signals each having a waveform having reproducibility in respect to a waveform of the input signal. The output unit generates a plurality of multiplication signals by multiplying output weights preset with respect to each of the plurality of output signals, and generates an integral signal obtained by time integration through adding up the plurality of multiplication signals. The determination unit determines whether the observation target device is normal or abnormal based on a result of comparison between the integral signal and a preset threshold, and outputs a determination signal representing a determination result. The output weights represent a positive prescribed value or a negative prescribed value, and are respectively set for the plurality of output signals.SELECTED DRAWING: Figure 2

A motor selection device (10) comprising: a speed calculation unit (16) configured to calculate a motor selection speed from a speed waveform of a motor configured to drive a specific driven object, taking into account iron losses generated in a target motor serving as an object to be selected, the speed waveform being obtained when the driven object is made to perform a prescribed operation, a storage unit (22) configured to store a motor characteristic associated with a speed of the target motor serving as the object to be selected, and a determination unit (24) configured to determine whether or not the prescribed operation is possible by the target motor, wherein the motor characteristic is used at the motor selection speed.

A spiking neuron circuit system 100 includes: a charging circuit 10 that, when an input voltage is applied, starts charging of a capacitor 12 by an output current I of a field effect transistor 11; a pulse generation circuit 20 that generates and outputs a pulse signal when a charging voltage of the capacitor 12 reaches a first threshold value; and a control circuit 50 that controls the output current I of the field effect transistor 11 by controlling a bulk voltage and / or a gate voltage of the field effect transistor 11.

To provide an information storage system which simulates a neural network on a silicon chip without using a bit.SOLUTION: A neural network has: a plurality of islands periodically disposed in a first axis direction and a second axis direction on a surface of a semiconductor device; a first link and a second link disposed between two islands adjacent to each other in the first direction and the second direction among the plurality of islands; and a first word line in a third axis direction; and a second word line in a fourth axis direction. Each of the plurality of islands has a diffusion layer formed on the surface of the semiconductor device. The first link is a first selection gate for bridging the two islands adjacent to each other in the first direction among the plurality of islands. The second link is a second selection gate for bridging the two islands adjacent to each other in the second direction among the plurality of islands. The first selection gate and the second selection gate have respective selection gate contacts. The selection gate contact is selected by the first word line and the second word line.SELECTED DRAWING: Figure 7

The standard for calculating memory capacity in modern computing is the bit, and the number of transistors (elements) that make up a node, i.e., the number of bits, is also the unit of modern information communication volume. In contrast, the human brain is made up of neural circuits, and human memory capacity is not based on the number of neural circuits (number of nodes). nerves Circuit complexity far exceeds bit capacity, and modern AI that attempts to replicate the human brain through bit-based computing is inherently wasteful because it handles information in a fundamentally different way. Moreover, bit-based computing is always at the limit of integration. The present invention provides a bit-independent information storage system using a three-dimensional silicon circuit network. [Solution] By switching the electrical connections of non-volatile memory cells distributed in a three-dimensional array, Reproducing the information processing mechanism of the human brain.

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

The invention provides a non-common-ground attack angle signal acquisition and calculation circuit and method. The non-common-ground attack angle signal acquisition and calculation circuit comprises a step-down follower circuit, an isolation operational amplifier circuit, an isolation power supply circuit and an A / D acquisition and MCU calculation circuit, an isolation operational amplifier circuit is used for isolating and collecting a tap voltage signal and an excitation positive voltage signal which are output by the attack angle alarm system passing through the step-down follower circuit, and outputting the tap voltage signal and the excitation positive voltage signal to an A / D collection and MCU resolving circuit, so that collection of non-common ground attack angle signals is realized; the isolation power supply circuit provides reference voltage for the input ends of the voltage reduction follower circuit and the isolation operational amplifier circuit; the reference voltage of the output end of the isolation operational amplifier circuit is connected to the A / D acquisition and MCU resolving circuit; the A / D acquisition and MCU resolving circuit is used for resolving a local attack angle and a true attack angle; non-common-ground attack angle signals can be effectively collected under the condition that an original system is not affected.

A semiconductor device capable of performing product-sum operations with reduced power consumption is provided. [Solution] A semiconductor device has first and second cells, a first circuit, and first to third wirings. Each of the first and second cells has a capacitance, and a first terminal of each capacitance is electrically connected to a third wiring. Each of the first and second cells has a function of flowing a current corresponding to a potential held at a second terminal of the capacitance to the first and second wirings. The first circuit is electrically connected to the first and second wirings, and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wire changes, the amount of current in the first wire changes from I1 to I3, and the amount of current in the second wire changes from I2 to I4, the first circuit generates a current of I1-I2-I3+I4. Note that the change in the third wire is achieved by first inputting a reference potential to the third wire, and then inputting a potential corresponding to internal data or information obtained by a sensor.

This system provides a mechanism for calibrating electrical parameters in deep learning artificial neural networks. [Solution] The system comprises a digital-to-analog converter for receiving k bits of input and generating a first analog output, a mapping scalar for converting the first analog output to a second analog output, and an analog-to-digital converter for generating an n-bit output from the second analog output, where n is a different value from k.

Provided is a semiconductor device that can retain data to be used for computation for a long period of time. The semiconductor device comprises a computation cell and a drive cell. The computation cell and the drive cell each include first to third transistors, first and second capacitor elements, and a first amplification circuit. A first terminal of the first transistor is electrically connected to a gate of the third transistor, an input terminal of the first amplification circuit, and a first terminal of the first capacitor element. A second terminal of the first transistor is electrically connected to a first terminal of the second transistor, an output terminal of the first amplification circuit, and a first terminal of the second capacitor element. The first amplification circuit functions as a buffer circuit that outputs an analog potential. Electric charge is replenished to the first terminal of the second capacitor element by the first amplification circuit on the basis of the electric potential of the first terminal of the first capacitor element, thereby preventing leakage current between the source and the drain of each of the first transistor and the second transistor.

To provide a semiconductor device capable of efficiently performing reading of weight coefficients and multiply-accumulate operations.SOLUTION: A semiconductor device includes a multiply-accumulate circuit and a storage device. The multiply-accumulate circuit is configured using transistors formed in a semiconductor substrate, and memory cells of a storage device are configured using OS transistors stacked above the semiconductor substrate. The semiconductor device includes a plurality of multiply-accumulate units in which the multiply-accumulate circuit and the memory cells of the storage device are electrically connected. and in each multiply-accumulate unit, weight coefficients stored in the memory cells can be read and subjected to multiply-accumulate operations.SELECTED DRAWING: Figure 1

A disclosed method for designing a prosthetic element is executable prior to a cutting of a tooth of a patient for placing the prosthetic element.

The present invention improves learning accuracy in a semiconductor device that performs machine learning.　This semiconductor device includes a prescribed number of memory cells, a driver, and a control circuit. In the semiconductor device, the driver supplies a write pulse to each of the memory cells. Further, the control circuit sequentially performs course tuning for controlling, to a prescribed value, a statistical amount of a change amount of the reciprocal of the impedance of the memory cell for each write pulse, and fine tuning for controlling the statistical amount to a value smaller than the prescribed value.

Numerous embodiments are disclosed for an input circuit for an analog neural memory in a deep learning artificial neural network.

To generate a model for detecting biological signals and to detect abnormal biological signals using the model with a monitor of the biological signal.SOLUTION: A device 1 for detecting abnormal biological signals can communicate with a sensor 2 and one or more external control devices 31, 32, 33, 34. The device 1 receives input data collected by the sensor 2. The sensor 2 emits radio waves toward a human body being the monitoring object, receives radio waves reflected from the surface of the object, and thereby collects characteristics relating to the shape or movement of the object. Thus, the sensor 2 collects changes in the thorax caused by respiration or heartbeat of the human body being the monitoring object. The obtained data is input to a neural network learned on the basis of predetermined learning data in a neuromorphic device that implements the neural network for detecting abnormal biological signals, thereby detecting abnormal biological signals.SELECTED DRAWING: Figure 5

Electronic circuit for implementing a Bayesian neural network The invention relates to an electronic circuit (10) for implementing a Bayesian neural network, comprising bit, source and word lines;and - at least one primary branch (15), each comprising a primary cell (30) connected between source and bit lines and including a primary memory component (32) and a primary switch (34) connected in series, - at least one secondary branch (20), each comprising a secondary cell (50) connected between source and bit lines and including a secondary memory component (52) and a secondary switch (54) connected together, - an accumulation device (25) configured to accumulate a total quantity being the sum of a primary quantity of charges from a primary cell and a secondary quantity of charges from a secondary cell, the primary and secondary quantities being accumulated independently of each other. Figure for the abstract: Figure 1;

To provide a semiconductor device that can perform multiply-accumulate operations with low power consumption. [Solution] An arithmetic circuit having circuits MC and MCr, wherein circuit MC has a holding node nd1, and circuit MCr has a holding node nd1r. Circuits MC and MCr are electrically connected to input wirings X1L and X2L and wirings OL and OLB, respectively, and each of circuits MC and MCr holds first and second potentials corresponding to first data in its respective holding node. When a potential corresponding to second data is input to input wirings X1L and X2L, circuit MC outputs a current to one of wirings OL or OLB, and circuit MCr outputs a current to the other of wirings OL or OLB. The current that circuits MC and MCr output to wirings OL or OLB is determined according to the first and second potentials held in the holding nodes nd1 and nd1r.