367results about "Analogue processes for specific applications" patented technology

A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes first to fourth cells, first and second circuits, and first to fourth current generation circuits. The first cell is electrically connected to the third cell through a first wiring and the first current generation circuit, and is electrically connected to the first circuit through a second wiring. The second cell is electrically connected to the fourth cell through a third wiring and the second current generation circuit, and is electrically connected to the second circuit through a fourth wiring. The third cell is electrically connected to the second cell through the third current generation circuit and the fourth wiring. The fourth cell is electrically connected to the first cell through the fourth current generation circuit and the second wiring. The first and second current generation circuits each function as a current mirror circuit, and the third and fourth current generation circuits each function as an arithmetic circuit of a function system. The first and second cells perform an arithmetic operation of a product, and the third and fourth cells retain the result of the arithmetic operation.

The present invention provides a novel semiconductor device. The present invention uses a comparison unit for comparing two current values, a control unit, and a current output type digital-analog conversion unit to convert an analog signal into a digital signal. The control unit has the function of generating a sign bit indicating the magnitude relation between the two current values, the function of converting, by successive approximation, the difference between the two current values into the digital signal, and the function of outputting the sign bit and the digital signal.

The basis of calculating memory capacity of modern computing is bit. Thus, the number of bits is the unit of information quantity of modern communication. The number of neurons (node number) in the neural networks in human brain is not the unit of the memory capacity of the human being. The complexity of neural network is much greater than the bit capacity. Hence, the current AI, which tries to imitate the human brain using computing with the basis on bits, performs inherently different processing of information from the human brain. In addition, computing based on bit number is always facing the limitation of integration. The present disclosure provides a system of information memory without relying on bits using three-dimensional neural networks. By replacing the electrical connection of non-volatile memory cells, which are distributed in a three-dimensional array, the mechanism of the information processing of the human brain can be imitated.

A method for simulating a photodetector behavior includes: receiving an input waveform for an photodetector; receiving an input optical power and a reverse bias voltage for the photodetector; searching for, in a lookup-table library, model parameters for a photodetector behavior model based on the input optical power and the reverse bias voltage; and outputting a second waveform from the photodetector behavior model, where the second waveform is indicative of an electrical response of the photodetector receiving the input waveform.

To provide a semiconductor device having a novel configuration.SOLUTION: A first storage circuit unit includes a first storage circuit that holds a plurality of pieces of first weight data. A second storage circuit unit includes a second storage circuit that holds a plurality of pieces of second weight data. A first arithmetic circuit unit includes a first arithmetic circuit, a first switching circuit, and a third switching circuit. A second arithmetic circuit unit includes a second arithmetic circuit, a second switching circuit, and a fourth switching circuit. The first switching circuit includes a function of providing any one of the plurality of pieces of first weight data to first wiring. The second switching circuit includes a function of providing any one of the plurality of pieces of second weight data to second wiring. The third switching circuit includes a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the first arithmetic circuit. The fourth switching circuit includes a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the second arithmetic circuit.SELECTED DRAWING: Figure 1

A memory cell capable of reversing magnetization on the basis of voltage drive is achieved without providing a selector element in the memory cell. A storage device includes: a memory cell provided with a magnetoresistive effect element; a word line connected to one end of the magnetoresistive effect element; and a bit line connected to another end of the magnetoresistive effect element. The magnetoresistive effect element may have a voltage controlled magnetic anisotropy (VCMA) effect. A driver configured to apply a reversing voltage for reversing a magnetization direction of the magnetoresistive effect element on the basis of the VCMA effect may be included. The driver may switch a voltage applied to the memory cell such that a reversing voltage is applied to a selected cell while a non-reversing voltage is applied to a non-selected cell, in which the non-reversing voltage does not reverse a magnetization direction of the magnetoresistive effect element.

A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes a first arithmetic portion that performs a digital arithmetic operation and a second arithmetic portion that performs an analog arithmetic operation. In an arithmetic operation of a convolutional neural network, the first arithmetic portion executes an arithmetic operation of a convolution layer, and the second arithmetic portion executes an arithmetic operation of a fully connected layer. The convolution layer often uses the same filter value repeatedly; thus, the first arithmetic portion is configured to execute a plurality of product-sum operations at the same time with single input of the same filter value and with input of a plurality of pieces of data to be subjected to convolution processing. Since the fully connected layer needs weight coefficients as many as the product of the number of pieces of input data and the number of pieces of output data, the second arithmetic portion has a structure in which arithmetic cells arranged in a matrix retain the weight coefficients and the input data is transmitted in the row directions, whereby the output data is output in the column directions.

An artificial neuron unit for processing a signal is presented, comprising: a fiber-based optical processing unit having first and second optical input ports and first and second optical output ports, configured and operative to controllably apply optical processing to incoherent input optical signals to generate first and second weighted combined optical signals; and an electro-optical processing unit configured and operative to process the first and second weighted combined optical signals, the electro-optical processing unit configured and operative to generate a weighted sum output of the artificial neuron unit by successively performing the steps of applying a predetermined mathematical function to the first and second weighted combined optical signals corresponding to positive and negative weights to generate a resultant signal, and applying nonlinear processing to the resultant signal to convert the resultant signal into an optical output signal indicative of the weighted sum output of the artificial neuron unit.

This solution addresses the challenges of reduced learning accuracy and reproducibility in the integration of short-term plasticity (STP) and long-term plasticity (LTP) at the single-element level, due to adjacent element interference and difficulties in non-destructive readout. [Solution] This system utilizes a neuromorphic circuit array based on single elements capable of expressing STP and LTP, and reduces adjacent element interference through interference suppression circuits and common electrode control. The internal state of a single element can be read non-destructively, enabling STP→LTP transitions and spike timing-dependent plasticity (STDP) control according to input pulse conditions. This enables stable and highly reproducible learning operations even in large-scale arrays, improving neuromorphic computation performance.

To provide arithmetic unit and method capable of performing a multiplication operation on input data with different data types.SOLUTION: An arithmetic unit in an embodiment can include a controller that receives first input data of a first data type and second input data of a second data type different from the first data type, and outputs a first signal expressing the first data type, a second signal expressing the second data type, and a clock signal based on the number of bits of the first input data and the second input data, and an arithmetic circuit that generates output data by performing a multiplication operation on the first input data and the second input data on the basis of the first signal, the second signal, and the clock signal.SELECTED DRAWING: Figure 6

[Problem] To provide a quantum circuit that performs arithmetic operations for changing propositions by making the flow of positive calculations reversible. [Solution] A quantum circuit used in a quantum computer, the quantum circuit being characterized in that an inverse-function space is generated with a function obtained from an intersection of an arbitrary string and a rev function as an axis, and the inverse-function space is used for calculation.

To provide a semiconductor device that restores degraded data.SOLUTION: A semiconductor device includes a first circuit, a storage unit, and a calculation unit, in which the first circuit has a current source and a first switch, the storage unit has a first transistor and a first capacitor, and the calculation unit has a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch, a first terminal of the first switch is electrically connected to an output terminal of the current source, and a second terminal of the first switch is electrically connected to a first terminal of the second transistor. Upon restoring data held in the storage unit, the first transistor is turned into an ON state to provide the data held in the storage unit to the control terminal of the first switch via the first transistor. The first switch turns into either of an ON state and an OFF state depending on the data and applies the current to the calculation unit from the current source via the second transistor to replenish electric charges to a holding unit of the calculation unit.SELECTED DRAWING: Figure 1

Oil or gas fields and associated facilities are computer simulated by solving linear algebraic equations using a Schwarz method with at least one well node included in the overlap. According to another aspect, equations for the wellbore nodes are processed to eliminate some non-pressure variables, e.g. component compositions. Other features are also provided.

To provide a system and method, which greatly increase speed, resolution, and power efficiency as compared to digital spatial convolutions for optically processing images.SOLUTION: A photonic neural network system 10 for convolving and adding frames of data includes a first sensor display device 14 and a second sensor display device 26. Each sensor display device comprises an array of transmit-receive modules. Each transmit-receive module comprises a light sensor element, a light transmitter element, and a memory bank. A radial modulator device 20 is positioned where transmission of light fields including frames of data are Fourier transformed. Filters implemented by modulator elements of the radial modulator device 20 convolve fields of light including the frames of data, which are then sensed on a pixel-by-pixel basis by the light sensor elements, which accumulate charges, thus sum pixel values of sequential convolved frames of data.SELECTED DRAWING: Figure 1

To provide an improved decoding system and physical layout for an analog neural memory system which uses a non-volatile memory cell.SOLUTION: An analog neural memory system includes a plurality of vector matrix multiplication arrays, a plurality of low voltage row decoders, and a plurality of global high voltage row decoders. Each of the low voltage row decoders provides a row decoder function for one of the plurality of vector matrix multiplication arrays, and each of the global high voltage row decoders is shared by two of the plurality of vector matrix multiplication arrays and provides a high voltage signal to two of the plurality of low voltage row decoders.SELECTED DRAWING: None

The thermodynamic computing platform samples multivariate distributions (e.g., multivariate Gaussian distributions) using a network of coupled analog unit cells controlled by a digital processor. The analog unit cells are capacitively, resistively, and / or inductively coupled to each other. Each analog unit cell contains an adjustable resistor, capacitor, inductor, current source, and / or voltage source. The digital processor sets initial values ​​for these components. These values, or input parameters, represent the multivariate distribution. The network of coupled analog unit cells is then evolved through a series of time steps until thermal equilibrium is reached. As the network evolves, the digital processor samples voltages at nodes in the network at each time step. These voltages represent samples of the multivariate distribution.

To detect anomalies in an excellent-accuracy and high-speed manner with a simplified configuration.SOLUTION: An anomaly detection device comprises an input unit, a reservoir unit, an output unit, and a determination unit. The input unit outputs a plurality of intermediary signals in accordance with a time-series input signal detected by observing an observation target device. The reservoir unit acquires the plurality of intermediary signals, and outputs a plurality of output signals each having a waveform having reproducibility in respect to a waveform of the input signal. The output unit generates a plurality of multiplication signals by multiplying output weights preset with respect to each of the plurality of output signals, and generates an integral signal obtained by time integration through adding up the plurality of multiplication signals. The determination unit determines whether the observation target device is normal or abnormal based on a result of comparison between the integral signal and a preset threshold, and outputs a determination signal representing a determination result. The output weights represent a positive prescribed value or a negative prescribed value, and are respectively set for the plurality of output signals.SELECTED DRAWING: Figure 2

A motor selection device (10) comprising: a speed calculation unit (16) configured to calculate a motor selection speed from a speed waveform of a motor configured to drive a specific driven object, taking into account iron losses generated in a target motor serving as an object to be selected, the speed waveform being obtained when the driven object is made to perform a prescribed operation, a storage unit (22) configured to store a motor characteristic associated with a speed of the target motor serving as the object to be selected, and a determination unit (24) configured to determine whether or not the prescribed operation is possible by the target motor, wherein the motor characteristic is used at the motor selection speed.

A spiking neuron circuit system 100 includes: a charging circuit 10 that, when an input voltage is applied, starts charging of a capacitor 12 by an output current I of a field effect transistor 11; a pulse generation circuit 20 that generates and outputs a pulse signal when a charging voltage of the capacitor 12 reaches a first threshold value; and a control circuit 50 that controls the output current I of the field effect transistor 11 by controlling a bulk voltage and / or a gate voltage of the field effect transistor 11.

To provide an information storage system which simulates a neural network on a silicon chip without using a bit.SOLUTION: A neural network has: a plurality of islands periodically disposed in a first axis direction and a second axis direction on a surface of a semiconductor device; a first link and a second link disposed between two islands adjacent to each other in the first direction and the second direction among the plurality of islands; and a first word line in a third axis direction; and a second word line in a fourth axis direction. Each of the plurality of islands has a diffusion layer formed on the surface of the semiconductor device. The first link is a first selection gate for bridging the two islands adjacent to each other in the first direction among the plurality of islands. The second link is a second selection gate for bridging the two islands adjacent to each other in the second direction among the plurality of islands. The first selection gate and the second selection gate have respective selection gate contacts. The selection gate contact is selected by the first word line and the second word line.SELECTED DRAWING: Figure 7

The standard for calculating memory capacity in modern computing is the bit, and the number of transistors (elements) that make up a node, i.e., the number of bits, is also the unit of modern information communication volume. In contrast, the human brain is made up of neural circuits, and human memory capacity is not based on the number of neural circuits (number of nodes). nerves Circuit complexity far exceeds bit capacity, and modern AI that attempts to replicate the human brain through bit-based computing is inherently wasteful because it handles information in a fundamentally different way. Moreover, bit-based computing is always at the limit of integration. The present invention provides a bit-independent information storage system using a three-dimensional silicon circuit network. [Solution] By switching the electrical connections of non-volatile memory cells distributed in a three-dimensional array, Reproducing the information processing mechanism of the human brain.

Ferroelectric diodes made of materials such as aluminum scandium nitride (AiScN) or hafnium zirconium oxide (HfZrO2) can be formed on top of semiconductor structures such as COMOS wafers to create storage memory cells, search ternary content addressable memory (TCAM) cells, and / or neural circuits. The diodes are non-volatile and field programmable by pulsing to analog states depending on the number of pulses, with high on / off and self-rectifying ratios. Cells can be formed, for example, with two diodes of opposite polarity or without transistors to form, for example, a 0T-2R structure.

Numerous embodiments are disclosed for a programmable output block for use with a VMM array in an artificial neural network. In one embodiment, the gain of the output block can be configured by a configuration signal. In another embodiment, the resolution of the ADC in the output block can be configured by a configuration signal.

To provide a memory device having a high retention property where weights are retained for inference calculation, and an operation method of the same.SOLUTION: A universal memory cell 400 of a universal memory device includes a write transistor 410 and a read transistor 420 coupled to the write transistor 410. The write transistor has a gate terminal 412, a first terminal 414, and a second terminal 416. The read transistor includes a gate terminal 422, a charge trap layer 423, a first terminal 424, and a second terminal 426. The charge trap layer is configured to be unalterable when a first write voltage is applied at the first terminal of the write transistor, and be alterable when a second write voltage is applied at the first terminal of the write transistor to change a threshold voltage of the read transistor. The second write voltage is greater than the first write voltage.SELECTED DRAWING: Figure 4

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

A device comprising an array of resistive processing unit (RPU) cells, a first plurality of control lines extending across the array of RPU cells in a first direction, and a second plurality of control lines extending across the array of RPU cells in a second direction. A peripheral circuit comprising a readout circuit is coupled to the first and second control lines. A control system generates control signals to control the peripheral circuit to perform a first operation on the array of RPU cells and to perform a second operation on the array of RPU cells. The control signals include a first configuration control signal for configuring the readout circuit to have a first hardware configuration when the first operation is performed on the array of RPU cells; and a second configuration control signal for configuring the readout circuit to have a second hardware configuration different from the first hardware configuration when the second operation is performed on the array of RPU cells.