52results about "Computing operations for addition/subtraction" patented technology

The invention provides a sampling compensation circuit, a voltage sampling device and radio frequency power supply equipment, and relates to the technical field of power electronics, the sampling compensation circuit is used for compensating a sampling voltage value obtained by a voltage sampling circuit, the voltage sampling circuit at least comprises a sampling diode, the sampling diode is used for rectifying a to-be-detected alternating current signal, and the to-be-detected alternating current signal is sent to the sampling compensation circuit. Therefore, a sampling voltage signal is obtained. The sampling compensation circuit comprises a voltage drop acquisition unit and a sampling compensation unit. The first input end and the second input end of the voltage drop obtaining unit are used for being connected with the first end and the second end of the sampling diode respectively, and the voltage drop obtaining unit is used for obtaining a voltage difference signal. The sampling compensation unit is used for acquiring a sampling voltage signal output by the second end of the sampling diode and a voltage difference signal output by the first output end of the voltage drop acquisition unit, and compensating the sampling voltage signal according to the voltage difference signal to obtain a corrected sampling signal. According to the invention, a more accurate sampling voltage value can be obtained.

A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.

A current-integrating summing circuit is provided, and may include a first capacitor and a second capacitor to integrate an input current over time, a first pair of transistors to receive a differential pair of input signals, a second pair of transistors to receive a common-mode voltage, a third pair of transistors and a fourth pair of transistors respectively configured in a cascode formation relative to the first pair of transistors and the second pair of transistors, and a pair of complementary clocks to activate the third pair of transistors to enable charging of the first and second capacitors according to the differential pair of input signals during an integration phase, wherein the pair of complementary clocks are to activate the fourth pair of transistors to enable discharging of the first and second capacitors during a reset phase.

The invention relates to the technical field of semiconductors, and provides an arithmetic unit and method based on a ferroelectric field effect transistor and a storage and calculation switch array. The arithmetic unit comprises a 1F1R unit, a shared capacitor, a bit line and a word line; each column of 1F1R units comprises a plurality of 1F1R units which are arranged in parallel; each 1F1R unit comprises a first resistor and a ferroelectric field effect transistor, the first resistor comprises a first end and a second end, and the ferroelectric field effect transistor comprises a grid electrode, a source electrode and a drain electrode; the grid electrode of each ferroelectric field effect transistor is connected with the word line, the source electrode is connected with the second end of the first resistor, and the drain electrode is connected with the bit line; the shared capacitor comprises a first end and a second end, the first end of the first resistor of each column of 1F1R units is connected with the first end of the shared capacitor, and the second end of the shared capacitor is grounded. According to the scheme, compact and low-power-consumption memory operation can be realized, the energy consumption of the whole array is reduced on the basis of ensuring the energy efficiency, and meanwhile, a large-area coding and decoding circuit is avoided due to the single-bit data bit width.

To detect anomalies in an excellent-accuracy and high-speed manner with a simplified configuration.SOLUTION: An anomaly detection device comprises an input unit, a reservoir unit, an output unit, and a determination unit. The input unit outputs a plurality of intermediary signals in accordance with a time-series input signal detected by observing an observation target device. The reservoir unit acquires the plurality of intermediary signals, and outputs a plurality of output signals each having a waveform having reproducibility in respect to a waveform of the input signal. The output unit generates a plurality of multiplication signals by multiplying output weights preset with respect to each of the plurality of output signals, and generates an integral signal obtained by time integration through adding up the plurality of multiplication signals. The determination unit determines whether the observation target device is normal or abnormal based on a result of comparison between the integral signal and a preset threshold, and outputs a determination signal representing a determination result. The output weights represent a positive prescribed value or a negative prescribed value, and are respectively set for the plurality of output signals.SELECTED DRAWING: Figure 2

The invention relates to the technical field of computers, and discloses a computer memory data processing system comprising a calculation task compiling module used for determining physical setting parameters according to a calculation task and generating a preset target evolution path; the physical calculation execution module is used for performing state evolution according to the physical setting parameters; the dynamic feedback control module is used for monitoring the actual evolution state and generating a calibration signal according to the deviation between the actual evolution state and a preset target evolution path so as to dynamically adjust driving; and the result decoding module is used for converting the steady-state physical quantity into a calculation result after the system reaches a stable equilibrium state. By constructing closed-loop feedback control, evolution deviation generated by non-ideal factors of a physical system is corrected in real time, it can be effectively guaranteed that actual state evolution of physical calculation accurately tends to a preset ideal path, and therefore the accuracy and reliability of data processing through the physical process are remarkably improved.

A semiconductor device capable of performing product-sum operations with reduced power consumption is provided. [Solution] A semiconductor device has first and second cells, a first circuit, and first to third wirings. Each of the first and second cells has a capacitance, and a first terminal of each capacitance is electrically connected to a third wiring. Each of the first and second cells has a function of flowing a current corresponding to a potential held at a second terminal of the capacitance to the first and second wirings. The first circuit is electrically connected to the first and second wirings, and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wire changes, the amount of current in the first wire changes from I1 to I3, and the amount of current in the second wire changes from I2 to I4, the first circuit generates a current of I1-I2-I3+I4. Note that the change in the third wire is achieved by first inputting a reference potential to the third wire, and then inputting a potential corresponding to internal data or information obtained by a sensor.

A number of examples are described for providing an artificial neural network system with analog and digital arrays. In certain examples, the analog and digital arrays are coupled to shared bit lines. In other examples, the analog and digital arrays are coupled to separate bit lines.

To provide a semiconductor device with a novel structure.SOLUTION: A calculation block 21_O includes a storage circuit part 30 that holds a plurality of pieces of first weight data, a calculation circuit 45, a first switch circuit (switch circuit 42), and a second switch circuit (switch circuit 44). The first switch circuit applies any of the pieces of first weight data to a first wire WOL. The second switch circuit applies any of the applied first weight data or second weight data applied to a second wire WEL to a first calculation circuit (calculation circuit 45). A calculation block 21_E includes a storage circuit part 30 that holds a plurality of pieces of second weight data, a second calculation circuit (calculation circuit 45), a third switch circuit (switch circuit 42), and a fourth switch circuit (switch circuit 44). The third switch circuit applies any of the pieces of second weight data to the second wire WEL. The fourth switch circuit applies any of the applied first weight data or the second weight data applied to the second wire to the second calculation circuit.SELECTED DRAWING: Figure 1

The invention provides a sampling compensation circuit, a voltage sampling device and radio frequency power supply equipment, the sampling compensation circuit is used for compensating a sampling voltage value obtained by a voltage sampling circuit, the voltage sampling circuit comprises a sampling input end, a sampling output end and a sampling diode, the sampling diode is used for rectifying a to-be-detected alternating current signal, and the sampling output end is used for outputting the rectified alternating current signal; therefore, a sampling voltage signal is obtained. The sampling compensation circuit comprises a test alternating current source, a test diode, a voltage drop acquisition unit and a sampling compensation unit. The test diode is used for rectifying a test AC signal, and the test diode and the sampling diode have at least partially the same manufacturing parameters. The voltage drop obtaining unit is used for obtaining a voltage difference value signal reflecting the voltage difference value of the two ends of the test diode and outputting the voltage difference value signal through the first output end. The sampling compensation unit is used for compensating the sampling voltage signal at least according to the voltage difference signal so as to obtain a corrected sampling signal. According to the invention, a more accurate sampling voltage value can be obtained.

Various mechanisms for performing sequential vector-matrix multiplication may include sequentially performing a first vector-matrix multiplication for each bit order of values ​​in an input vector. The first vector-matrix multiplication operation for each bit order may generate an analog output. Each analog output generated by the vector-matrix multiplication may be converted to one or more digital bit values, and the one or more digital bit values ​​may be sent to a second vector-matrix multiplication operation.

An electricity metering circuit for a matrix operation circuit, having a circuit input for an electrical input current that is an output current of the matrix operation circuit. The electricity metering circuit is set up to provide a ground potential at the circuit input, to integrate the input current at the circuit input over time, to store a storage charge that is increased up to a predetermined maximum storage charge in accordance with a proportionality constant, proportionally to the integrated input current, to quantify the integrated input current in a charge unit, the charge unit corresponding to the maximum storage charge taking into account the proportionality constant, and to determine the integrated input current rounded down to the nearest integer charge unit as a count sum.

The invention provides a memristor-based fixed-point matrix FFT (Fast Fourier Transform) calculation method, which belongs to the technical field of signal processing and image processing, and comprises the following steps of: firstly, constructing a non-linear voltage controlled memristor model, simulating a state conversion behavior in logic operation through a dynamic regulation mechanism, and realizing the function of a basic logic gate; according to the method, an FFT algorithm based on matrix block optimization is designed, FFT calculation is decomposed into small-scale matrix operation units, calculation efficiency is optimized in combination with a Kronecker product and an arrangement matrix, FFT operation with higher point number is expanded in a recursion mode, meanwhile, a full adder and a multiplier are designed based on a memristor, efficient fixed-point number operation is achieved, and finally, the FFT calculation efficiency is improved. The method is applied to image FFT processing, and a processing result is obtained. The scheme of the invention has higher calculation efficiency and lower energy consumption while ensuring the calculation precision, can be widely applied to the fields of image processing, signal analysis, scientific calculation and the like, and has important practical value and application prospect.

This invention provides an arithmetic circuit that calculates the product of weight coefficients, which are analog or multi-level data, and data. [Solution] In the arithmetic circuit MAC2, transistors F2 and F2m are operated in the subthreshold region, and a wiring VE is provided that flows a current corresponding to the product of the weight coefficient and the data between the source and drain of the transistors.

The invention belongs to the technical field of chaotic circuits, and discloses a sine nonlinear characteristic-based third-order circuit system, which comprises a sine nonlinear function circuit and a third-order linear differential equation circuit, the input end of the sine nonlinear function circuit is connected with the x output end of the third-order linear differential equation circuit, and the output end of the sine nonlinear function circuit is connected with the x output end of the third-order linear differential equation circuit. The output end is connected with one input end of the x integrator of the third-order linear differential equation circuit; the sine nonlinear function circuit is composed of a first operational amplifier A1, resistors R1 to R16 and diodes D1 to D6, and the output and the input of the sine nonlinear function circuit are in a sine nonlinear function relationship; the third-order linear differential equation circuit forms three anti-phase addition integrators by three anti-phase operational amplifiers, three capacitors and seven resistors, and the sine nonlinear function circuit provides nonlinear signals to generate three Chua's chaotic signal outputs of the sine nonlinear third-order Chua's circuit; according to the invention, various chaotic line systems and chaotic secret communication systems can be formed.

A novel semiconductor device is provided. An analog signal is converted into a digital signal using a comparison portion comparing two current values, a control portion, and a current output digital-analog conversion portion. The control portion has a function of generating a sign bit showing a magnitude relation between the two current values, a function of converting a difference between the two current values into a digital signal by successive approximation, and a function of outputting the sign bit and the digital signal.

To provide a processing device, and an electronic device having the same.SOLUTION: A processing device with improved computational reliability is provided, the processing device comprising a variable resistor layer including active variable resistors, an active layer including switches configured to control voltage applied across or current flowing through the active variable resistors, and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches.SELECTED DRAWING: Figure 9A

The invention relates to an adjustable square wave signal synthesis method and a digital frequency synthesizer, and the method comprises the steps: executing repeated accumulation operation through a phase accumulator according to an initial phase PCW and a target frequency control word FCW, and generating a continuous carry signal CARRY; the integration module performs integration operation on a target frequency control word FCW according to a continuous carry signal CARRY and outputs an integration voltage Vinteg, the comparator compares the integration voltage Vinteg with a preset reference voltage Vref to obtain a comparison result signal CMPOUT, and the trigger performs signal flipping according to the comparison result signal CMPOUT to generate a square wave signal Dout; according to the invention, by utilizing the periodicity of the carry signal and the current source in a correlation proportion with the target frequency control word FCW, the balance between the total charging amount and the total discharging amount of the capacitor in the whole period is realized, and the stability and the reliability under the actual circuit application are ensured.

Various embodiments include devices and methods for a multi-bit multiply-accumulate (MAC). Some embodiments may include an analog adder having a first adder capacitor. The first adder capacitor may add the multiple single-bit MAC outputs by receiving multiple single-bit MAC outputs from multiple single-bit MACs and storing the multiple single-bit MAC outputs. In some embodiments, the analog adder may output a multi-bit MAC output based on the addition of the multiple stored single-bit MAC outputs.

The invention discloses a universal programmable piecewise linear function analog circuit, which relates to the technical field of electronic information engineering and comprises a judgment module, a selection module and an addition module. The judgment module comprises a plurality of judgment branches, each judgment branch comprises a comparator and a threshold voltage, the in-phase input end of the comparator is externally connected to an original input signal, and the inverted input end of the comparator is grounded through the threshold voltage; the selection module comprises controllable bias voltage and analog switches, the number of the analog switches is equal to that of the judgment branches, the control ends of the analog switches are connected to the output ends of the comparators in a one-to-one correspondence mode, and the input ends of all the analog switches are grounded through the controllable bias voltage; the addition module comprises an anti-phase summator and an input resistor, the input end of the anti-phase summator is connected to the output ends of all the analog switches, and meanwhile, the anti-phase summator is externally connected to an original input signal through the input resistor; and the output end of the anti-phase adder is used as circuit output. The method simulates a piecewise linear function, and has the characteristics of universality, online programming and easy expansion.

Systems, devices, circuits, and methods of operating said systems, devices, and circuits are disclosed. In one aspect, a system includes an input buffer circuit storing a set of data values for a convolution operation and a plurality of multiply-accumulate (MAC) circuits. A first MAC circuit of the plurality of MAC circuits can retrieve the set of data values for the convolution operation and generate a first output by applying a first weight value stored at the first MAC circuit to a first data value of the set of data values. The first MAC circuit can provide the first data value to a second MAC circuit of the plurality of MAC circuits. The first MAC circuit can generate a plurality of second outputs by applying a second weight value and a third weight value stored at the first MAC circuit to a second data value of the set of data values.

To provide a novel semiconductor device.SOLUTION: A semiconductor device has a function of performing a product-sum operation between a weight value set by an analog current signal and an input value, in which the analog current signal is output by a digital-to-analog conversion circuit having a circuit in which a plurality of variable resistance elements and switches electrically connected in series are electrically connected in parallel, and a ferroelectric element is used as the variable resistance element. The ferroelectric element has a ferroelectric material containing an oxide containing either hafnium or zirconium, or both.SELECTED DRAWING: Figure 2

The application discloses a reconfigurable fractional order calculation system with high-efficiency FPGA resource utilization. After input data is normalized and converted into single-precision floating-point numbers by a data preprocessing module, a control module receives binomial coefficient theoretical calculation parameters and binomial coefficient segmented linear fitting parameters set by a user, controls a binomial coefficient fitting module to calculate binomial coefficients and perform segmented linear fitting, configures configuration parameters required by a fixed window length calculation module and a segmented linear function calculation module according to a fitting result, and starts the fixed window length calculation module and the segmented linear function calculation module to perform fractional order calculation after the configuration is completed, so that a fractional order calculation result of the input data is obtained. The application is based on a fixed window (FWL) with error compensation and a multi-segment linear function (PWL), realizes a real-time reconfigurable fractional order calculation system on an FPGA platform, improves the FPGA resource utilization efficiency, and guarantees the precision and efficiency of the fractional order calculation.

The invention relates to a method with a computing device which comprises a circuit, wherein the circuit has an ohmic resistor (3), wherein the computing device comprises an analogue-digital converter (24) which can convert an output signal, generated by the circuit, into a digital value, the method comprising the following steps: the smallest possible and the largest possible output signal of the circuit are determined, the analogue-digital converter is adapted to the smallest possible and largest possible output value. The invention also relates to a computing device having a circuit which has an ohmic resistor (3), wherein the computing device comprises an analogue-digital converter (24) which can convert an output signal, generated by the circuit, into a digital value, wherein the analogue-digital converter (24) is adapted to the smallest possible and largest possible output signal of the circuit or can be adapted to the smallest possible and largest possible output signal of the circuit.

In a method for forming a non-volatile tunable capacitor device, a first electrode layer is formed facing distally from a second electrode layer, the first electrode layer configured to make a first electrical connection and the second electrode layer configured to make a second electrical connection. A dielectric layer is positioned between the first electrode layer and an adjacent second electrode layer. A phase change material (PCM) layer is positioned between the first electrode layer and the second electrode layer adjacent the dielectric layer. An activation component is provided for heating the PCM layer to change a phase of the PCM layer. The activation component may include a heating element or an electrical probe in direct contact with the PCM layer and is configured to apply heat to the PCM layer when activated. The phase of the PCM layer is changeable between an amorphous phase and a crystalline phase.

The invention belongs to the field of chaotic circuits, and particularly discloses a chaotic system based on a double-charge-control memristor model, which comprises a driving force module, an integral summation reverse module and a multiplication module, the integral summation reverse module comprises a first summation circuit, a first integral circuit, a second summation circuit, a second integral circuit, a first reverse circuit and a third integral circuit, the multiplication module comprises multipliers A1-A4 and a third integral circuit, and the multiplier A3 and the multiplier A4 form a charge-controlled memristor model and are used for enhancing the nonlinearity and noise immunity of the chaotic system. According to the invention, the charge-controlled memristor model is introduced into a Van der Pol-Duffing chaotic system structure, a chaotic system circuit with complex dynamic characteristics is successfully constructed, and the circuit can be suitable for a weak signal detection scene with a low signal-to-noise ratio and high precision.

We provide a novel semiconductor device. [Solution] A comparison unit that compares two current values, a control unit, and a current output type digital-analyzer. The log conversion unit converts the analog signal to a digital signal using two power units. It has a function to generate a sign bit that indicates the relative magnitude of the current values, and the difference between two current values ​​through successive comparison. It has the function of converting minutes into a digital signal and the function of outputting a sign bit and a digital signal. do.

The disclosure provides systems and methods for performing analog computing. In one arrangement, an input data stream comprises a plurality of input data units. An analog computational operation is performed on the input data stream to generate an output data stream comprising output data units. Each output data unit comprises a sequence of computed values corresponding to a sequence of symbols of an input data unit corresponding to the output data unit. An output value corresponding to each output data unit is generated by applying encoding functions to the computed values to generate respective encoding waveforms that decay. The output value is generated by sampling a combination of the encoding waveforms at a sampling time. Positions of the encoding waveforms in the sequence represent significances of the symbols of the corresponding input data unit.