8results about "Computing operations for addition/subtraction" patented technology

The disclosure provides systems and methods for performing analog computing. In one arrangement, an input data stream comprises a plurality of input data units. An analog computational operation is performed on the input data stream to generate an output data stream comprising output data units. Each output data unit comprises a sequence of computed values corresponding to a sequence of symbols of an input data unit corresponding to the output data unit. An output value corresponding to each output data unit is generated by applying encoding functions to the computed values to generate respective encoding waveforms that decay. The output value is generated by sampling a combination of the encoding waveforms at a sampling time. Positions of the encoding waveforms in the sequence represent significances of the symbols of the corresponding input data unit.

We provide electronic devices for use in artificial neuronal networks. [Solution] The electronic device 100, which is an artificial neural network, has an artificial neural array (ANA) 111, a row decoder 112, a column decoder 113, an input circuit 114, an output circuit 115, an analog signal processing circuit 116, and a memory 130. The ANA 111 has multiple circuits 10, 11, multiple wires WW, WB, DL, RB, and one wire RD. The circuits 10 are arranged in an n-row m-column array, and the circuits 11 are arranged in an n-row 1-column array. The wires WW are electrically connected to the row decoder, and the wires WB are electrically connected to the column decoder. The row decoder and column decoder are peripheral circuits for writing weights or thresholds to the circuit 10. The input circuit writes data DIN to the ANA 111, and the output circuit processes the analog signal input via wires RB and RD to generate data DOUT.

The application discloses a mixed-precision dequantization system and method for in-memory computing, and belongs to the field of integrated circuits and artificial intelligence hardware. The system comprises a digital domain pre-alignment module, an analog in-memory computing core and a general dequantization DQ-SIMD unit. The pre-alignment module completes floating-point activation processing and generates an activation value compensation term. The analog in-memory computing core completes multiplication and accumulation and eliminates physical offset errors based on a 1T1R single-terminal array. The dequantization unit realizes fixed-point to floating-point conversion and asymmetric quantization inverse transformation through a three-stage pipeline. The application proposes a single-terminal storage scheme of non-negative shift mapping in view of the core contradiction between mixed-precision computing requirements and the non-negativity of device conductance when deploying a large language model inference on a 1T1R structure RRAM array. The single-terminal storage scheme is matched with a double-error elimination mechanism of software and hardware cooperation to realize single-terminal storage of signed weights by superimposing a fixed offset in the analog domain and to eliminate physical errors introduced by the offset in real time through a pipeline circuit in the digital domain.

To provide semiconductor and electronic devices that can perform calculations with low power consumption. [Solution] The arithmetic circuit is a semiconductor device having an array unit ALP and a circuit AFP, wherein the array unit ALP has circuits MP[1,j] to MP[m,j]. The circuit AFP also has a circuit ACTF[j], which has a capacitor CRE, a circuit AC, terminal T1, and terminal T2. Each of the circuits MP[1,j] to MP[m,j] is electrically connected to wiring XLS[1] to wiring XLS[m]. Wiring OL[j] is electrically connected to terminal T1, terminal T1 is electrically connected to the first terminal of capacitor CRE, wiring OLB[j] is electrically connected to terminal T2, terminal T2 is electrically connected to the second terminal of capacitor CRE. The voltage (charge) stored in capacitor CRE is input to circuit AC, and the amount of voltage (charge) stored in capacitor CRE is sensed.

Provided is a semiconductor device capable of calculating an echo state network. The semiconductor device has first to fifth circuits and first to third cells. The first circuit has a function of transmitting a first value to the first cell and a function of transmitting a second value to the second cell. The second circuit has a function of transmitting a third value to the third cell. The third circuit has a function of transmitting a fourth value to the first cell. The first cell has a function of adding the product of the first value and the fourth value, as a current, to a first current flowing through an input terminal of the fourth circuit. The fourth circuit has a function of generating a fifth value corresponding to the first current, and a function of transmitting the fifth value to the second cell and the third cell. The second cell has a function of adding the product of the second value and the fifth value, as a current, to the first current flowing through an input terminal of the fifth circuit. The third cell has a function of adding the product of the third value and the fifth value, as a current, to a second current flowing through the input terminal of the fifth circuit.