75results about "Computing operations for addition/subtraction" patented technology

The present invention provides a novel semiconductor device. The present invention uses a comparison unit for comparing two current values, a control unit, and a current output type digital-analog conversion unit to convert an analog signal into a digital signal. The control unit has the function of generating a sign bit indicating the magnitude relation between the two current values, the function of converting, by successive approximation, the difference between the two current values into the digital signal, and the function of outputting the sign bit and the digital signal.

The invention provides a sampling compensation circuit, a voltage sampling device and radio frequency power supply equipment, and relates to the technical field of power electronics, the sampling compensation circuit is used for compensating a sampling voltage value obtained by a voltage sampling circuit, the voltage sampling circuit at least comprises a sampling diode, the sampling diode is used for rectifying a to-be-detected alternating current signal, and the to-be-detected alternating current signal is sent to the sampling compensation circuit. Therefore, a sampling voltage signal is obtained. The sampling compensation circuit comprises a voltage drop acquisition unit and a sampling compensation unit. The first input end and the second input end of the voltage drop obtaining unit are used for being connected with the first end and the second end of the sampling diode respectively, and the voltage drop obtaining unit is used for obtaining a voltage difference signal. The sampling compensation unit is used for acquiring a sampling voltage signal output by the second end of the sampling diode and a voltage difference signal output by the first output end of the voltage drop acquisition unit, and compensating the sampling voltage signal according to the voltage difference signal to obtain a corrected sampling signal. According to the invention, a more accurate sampling voltage value can be obtained.

To provide a semiconductor device having a novel configuration.SOLUTION: A first storage circuit unit includes a first storage circuit that holds a plurality of pieces of first weight data. A second storage circuit unit includes a second storage circuit that holds a plurality of pieces of second weight data. A first arithmetic circuit unit includes a first arithmetic circuit, a first switching circuit, and a third switching circuit. A second arithmetic circuit unit includes a second arithmetic circuit, a second switching circuit, and a fourth switching circuit. The first switching circuit includes a function of providing any one of the plurality of pieces of first weight data to first wiring. The second switching circuit includes a function of providing any one of the plurality of pieces of second weight data to second wiring. The third switching circuit includes a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the first arithmetic circuit. The fourth switching circuit includes a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the second arithmetic circuit.SELECTED DRAWING: Figure 1

A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.

A current-integrating summing circuit is provided, and may include a first capacitor and a second capacitor to integrate an input current over time, a first pair of transistors to receive a differential pair of input signals, a second pair of transistors to receive a common-mode voltage, a third pair of transistors and a fourth pair of transistors respectively configured in a cascode formation relative to the first pair of transistors and the second pair of transistors, and a pair of complementary clocks to activate the third pair of transistors to enable charging of the first and second capacitors according to the differential pair of input signals during an integration phase, wherein the pair of complementary clocks are to activate the fourth pair of transistors to enable discharging of the first and second capacitors during a reset phase.

The invention relates to the technical field of semiconductors, and provides an arithmetic unit and method based on a ferroelectric field effect transistor and a storage and calculation switch array. The arithmetic unit comprises a 1F1R unit, a shared capacitor, a bit line and a word line; each column of 1F1R units comprises a plurality of 1F1R units which are arranged in parallel; each 1F1R unit comprises a first resistor and a ferroelectric field effect transistor, the first resistor comprises a first end and a second end, and the ferroelectric field effect transistor comprises a grid electrode, a source electrode and a drain electrode; the grid electrode of each ferroelectric field effect transistor is connected with the word line, the source electrode is connected with the second end of the first resistor, and the drain electrode is connected with the bit line; the shared capacitor comprises a first end and a second end, the first end of the first resistor of each column of 1F1R units is connected with the first end of the shared capacitor, and the second end of the shared capacitor is grounded. According to the scheme, compact and low-power-consumption memory operation can be realized, the energy consumption of the whole array is reduced on the basis of ensuring the energy efficiency, and meanwhile, a large-area coding and decoding circuit is avoided due to the single-bit data bit width.

To provide a system and method, which greatly increase speed, resolution, and power efficiency as compared to digital spatial convolutions for optically processing images.SOLUTION: A photonic neural network system 10 for convolving and adding frames of data includes a first sensor display device 14 and a second sensor display device 26. Each sensor display device comprises an array of transmit-receive modules. Each transmit-receive module comprises a light sensor element, a light transmitter element, and a memory bank. A radial modulator device 20 is positioned where transmission of light fields including frames of data are Fourier transformed. Filters implemented by modulator elements of the radial modulator device 20 convolve fields of light including the frames of data, which are then sensed on a pixel-by-pixel basis by the light sensor elements, which accumulate charges, thus sum pixel values of sequential convolved frames of data.SELECTED DRAWING: Figure 1

To detect anomalies in an excellent-accuracy and high-speed manner with a simplified configuration.SOLUTION: An anomaly detection device comprises an input unit, a reservoir unit, an output unit, and a determination unit. The input unit outputs a plurality of intermediary signals in accordance with a time-series input signal detected by observing an observation target device. The reservoir unit acquires the plurality of intermediary signals, and outputs a plurality of output signals each having a waveform having reproducibility in respect to a waveform of the input signal. The output unit generates a plurality of multiplication signals by multiplying output weights preset with respect to each of the plurality of output signals, and generates an integral signal obtained by time integration through adding up the plurality of multiplication signals. The determination unit determines whether the observation target device is normal or abnormal based on a result of comparison between the integral signal and a preset threshold, and outputs a determination signal representing a determination result. The output weights represent a positive prescribed value or a negative prescribed value, and are respectively set for the plurality of output signals.SELECTED DRAWING: Figure 2

The invention relates to the technical field of computers, and discloses a computer memory data processing system comprising a calculation task compiling module used for determining physical setting parameters according to a calculation task and generating a preset target evolution path; the physical calculation execution module is used for performing state evolution according to the physical setting parameters; the dynamic feedback control module is used for monitoring the actual evolution state and generating a calibration signal according to the deviation between the actual evolution state and a preset target evolution path so as to dynamically adjust driving; and the result decoding module is used for converting the steady-state physical quantity into a calculation result after the system reaches a stable equilibrium state. By constructing closed-loop feedback control, evolution deviation generated by non-ideal factors of a physical system is corrected in real time, it can be effectively guaranteed that actual state evolution of physical calculation accurately tends to a preset ideal path, and therefore the accuracy and reliability of data processing through the physical process are remarkably improved.

A semiconductor device capable of performing product-sum operations with reduced power consumption is provided. [Solution] A semiconductor device has first and second cells, a first circuit, and first to third wirings. Each of the first and second cells has a capacitance, and a first terminal of each capacitance is electrically connected to a third wiring. Each of the first and second cells has a function of flowing a current corresponding to a potential held at a second terminal of the capacitance to the first and second wirings. The first circuit is electrically connected to the first and second wirings, and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wire changes, the amount of current in the first wire changes from I1 to I3, and the amount of current in the second wire changes from I2 to I4, the first circuit generates a current of I1-I2-I3+I4. Note that the change in the third wire is achieved by first inputting a reference potential to the third wire, and then inputting a potential corresponding to internal data or information obtained by a sensor.

Provided is a product sum calculator which consumes little energy and has high calculation accuracy. A product sum arithmetic unit (1) is configured from: a resistive digital-to-analog conversion unit (11) that is provided with a plurality of RDACs and that converts digital values of each element of an input vector into analog voltages and outputs the analog voltages; a capacitive digital-to-analog conversion unit (12), which is provided with a plurality of CDACs, to which the analog voltage output from the resistive digital-to-analog conversion unit (11) is inputted, and which sets a capacitance ratio corresponding to the digital value of each element of the matrix between input and output terminals and between the output terminal and ground; a successive approximation-type analog-to-digital conversion unit (13) provided with a plurality of successive approximation-type ADCs for converting the voltage of a node commonly connected to each output terminal of the capacitive digital-to-analog conversion unit (12) into a digital value and outputting the digital value; and a consumption current control unit (14) for controlling the consumption current of the resistive digital-to-analog conversion unit (11), the output from the successive comparison analog-to-digital conversion unit (13) being an output vector.

A number of examples are described for providing an artificial neural network system with analog and digital arrays. In certain examples, the analog and digital arrays are coupled to shared bit lines. In other examples, the analog and digital arrays are coupled to separate bit lines.

To provide a semiconductor device with a novel structure.SOLUTION: A calculation block 21_O includes a storage circuit part 30 that holds a plurality of pieces of first weight data, a calculation circuit 45, a first switch circuit (switch circuit 42), and a second switch circuit (switch circuit 44). The first switch circuit applies any of the pieces of first weight data to a first wire WOL. The second switch circuit applies any of the applied first weight data or second weight data applied to a second wire WEL to a first calculation circuit (calculation circuit 45). A calculation block 21_E includes a storage circuit part 30 that holds a plurality of pieces of second weight data, a second calculation circuit (calculation circuit 45), a third switch circuit (switch circuit 42), and a fourth switch circuit (switch circuit 44). The third switch circuit applies any of the pieces of second weight data to the second wire WEL. The fourth switch circuit applies any of the applied first weight data or the second weight data applied to the second wire to the second calculation circuit.SELECTED DRAWING: Figure 1

The present invention relates to the field of artificial intelligence technology, and discloses a working method for simulating a computer chip. The method includes: receiving training data and initial values of model parameters; the initial values of the model parameters are used to initialize the parameters of the storage arithmetic unit; according to the training data, the regulator iteratively updates the parameters of the storage arithmetic unit, and when the iteration completion condition is satisfied, a first arithmetic model corresponding to the storage arithmetic unit is generated; inputting the model input value corresponding to the first target scenario into the analog computer chip, and outputting the model output value corresponding to the first target scenario through the first arithmetic model in the analog computer chip. The above solution can autonomously generate an arithmetic model inside the analog computer chip and can perform self-learning updates, thereby increasing the application scope of the working method and improving the accuracy of the artificial intelligence chip applying the working method.

The invention provides a sampling compensation circuit, a voltage sampling device and radio frequency power supply equipment, the sampling compensation circuit is used for compensating a sampling voltage value obtained by a voltage sampling circuit, the voltage sampling circuit comprises a sampling input end, a sampling output end and a sampling diode, the sampling diode is used for rectifying a to-be-detected alternating current signal, and the sampling output end is used for outputting the rectified alternating current signal; therefore, a sampling voltage signal is obtained. The sampling compensation circuit comprises a test alternating current source, a test diode, a voltage drop acquisition unit and a sampling compensation unit. The test diode is used for rectifying a test AC signal, and the test diode and the sampling diode have at least partially the same manufacturing parameters. The voltage drop obtaining unit is used for obtaining a voltage difference value signal reflecting the voltage difference value of the two ends of the test diode and outputting the voltage difference value signal through the first output end. The sampling compensation unit is used for compensating the sampling voltage signal at least according to the voltage difference signal so as to obtain a corrected sampling signal. According to the invention, a more accurate sampling voltage value can be obtained.

Various mechanisms for performing sequential vector-matrix multiplication may include sequentially performing a first vector-matrix multiplication for each bit order of values ​​in an input vector. The first vector-matrix multiplication operation for each bit order may generate an analog output. Each analog output generated by the vector-matrix multiplication may be converted to one or more digital bit values, and the one or more digital bit values ​​may be sent to a second vector-matrix multiplication operation.

An electricity metering circuit for a matrix operation circuit, having a circuit input for an electrical input current that is an output current of the matrix operation circuit. The electricity metering circuit is set up to provide a ground potential at the circuit input, to integrate the input current at the circuit input over time, to store a storage charge that is increased up to a predetermined maximum storage charge in accordance with a proportionality constant, proportionally to the integrated input current, to quantify the integrated input current in a charge unit, the charge unit corresponding to the maximum storage charge taking into account the proportionality constant, and to determine the integrated input current rounded down to the nearest integer charge unit as a count sum.

The invention provides a memristor-based fixed-point matrix FFT (Fast Fourier Transform) calculation method, which belongs to the technical field of signal processing and image processing, and comprises the following steps of: firstly, constructing a non-linear voltage controlled memristor model, simulating a state conversion behavior in logic operation through a dynamic regulation mechanism, and realizing the function of a basic logic gate; according to the method, an FFT algorithm based on matrix block optimization is designed, FFT calculation is decomposed into small-scale matrix operation units, calculation efficiency is optimized in combination with a Kronecker product and an arrangement matrix, FFT operation with higher point number is expanded in a recursion mode, meanwhile, a full adder and a multiplier are designed based on a memristor, efficient fixed-point number operation is achieved, and finally, the FFT calculation efficiency is improved. The method is applied to image FFT processing, and a processing result is obtained. The scheme of the invention has higher calculation efficiency and lower energy consumption while ensuring the calculation precision, can be widely applied to the fields of image processing, signal analysis, scientific calculation and the like, and has important practical value and application prospect.

This invention provides an arithmetic circuit that calculates the product of weight coefficients, which are analog or multi-level data, and data. [Solution] In the arithmetic circuit MAC2, transistors F2 and F2m are operated in the subthreshold region, and a wiring VE is provided that flows a current corresponding to the product of the weight coefficient and the data between the source and drain of the transistors.

The invention belongs to the technical field of chaotic circuits, and discloses a sine nonlinear characteristic-based third-order circuit system, which comprises a sine nonlinear function circuit and a third-order linear differential equation circuit, the input end of the sine nonlinear function circuit is connected with the x output end of the third-order linear differential equation circuit, and the output end of the sine nonlinear function circuit is connected with the x output end of the third-order linear differential equation circuit. The output end is connected with one input end of the x integrator of the third-order linear differential equation circuit; the sine nonlinear function circuit is composed of a first operational amplifier A1, resistors R1 to R16 and diodes D1 to D6, and the output and the input of the sine nonlinear function circuit are in a sine nonlinear function relationship; the third-order linear differential equation circuit forms three anti-phase addition integrators by three anti-phase operational amplifiers, three capacitors and seven resistors, and the sine nonlinear function circuit provides nonlinear signals to generate three Chua's chaotic signal outputs of the sine nonlinear third-order Chua's circuit; according to the invention, various chaotic line systems and chaotic secret communication systems can be formed.

To provide a novel semiconductor device.SOLUTION: A semiconductor device has a function of performing a product-sum operation between a weight value set by an analog current signal and an input value, in which the analog current signal is output by a digital-to-analog conversion circuit having a circuit in which a plurality of variable resistance elements and switches electrically connected in series are electrically connected in parallel, and a ferroelectric element is used as the variable resistance element. The ferroelectric element has a ferroelectric material containing an oxide containing either hafnium or zirconium, or both.SELECTED DRAWING: Figure 2

The present invention relates to the field of artificial intelligence technology, and discloses a method for generating a model of a simulated computer chip. The method includes: obtaining a training data set; iteratively updating a neural network model according to the training data set until an iteration condition is met, so as to obtain target parameter values of various transfer functions in the neural network model; wherein, the neural network model includes n layers of computing nodes, and any computing node in each layer of computing nodes is connected to each node in the upper layer through different transfer functions; the target parameter values of the transfer functions between the computing nodes are used to correspondingly set the parameters of the computing units between the adders in the model of the simulated computer chip, thereby generating the model of the simulated computer chip; the topological structure of the model of the simulated computer chip is the same as the topological structure of the neural network model. The above solution enables the simulated computer chip to have stronger computing power and faster computing speed when having the same volume.

To provide a novel semiconductor device.SOLUTION: Using a comparison unit that compares two current values, a control unit, and a current-output type digital-analog conversion unit, an analog signal is converted into a digital signal. The control unit has a function of generating a sign bit expressing a magnitude relation between the two current values, a function of converting a difference between the two current values into the digital signal by sequential comparison, and a function of outputting the sign bit and the digital signal.SELECTED DRAWING: Figure 1

A novel semiconductor device is provided. An analog signal is converted into a digital signal using a comparison portion comparing two current values, a control portion, and a current output digital-analog conversion portion. The control portion has a function of generating a sign bit showing a magnitude relation between the two current values, a function of converting a difference between the two current values into a digital signal by successive approximation, and a function of outputting the sign bit and the digital signal.

The present invention discloses an in-memory computing device, which includes a memory array, p×q analog-to-digital converters, and a stepped adder. The memory array is divided into p×q storage partitions, where both p and q are positive integers greater than 1. Each storage partition has multiple partition bit lines, which are respectively coupled to corresponding global bit lines through a plurality of bit line selection switches. The bit line selection switches are respectively turned on or off according to a plurality of control signals. The memory array receives a plurality of input signals. The analog-to-digital converters are respectively coupled to the multiple global bit lines of the storage partitions. The analog-to-digital converters respectively convert the electrical signals on the global bit lines to generate p×q digital sub-output values. The stepped adder is coupled to the analog-to-digital converters and performs an addition operation on the sub-output values to generate an operation result.

To provide a processing device, and an electronic device having the same.SOLUTION: A processing device with improved computational reliability is provided, the processing device comprising a variable resistor layer including active variable resistors, an active layer including switches configured to control voltage applied across or current flowing through the active variable resistors, and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches.SELECTED DRAWING: Figure 9A

The invention relates to an adjustable square wave signal synthesis method and a digital frequency synthesizer, and the method comprises the steps: executing repeated accumulation operation through a phase accumulator according to an initial phase PCW and a target frequency control word FCW, and generating a continuous carry signal CARRY; the integration module performs integration operation on a target frequency control word FCW according to a continuous carry signal CARRY and outputs an integration voltage Vinteg, the comparator compares the integration voltage Vinteg with a preset reference voltage Vref to obtain a comparison result signal CMPOUT, and the trigger performs signal flipping according to the comparison result signal CMPOUT to generate a square wave signal Dout; according to the invention, by utilizing the periodicity of the carry signal and the current source in a correlation proportion with the target frequency control word FCW, the balance between the total charging amount and the total discharging amount of the capacitor in the whole period is realized, and the stability and the reliability under the actual circuit application are ensured.