46 results about "Nanoelectronics" patented technology

The invention relates to the technical field of micro-nano manufacturing, in particular to air pressure type nano-imprinting equipment integrating stepping glue spraying, which comprises an air flotation damping platform, a stepping glue spraying module, air pressure type nano-imprinting equipment 3 and an integrated process unit, precise spraying of a micron-sized colloid array is achieved through a piezoelectric control glue spraying head, and high-uniformity air pressure imprinting is completed in combination with an air flotation damping platform and a six-axis leveling mechanism. The equipment also integrates the functions of glue spraying, impressing, curing and demolding, supports the manufacturing of a multi-region special-shaped structure, has the residual glue amount of less than 10nm, and is suitable for efficient preparation of nano electronic and optoelectronic devices.

The invention discloses a double-layer heterostructure device, a design method and application in spin thermoelectric conversion, and belongs to the technical field of nanoelectronics. The design method comprises the following steps: cutting two-dimensional C2N into single-layer C2NNR; based on a single-layer C2NNR, considering the alignment condition of different atoms between an upper layer and a lower layer in a transport period, and constructing b-C2NNR van der Waals heterostructures with different stacking modes; the bl-C2NNR van der Waals heterostructures in different stacking modes are used for respectively building a double-layer heterostructure device; under the condition of zero bias, the temperature of the left electrode and the right electrode of the double-layer heterostructure device and the temperature difference of the left electrode and the right electrode are changed to cause the double-layer heterostructure device to generate thermal driving current, it can be calculated that charge current Ic is restrained, at the moment, the double-layer heterostructure device can conduct spinning thermoelectric conversion, and therefore the material library of low-dimensional nano-electronic devices is expanded. The material has the potential to become one of excellent reserve materials of spinning thermoelectric nano devices.

The invention provides a gate injection type ferroelectric field effect transistor and a preparation method thereof, and belongs to the technical field of micro-nano electronics. The ferroelectric field effect transistor structurally comprises a semiconductor substrate, a highly-doped source region, a highly-doped drain region, a metal gate electrode and a gate stack, the structure of the gate stack sequentially comprises a channel insulating layer, a ferroelectric layer, a charge trapping layer and a gate insulating layer from bottom to top, the charge trapping layer comprises three layers of materials, and the structure of the charge trapping layer sequentially comprises a layer of charge trapping material, a layer of barrier layer insertion layer and a layer of charge trapping material from bottom to top; the metal gate electrode is located on the gate stack, and the highly-doped source region and the highly-doped drain region are located on the two sides of a channel region below the gate stack respectively. By introducing the charge trapping layer and inserting the barrier layer in the charge trapping layer, the storage characteristic of the device is improved, the preparation method is simple, and a material system is compatible with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process; the storage window and the retention characteristic of the gate injection type ferroelectric field effect transistor are improved, and the gate injection type ferroelectric field effect transistor has high practical value.

The present invention relates to a novel method for the preparation of photoaligning polymer materials comprising aryl acrylic acid ester groups, to photoalignment compositions obtained by this process, to the use of the composition as orienting layer for liquid crystals and to non-structured and structured optical elements, electro-optical elements, multi-layer systems or in nanoelectronics comprising the compositions.

The invention belongs to the technical field of crossing of nano electronics, superconducting technology and quantum information science, and relates to a preparation method of flux quantum bits, which comprises the following steps: 1, processing a substrate; 2, depositing and oxidizing an aluminum film; 3, photoetching and etching to form a large structure; 4, forming a double-layer electron beam adhesive and a suspension bridge structure; 5, carrying out first dip angle evaporation and oxidation; 6, second-time dip angle evaporation; 7, removing photoresist; parameter consistency, yield and microwave performance of the prepared device all reach the industry leading level, the packaging mode is compatible with an existing system, and a reliable solution is provided for large-scale integration of a quantum computing system.

The invention provides a method and device for constructing sub-5 nano-metal gaps in a large area, and the method comprises the steps: forming a discontinuous first metal layer through employing a patterning technology, employing a dielectric film with atomic-scale thickness precision as a gap template, and constructing a second metal layer complementary with the first metal layer through combining with an overlay, oblique cutting and selective stripping technologies, thereby achieving the large-area construction of sub-5 nano-metal gaps. And finally, a high-precision metal nano gap is released by removing the medium template, so that controllable preparation of a large-area and high-uniformity sub-5-nano metal gap structure is realized. The preparation method breaks through the limitation of the traditional preparation method on the aspects of structural design flexibility, gap width precision and large-area processing, and is particularly suitable for the graphical manufacturing of the high-precision independent metal gap unit in micro-nano electronics, micro-nano optics and quantum mechanics devices. The nano-gap structure prepared by the method has a closed or open topological configuration, the unit size can reach the submicron level, and a new technical direction is provided for large-scale application of a nano-gap device in an integrated optical system.

To solve problems such as the deterioration of the marine environment, including marine ecosystems, due to marine litter in recent years, particularly the problem of marine plastic litter, which not only occurs in large quantities every day around the world but also remains in the ocean for long periods of time and requires global-scale measures, and problems such as the reuse of industrial waste, such as salmon milt, which amounts to approximately 10,000 tons per year and is disposed of as industrial waste in Japan, in order to realize a sustainable society.SOLUTION: With the aim of potentially reusing the DNA contained in salmon milt and reducing the burden on the marine environment in mind, we focused on DNA not as a gene but as a polymeric material, leading to the invention of a DNA paste that could be used in enzymatically degradable plastics and thin film applications in nanoelectronics. Specifically, dialdehyde is added to an aqueous solution of DNA salt, and the paste is then baked at a temperature above the melting point of DNA, resulting in crosslinking.SELECTED DRAWING: Figure 1

The invention discloses a writing method of a ferroelectric field effect transistor array, and belongs to the technical field of micro-nano electronics. According to the method, a self-compensation write-in method is provided for a multi-stage storage ferroelectric field effect transistor array of a 1T structure, a pulse sequence of a self-compensation waveform is adopted for write-in and corresponds to different storage states in multi-stage storage, positive pulse write-in is adopted when the pulse sequence is higher than an intermediate storage state, and negative pulse write-in is adopted when the pulse sequence is lower than the intermediate storage state. The method comprises the following steps of: writing a FeFET memory cell, performing read verification on a written state of the FeFET memory cell, starting an error correction program for correction when a write error is found so as to reach a target state, and starting a durability recovery program to recover the performance of the FeFET memory device if the error correction program fails; the method simultaneously solves the reliability problems of large fluctuation between devices and between cycles, limited durability and serious write-in crosstalk, has the advantages of simple process, low hardware overhead and the like, is compatible with the current advanced node CMOS technology, and is easy to implement.

The application provides a high-durability FeFET based on a ferroelectric hafnium aluminum oxide and aluminum oxide gate stack and a preparation method thereof, and belongs to the field of micro-nano electronics. The FeFET device comprises a silicon substrate, a patterned aluminum oxide intermediate layer, a hafnium aluminum oxide ferroelectric layer, a gate metal electrode and a contact metal are sequentially arranged on the surface of the silicon substrate, a source-drain region is formed on the surface of the silicon substrate through self-aligned ion doping, a source-drain metal contact electrode is arranged above the source-drain region, the hafnium aluminum oxide ferroelectric layer is grown through atomic layer deposition, the cycle number of hafnium oxide and aluminum oxide is controlled in the atomic layer deposition cycle process to control the atomic proportion of doping, the proportion of hafnium atoms and aluminum atoms in the finally formed hafnium aluminum oxide ferroelectric layer is 24:1, and the hafnium aluminum oxide ferroelectric layer stores two storage states in different polarization states. The application can improve the durability of the FeFET storage device.

This invention belongs to the field of semiconductor devices and micro / nanoelectronics technology, and discloses a CNTFET based on MoTi alloy contacts and its fabrication method. The CNTFET includes a substrate, a gate electrode, a gate dielectric layer, a carbon nanotube channel, and source and drain electrodes, wherein the source and drain electrodes are MoTi alloys or multilayer metal structures coated with MoTi layers. By controlling the Mo / Ti atomic ratio and optimizing deposition process conditions, this invention constructs a contact structure with tunable work function, high oxidation resistance, and excellent thin film quality, effectively reducing the Schottky barrier between the metal and carbon nanotubes, and achieving stable near-ohmic contacts. This device overcomes the shortcomings of existing technologies such as easy oxidation of low work function metals like Sc and Y, poor interface stability, and insufficient process compatibility. It significantly reduces contact resistance and improves the N-type conductivity stability, on-state current, and long-term reliability of the device in air environments, making it suitable for the integration of high-performance carbon-based logic devices and next-generation micro / nanoelectronic systems.

The invention discloses a ferroelectric tunnel junction based on a two-dimensional TiSe2 / Sc2CO2 Van der Waals heterostructure and a design method thereof, and belongs to the technical field of nanoelectronics. The ferroelectric tunnel junction comprises a left electrode, a central scattering region and a right electrode which are connected in sequence; the left electrode and the right electrode are respectively formed by periodically repeating a TiSe2 / Sc2CO2 Van der Waals heterostructure leftwards and rightwards; the central scattering area is composed of N Sc2CO2 single-layer orthogonal unit cells, the length of the central scattering area is N times of the length of the Sc2CO2 single-layer orthogonal unit cells, and N is a positive integer; the TiSe2 / Sc2CO2 Van der Waals heterostructure is formed by stacking a two-dimensional metal TiSe2 and a two-dimensional ferroelectric body Sc2CO2, and each ferroelectric tunnel junction only comprises the TiSe2 / Sc2CO2 Van der Waals heterostructure in one polarization direction. The device has the ohm-Schottky contact reversible switching characteristic, stable switching of high and low conductivity states under the zero bias voltage condition is achieved, and an important theoretical basis and a feasible implementation path are provided for design of next-generation high-performance ferroelectric logic devices and memories.

The invention discloses a rectifier diode based on a C3Al heterojunction and a design method thereof, belonging to the field of nanoelectronic technology; a design method for a rectifier diode based on a C3Al heterojunction comprises: cutting a C3Al nanoribbon into three edge forms; calculating an energy band structure diagram for the C3Al nanoribbons with the three edge forms; using the C3Al nanoribbons with the three edge forms to respectively build heterojunction devices; calculating current values ​​of the heterojunction devices at different voltages; designing a rectifier diode using the current value of the device; negative differential resistance effect and rectification phenomenon occur in heterojunction devices built based on C3Al nanoribbons with different edges, which greatly enriches the application of the C3Al nanoribbon in the field of electronic devices.

This application belongs to the field of semiconductor optoelectronic devices and micro / nanoelectronics, specifically disclosing a two-dimensional memory junction device and its fabrication, performance acquisition, and application methods. The two-dimensional memory junction device includes a first contact electrode, a doped n-type Si layer, and AgO. x Charge trapping layer and second contact electrode; AgO x The charge trapping layer and the doped n-type Si layer are combined to form a heterojunction resistive switching region; the heterojunction resistive switching region is used for AgO-based... x The trapping ionization and deionization transitions in the charge trapping layer, driven by voltage, achieve continuously adjustable and mutually coupled memory strength in both photovoltaic responsivity and conductivity dimensions, while exhibiting non-volatility. This application can store information in two different dimensions—photovoltaic and conductivity—and a compact and efficient machine vision system can be built using a single device to construct two-dimensional arrays.

The present disclosure describes electrically stimulating biological systems using meshes, wherein the mesh comprises nanoscale wires and / or nanoelectronics. These may be embedded as a scaffold in biological structures, such as tissues, organoids, organs, organisms, and the like. These may be connectable to an external device to determine a property of the scaffold and / or to apply a stimulus to the biological structure. Certain embodiments are Al-driven systems designed for applications such as drug screening, stem cell therapy, or the like. In addition, some embodiments are directed to predictive models that can be used to predict and / or control the biological structure. For example, certain cells may be caused to mature more quickly, and / or the functionality of the biological structure may be enhanced or inhibited by using such models to apply suitable electrical stimuli to the biological structure, and / or portions of the biological structure.

The application discloses a writing method of a ferroelectric field effect transistor array, and belongs to the technical field of micro-nano electronics. The method is used for a multi-level storage ferroelectric field effect transistor array with a 1T structure, and a self-compensation writing method is provided. A pulse sequence with a self-compensation waveform is used for writing, and different storage states in the multi-level storage are corresponded. A positive pulse is used for writing when the storage state is higher than a middle storage state, and a negative pulse is used for writing when the storage state is lower than the middle storage state. The state of a FeFET storage unit after writing is read and verified. When a writing error is found, an error correction program is started to correct the error to reach a target state. If the error correction program fails, a durability recovery program is started to recover the performance of the FeFET storage device. The application solves the reliability problems of large fluctuation between devices and cycles, limited durability and serious writing crosstalk between devices, has the advantages of simple process and small hardware cost, and is compatible with current advanced CMOS technology and easy to implement.

The invention discloses a ferroelectric field effect transistor FeFET with optimized double interface layers and a preparation method of the ferroelectric field effect transistor FeFET, and belongs to the technical field of micro-nano electronics. The FeFET structure comprises a silicon substrate, a source, drain and gate laminated structure and a gate metal electrode, the gate laminated structure comprises an optimized double-interface layer and a hafnium zirconium oxide ferroelectric layer, the double-interface layer comprises a lower silicon oxide interface layer and an upper aluminum oxide interface layer, the hafnium zirconium oxide ferroelectric layer is arranged on the double-interface layer, and the gate metal electrode is arranged on the hafnium zirconium oxide ferroelectric layer. An optimized double-interface layer structure is introduced, the charge trapping effect in the writing and circulating process of the FeFET is restrained, the storage window and durability of the FeFET are optimized, meanwhile, the storage density and reliability of the FeFET are optimized, and the restriction of tradeoff between the FeFET and the storage window is broken through. According to the method, the size of the prepared FeFET is reduced by adopting the electron beam lithography technology, and the integration density of the FeFET is improved; and the preparation process is completely compatible with an advanced node CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process, and is expected to be applied to large-scale integrated circuit manufacturing.

The application discloses a metal nanomaterial, in particular discloses a thermoluminescence color-changing metal nanomaterial, a preparation method and application thereof. The thermoluminescence color-changing metal nanomaterial exhibits a significant temperature-dependent characteristic in emission intensity under ultraviolet excitation. The thermoluminescence color-changing metal nanomaterial can be used as a nanometer fluorescence thermometer and has wide application in the technical fields of biological medicine, environmental monitoring and nanoelectronics.

A simulation of an electronic device may use a distribution of atomistic defects to provide more accurate results. An input mesh may be received representing a physical structure of the electronic device. This input mesh may be transformed into a polyhedral mesh to facilitate the simulation. A distribution of defects may then be generated and distributed throughout the polyhedral mesh. When performing each time step of the simulation, the effects of these defects may be attributed to individual cells in the polyhedral mesh and incorporated into the simulation equations for each volume. For example, charge and power contributions from the defects may be incorporated into the simulation equations to more accurately model the performance of the device.

The invention discloses a reservoir calculation implementation method based on a double-transistor structure, and belongs to the technical field of micro-nano electronics. High-precision time sequence signal processing is achieved only through a unit composed of two transistors, the two transistors are the writing transistor and the reading transistor respectively, the source end of the writing transistor is connected with the gate end of the reading transistor to form a storage node SN used for temporarily storing signal charges, the drain end and the gate end of the writing transistor are connected with the WBL and the WWL respectively, and the storage node SN is connected with the WBL and the WWL respectively. The drain end and the source end of the reading transistor are respectively connected with the RBL and the ground, a signal to be detected is input on the WWL, the square law charging of a saturation region of the writing transistor is combined with the nonlinear relaxation of leakage current, and the attenuation of the charge quantity of the storage node SN is mapped into 16 dynamic response states of the current of the reading bit line (RBL) through the transconductance amplification effect of the reading transistor. According to the method, a high-discrimination feature space is provided for reservoir calculation, and the multi-scale time sequence signal processing requirement is met.

A method implemented with a computing device for estimating a physical parameter in a spatial object includes obtaining at least one property of the spatial object, obtaining a mesh representing a topology of the spatial object, assembling a first tensor based on the at least one property and the mesh, the first tensor having at least a first and a second component representing a first and a second point in the mesh, respectively, executing simultaneously, by a first and a second processing unit of the computing device, a predetermined function on the first and the second component, respectively, and generating a first and a second estimation of the physical parameter at the first and second point, respectively, from executing the predetermined function on the first and the second component, respectively.

The application discloses a reserve pool calculation method based on 2T0C dual-mode judgment, and belongs to the technical field of micro-nano electronics. hold By changing the storage node relaxation time constant tau, the short relaxation and the long relaxation are switched between each other, and the multi-level threshold layer judgment mechanism is combined, so that the complementary extraction and fusion classification of the image time sequence-space double features are realized, the precision and the generalization ability of image recognition are obviously improved, and the advantages of simple hardware structure and low power consumption are kept.

The present invention relates to a novel method for the preparation of photoaligning polymer materials comprising aryl acrylic acid ester groups, to photoalignment compositions obtained by this process, to the use of the composition as orienting layer for liquid crystals and to non-structured and structured optical elements, electro-optical elements, multi-layer systems or in nanoelectronics comprising the compositions.

A simulation of an electronic device may use a distribution of atomistic defects to provide more accurate results. An input mesh may be received representing a physical structure of the electronic device. This input mesh may be transformed into a polyhedral mesh to facilitate the simulation. A distribution of defects may then be generated and distributed throughout the polyhedral mesh. When performing each time step of the simulation, the effects of these defects may be attributed to individual cells in the polyhedral mesh and incorporated into the simulation equations for each volume. For example, charge and power contributions from the defects may be incorporated into the simulation equations to more accurately model the performance of the device.

The invention discloses a high-durability FeNAND device with a micro heater and a preparation method of the high-durability FeNAND device, and belongs to the technical field of micro-nano electronics. The FeNAND memory is composed of the FeNAND memory and the micro heater, and the Joule heat generated by the micro heater is utilized to recover the fatigue of the FeNAND device caused by write-in circulation, so that the durability of the FeNAND is effectively optimized, and the storage density of the FeNAND memory is not influenced at the same time. The FeNAND device with the micro heater is compatible with an advanced node three-dimensional NAND storage technology, no extra technology cost is introduced, the influence on the storage density is small, and the FeNAND device can be conveniently applied to the three-dimensional FeNAND storage technology.

This invention discloses a one-dimensional coaxial heterostructure composite material, its preparation method, and its applications. The one-dimensional coaxial heterostructure composite material comprises: a nanotube with a cavity structure, and a one-dimensional embedded material uniformly embedded within the cavity structure of the nanotube. The one-dimensional embedded material includes one or more combinations of molybdenum sulfide, molybdenum selenide, and molybdenum telluride, forming a coaxial heterostructure between the nanotube and the embedded material. The preparation method of this invention efficiently synthesizes the one-dimensional coaxial heterostructure composite material on a substrate using chemical vapor deposition. This method is simple, versatile, and has the potential for large-area preparation. The prepared one-dimensional coaxial heterostructure composite material has advantages such as high quality and good uniformity, ensuring the convenience of synthesizing the one-dimensional heterostructure and providing a new material foundation for the development and application of embedded one-dimensional materials in nanoelectronics, nanooptics, and other fields.

The application discloses a preparation method of metal nanometer material surface protrusions and belongs to the field of nanoelectronics. In the application, metal nanometer wires or nanometer strips are first prepared into two-end devices, the metal nanometer wires are annealed by using Joule heat, and the initial morphology of the surface of the nanometer wires is stabilized through electrical preparation operation, then a semiconductor parameter analyzer and a matched probe station are used to perform current-voltage (I-V) scanning on the metal nanometer wires, the three-dimensional metal protrusions on the surface of the nanometer wires are regulated to the required morphology and height by monitoring the transient slope of the R-V curve of the nanometer wires and the amplitude of the resistance increase.

The present disclosure generally relates to devices and methods to determine and / or terminate cardiac arrhythmias. In some embodiments, the devices comprise meshes comprising nanoscale wires and / or nanoelectronics. In some case, meshes may be embedded in or placed upon a tissue at a target location within or on a heart. In some embodiments, the meshes may be connectable to an external device (e.g., to determine an electrical property at the target location and / or to apply an electrical stimulus to the target location). Other aspects relate to using the devices and methods disclosed herein for the treatment of cardiac arrythmia, such as atrial fibrillation. Additional non-limiting embodiments are generally directed to Al-driven systems to guide treatment of the arrythmia. For example, some embodiments are generally directed to predictive models that can be used to predict and / or control a pulse sequence of electroactive cells at the target location in the heart (e.g., to detect and correct an aberrant electrogram at the target location by delivering an appropriate pulse sequence).

The invention provides a gate stack structure FeFET and a preparation method thereof, and belongs to the technical field of micro-nano electronics. The FeFET structure comprises a silicon substrate, a source laminated layer, a drain laminated layer, a gate metal electrode, a passivation layer and a contact metal electrode, the gate laminated layer comprises an aluminum oxide channel interface layer and a double-layer hafnium zirconium oxide ferroelectric layer, and a thin aluminum oxide middle interface layer is inserted between the double-layer ferroelectric layer to effectively inhibit continuous growth of crystal grains in the ferroelectric layer. A write pulse with a larger amplitude and a shorter width is applied to the gate region of the FeFET structure, so that the consistency and durability of the FeFET device are synergistically optimized; the preparation process of the FeFET is mature, can be quickly applied to large-scale circuit design of the FeFET, and has a wide application prospect.

The invention belongs to the technical field of memories in the micro-nano electronic technology, and particularly relates to a phase change film containing an embedded nano heating electrode and a phase change memory. According to the phase change film containing the embedded nano heating electrode, the compound electrode material and the phase change material are co-doped by adopting a conventional doping process and then are subjected to pulse treatment, so that the compound electrode material spontaneously forms a bond to form the embedded nano heating electrode, and the local current density in the phase change film of the device is regulated and controlled; the heat production efficiency of the phase-change film is increased, the heat loss of the device is reduced, and the power consumption of the device is reduced. Meanwhile, the embedded nano heating electrode can effectively hinder migration of atoms in the phase change material, reduce structural relaxation and element segregation of the phase change material, and improve the cycle performance of the device. The method breaks through the limitation of the process, effectively reduces the size of the heating electrode, is simple in process step, obviously reduces the operation power consumption of the device, and greatly improves the cycle performance.

The invention discloses a ferroelectric field effect transistor based on gate stack optimization and a preparation method thereof, and belongs to the technical field of micro-nano electronics. The gate laminated structure optimized by the FeFET comprises an aluminum oxide channel interface layer, a double-layer hafnium zirconium oxide ferroelectric layer, an aluminum oxide gate interface layer and a gate metal electrode which are sequentially stacked on top silicon of a substrate, the double-layer hafnium-zirconium-oxide ferroelectric layer comprises an upper hafnium-zirconium-oxide ferroelectric layer and a lower hafnium-zirconium-oxide ferroelectric layer which are consistent in thickness, and an aluminum oxide middle interface layer between the two hafnium-zirconium-oxide ferroelectric layers. According to the novel FeFET gate stack structure design, through collaborative optimization between the ferroelectric layers and the interface layers, MW is increased, meanwhile, the stress of the interface layers is reduced, durability is optimized in a multi-bit storage FeFET unit, D2D fluctuation is restrained in a FeFET with the reduced size, the limitation of the tradeoff effect is successfully broken through, and the performance of the device is improved. And comprehensive improvement of the storage density and reliability of the FeFET is realized. The size of the prepared FeFET is reduced by adopting the electron beam lithography technology, so that the integration density of the FeFET is improved.