Low-power fin type field effect transistor and manufacturing method thereof

Abstract

The invention provides a low-power fin type field effect transistor and a manufacturing method thereof, and belongs to the technical field of super-large integrated circuit manufacture. The thickness of a sidewall channel layer and the thickness of a top channel layer of the field effect transistor are no greater than 10nm, and a fin-type isolation bar is formed on a deep body area far away from top gate control. Further shortening of a device trench length is facilitated, short channel effect control ability of the device is improved, and static power consumption is minimized. The source-drain area of the device is a monocrystalline active island, and has maller source-drain series resistance. Compared with a fin type field effect transistor employing lifting source-drain structure, the low-power fin type field effect transistor requires no epitaxial lifting source-drain to obtain rapidly high open-state current. The low-power fin type field effect transistor is compatible with conventional IC-manufacture technology and has the advantages of simple process and low manufacture cost.

Description

technical field [0001] The invention belongs to the technical field of ultra-large-scale integrated circuit manufacturing, and relates to a low-power consumption fin field effect transistor and a preparation method thereof. Background technique [0002] When semiconductor devices enter the 22nm technology generation, Fin Field Effect Transistor (FinFET) is a representative of three-dimensional multi-gate MOSFET (MuGFET), which has outstanding ability to suppress short channel effect and high integration density, and its preparation process Compatible with the traditional CMOS process, it has become the mainstream of semiconductor devices. However, when moving towards a smaller technology node, the deep body region of the three-dimensional multi-gate device is far away from the top gate control, which will cause a large leakage current and increase the static power consumption of the device. [0003] In order to overcome this problem, the method of thinning the Fin width is ...

AI Technical Summary

Problems solved by technology

However, if you want to form thinner and high-aspect-ratio Fin by etching, it poses a great challenge to the etching process, and the formation of ultra-thin Fin sidewalls by etching will have a large edge roughness , resulting in the degradation of the consistency of the device characteristics; in addition, in order to suppress the leakage of the deep body region, the doping of Fin will not only cause the degradation of the channel mobility, but also introduce a large random doping fluctuation (RDF), which limits The application of multi-gate devices in the field of low power consumption

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