Stacked gate dielectric GaN-based insulated gate high-electron mobility transistor and manufacturing method
A high electron mobility, insulating gate technology, used in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve the problems of unstable oxygen substitution nitrogen, unstable threshold voltage, negative threshold voltage drift, etc. Activity, improved compatibility, reduced process temperature effects
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[0032] In the first embodiment, an AlN dielectric insertion layer 81 with a thickness of 2 nm is fabricated on a sapphire substrate, and HfO 2 The high-k dielectric layer 82 has a GaN-based insulated gate high electron mobility transistor with a thickness of 8 nm.
[0033] Step 1, forming a source electrode 10 and a drain electrode 11 on the GaN buffer layer 3 of the epitaxial substrate.
[0034] 1a) Lithography of the source electrode 10 area and the drain electrode 11 area on the GaN cap layer 6:
[0035] First, put the epitaxial substrate on a hot plate at 200°C for 5 minutes;
[0036] Then, apply peeling glue and spin glue on the GaN cap layer 6 with a thickness of 0.35 μm, and place the sample on a hot plate at 200°C for 5 minutes;
[0037] Then, apply the photoresist and spin the glue on the peeling glue, the thickness of the glue is 0.77μm, and the sample is baked on a hot plate at 90°C for 1 min;
[0038] Afterwards, put the glue-coated and glue-spun samples into a photolithograp...
Example Embodiment
[0118] In the second embodiment, the thickness of the AlN dielectric insertion layer 81 is 1nm on the SiC substrate, and the Al 2 O 3 The dielectric layer 82 has a GaN-based insulated gate high electron mobility transistor with a thickness of 4 nm.
[0119] Step one: fabricate a source electrode 10 and a drain electrode 11 on the GaN buffer layer 3 of the epitaxial substrate.
[0120] 1.1) Lithography of the source electrode 10 area and the drain electrode 11 area on the GaN cap layer 6:
[0121] The specific implementation of this step is the same as step 1a) in the first embodiment;
[0122] 1.2) Evaporate the source electrode 10 and the drain electrode 11 on the GaN cap layer 6 in the region of the source electrode 10 and the drain electrode 11 and on the photoresist outside the region of the source electrode 10 and the drain electrode 11:
[0123] The specific implementation of this step is the same as step 1b) in the first embodiment;
[0124] 1.3) Put the sample after ohmic metal e...
Example Embodiment
[0151] In the third embodiment, the thickness of the AlN dielectric insertion layer 81 is 1.5nm on the Si substrate, and the HfO 2 The high-k dielectric layer 82 has a GaN-based insulated gate high electron mobility transistor with a thickness of 6 nm.
[0152] Step A, the source electrode 10 and the drain electrode 11 are fabricated on the GaN buffer layer 3 of the epitaxial substrate.
[0153] The specific implementation of this step is the same as step 1 in the first embodiment.
[0154] Step B, photoetching the electrical isolation area of the active area on the GaN cap layer 6, and using an ion implantation process to produce electrical isolation of the active area of the device.
[0155] The specific implementation of this step is the same as that of step two in the second embodiment.
[0156] Step C, on the source electrode 10, the drain electrode 11 and the GaN cap layer 6 in the active area, a SiN passivation layer 7 is grown by a PECVD process.
[0157] The specific impleme...
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