679 results about "High-electron-mobility transistor" patented technology

A structure includes a transistor, e.g., HEMT, with a field plate positioned laterally to a side of an active gate and including a first portion extending over the active gate. A dielectric layer isolates a lower surface of the first portion from an upper surface of the active gate. A field plate contact includes interconnect layers located directly over the active gate and electrically coupled to the first portion directly over the active gate. The field plate contact allows electrical operation of the field plate, but also acts as a thermally conductive path from the active gate through the interconnect layers to cool likely hot spots within the transistor.

The invention discloses a junction temperature testing device and method for a high-electron-mobility transistor. A current measuring module in the junction temperature testing device for the high-electron-mobility transistor is used for acquiring current flowing through a tested device; the power supply module is electrically connected with the other end of the switch module, and the power supply module and the switch module are connected in parallel with the bus capacitor; the control module is electrically connected with the control end, the driving end and the regulation and control end of the switch module, and the control module is used for providing switching signals for the control end, the driving end and the regulation and control end of the switch module so as to control the switching states of the switch protection module, the tested device and the switch module; the heating plate is used for heating a tested device; the temperature detection module is used for measuring the temperature of the detected device; and the waveform analysis module is electrically connected with the control module, the temperature detection module and the current measurement module, and is used for obtaining and forming an experimental oscillogram of the tested device at the temperature according to the temperature, the current and the conduction time of the tested device controlled by the control module.

The invention provides a preparation method of a GaN HEMT (High Electron Mobility Transistor) device and the GaN HEMT device. The preparation method comprises the following steps: forming a substrate of an SIC material of a second doping type; forming a single SIC epitaxial wafer of the first doping type growing along the C axis; forming an electric field stop layer of a first doping type on the front surface of the SIC epitaxial wafer; wherein the doping concentration of the electric field stop layer is greater than that of the substrate; forming a stripping layer at a position below the electric field stop layer in the SIC epitaxial wafer; wherein the part, located between the electric field stop layer and the stripping layer, in the SIC epitaxial wafer serves as an electric field pressure bearing layer; bonding the front surface of the electric field stop layer and the front surface of the substrate together; stripping is carried out at the stripping layer; the electric field stop layer is arranged on the substrate, and the electric field pressure bearing layer is arranged on the electric field stop layer. According to the GaN HEMT device and the manufacturing method thereof, the technical problem caused by relatively high cost of a traditional GaN HEMT device is solved.

Methods, systems, and apparatus are provided for normally open GaN high electron mobility transistor (HEMT) integration on a monolithic p-GaN integrated circuit (IC) platform. In particular, the integrated circuit platform may include both enhanced and depletion mode HEMT power devices in a monolithic integrated p-GaN power IC. An exemplary method may include treating at least one of the plurality of p-GaN gates with an in-situ plasma treatment to deactivate Mg in the treated p-GaN gate and deplete Mg of the p-GaN gate. The depleted p-GaN gate may be a gate of a normally-on HEMT in the IC. At least one of the p-GaN gates that is not exposed to the in-situ plasma pretreatment may be a gate of a normally off HEMT in the IC.

The invention relates to the field of gallium nitride high electron mobility transistor (GaN HEMT) compact modeling, and provides a p-GaN gate HEMT model establishment method based on a physical guided neural network (PGNN) in order to solve the problem of p-GaN gate HEMT compact model development, and the method comprises the following steps: constructing a p-GaN gate HEMT transistor model by using a TCAD simulation tool, generating a model sample, and extracting simulation data; constructing a DerivNet model and a loss function based on a physical guidance neural network; and finally, performing model training by using the simulation data to obtain the p-GaN gate HEMT model based on the physical guidance neural network.

A high-electron mobility transistor includes a substrate, a gate electrode, a drain electrode, a source electrode and a first field plate. The substrate includes an active region. The gate electrode is disposed on the substrate. The drain electrode is disposed at one side of the gate electrode. The source electrode is disposed at another side of the gate electrode. The first field plate is electrically connected with the source electrode and extends from the source electrode toward the drain electrode. An overlapping area of the first field plate and the gate electrode is smaller than an overlapping area of the gate electrode and the active region.

A high electron mobility transistor and a method of manufacturing the same are disclosed. The high electron mobility transistor includes a channel layer, a channel supplying layer causing generation of a two-dimensional electron gas (2DEG) in the channel layer, a source electrode and a drain electrode provided on respective sides of the channel supplying layer, a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG, a gate electrode provided on a portion of the depletion forming layer, and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer. The current limiting layer limits a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode.

The invention relates to the technical field of transistor structures, and provides a region activation mixed gate structure, a high electron mobility transistor and a manufacturing method, and the structure comprises a substrate structure, and a source electrode and a drain electrode which are disposed on the substrate structure. The gate depletion layer is arranged on the substrate structure and between the source electrode and the drain electrode; an activation enhancement region is formed between the activation enhancement layer and the gate depletion layer; the gate lead-out layer is arranged on the activation enhancement area and the area, not covered by the activation enhancement layer, of the gate consumption layer, and the area, making contact with the gate consumption layer, of the gate lead-out layer forms a low-leakage area. An activation enhancement region with high grid leakage is formed through an activation enhancement layer, a path for rapidly releasing trapped charges in a grid consumption layer is provided, and by adjusting the proportion of the activation enhancement region to a low leakage region, the grid performance is guaranteed while the trapped charges are rapidly released, the influence of the trapped charges is reduced, and the threshold voltage drift is improved. The switch performance and stability are improved.

The invention discloses a GaN HEMT (High Electron Mobility Transistor) device with high gate reliability and a preparation method thereof. The preparation method comprises the following steps: providing a basic structure; sequentially forming a p-type GaN layer, a gate material layer, a dielectric mask layer and a metal mask layer; patterning etching is carried out; carrying out wet etching on the metal mask structure, and meanwhile, generating a corrosion effect on the side surface of the grid precursor to form a grid; performing dry etching to form a p-type GaN structure; performing plasma treatment on the side surface; and respectively manufacturing and forming a source electrode and a drain electrode. Dry etching is replaced by wet etching to form a structure that the p-type GaN structure extends to the source and drain sides, grid self-alignment etching is achieved, the uniformity and controllability of an extension area are improved, the technological process is simplified, the repeatability of device structure preparation is guaranteed, meanwhile, plasma is used for treating and passivating the side wall, and the device structure is more stable in performance. Current leakage caused by a surface state and surface roughness is suppressed, off-state leakage of the device is greatly reduced, and reliability is improved.

The invention relates to a dynamic thermal characteristic characterization method for a GaN HEMT (High Electron Mobility Transistor) radio frequency device. The method comprises the following steps: acquiring structural parameters of the GaN HEMT radio frequency device Establishing a three-dimensional finite element thermal model according to the structure parameters of the GaN HEMT radio frequency device; adjusting material parameters of the three-dimensional finite element thermal model according to an infrared thermal imaging test result of the GaN HEMT radio frequency device; based on the three-dimensional finite element thermal model, simulation is carried out under different environment temperatures and dissipation powers, thermal resistance of the GaN HEMT radio frequency device is obtained, and the relation between the thermal resistance and the environment temperatures and the dissipation powers is obtained; and establishing a Foster-form third-order RC heater network model of the GaN HEMT radio frequency device on the basis of the relationship between the thermal resistance and the ambient temperature as well as between the thermal resistance and the dissipated power and in combination with the transient pulse current response of the GaN HEMT radio frequency device. According to the invention, the transient thermal characteristics of the device under different working conditions can be rapidly represented.

There is provided a field-programmable gate array, FPGA, device (100) comprising a configurable logic block, CLB, (110) comprising a logic inverter (120) comprising a high-electron-mobility transistor, HEMT, (130), wherein the HEMT comprises: a Si substrate (384); an AlyGay-1N layer structure (380), wherein 0<y≤1; a GaN layer structure (382); and a crystal transition layer structure (386) arranged on the Si substrate. The crystal transition layer comprises: a plurality of vertical nanowire structures (388) perpendicularly arranged on the Si substrate, and an AlxGax-1N layer structure (389), wherein 0≤x<1, wherein the AlxGax-1N layer structure is arranged to vertically and laterally enclose the vertical nanowire structures. There is also provided an AI processing system comprising said FPGA device (100).

The invention provides a GaN HEMT (High Electron Mobility Transistor) with strong non-clamping inductive switching capability in an irradiation scene and a preparation method thereof, and belongs to the technical field of semiconductors. Comprising a substrate layer, a gallium nitride layer, a passivation layer, a channel layer, a barrier layer and an electrode structure layer, the electrode structure layer comprises a grid electrode structure, a source electrode structure and a drain electrode structure, the source electrode structure and the drain electrode structure are arranged on the two sides of the grid electrode structure, the grid electrode structure is in a strip shape and arranged above the barrier layer in the first direction, and the source electrode structure and the drain electrode structure are connected with the channel layer; a plurality of rectangular P-type gallium nitride layers arranged in groups are arranged between the grid electrode structure and the drain electrode structure, the plurality of rectangular P-type gallium nitride layers arranged in groups are uniformly arranged at intervals along a first direction and are connected through a metal wire, the top of the metal wire is connected with a negative potential electrode, and an area between the potential barrier layer and the negative potential electrode is filled with a dielectric layer. The technical problems that the normal switching capability of a device is affected and the overvoltage robustness is degraded due to hole accumulation after irradiation of a traditional HEMT can be solved.

The invention provides a non-polar gallium nitride-based enhanced HEMT (High Electron Mobility Transistor) with low source-drain contact resistance, and relates to the technical field of semiconductors. Comprising an m-plane substrate, an unintentionally doped GaN buffer layer, a Fe doped GaN layer, a GaN channel layer, an AlN insertion layer and an AlGaN barrier layer which are sequentially arranged from bottom to top, the plurality of grooves are arranged in the edge areas of the two sides of the AlGaN barrier layer at intervals, penetrate through the AlGaN barrier layer and are in contact with the upper surface of the AlN insertion layer, and target GaN is arranged in each groove so as to form longitudinal AlGaN / GaN superlattice structures on the two sides; the GaN cap layer is formed on the middle region of the AlGaN barrier layer; the grid electrode is formed on the GaN cap layer; the source electrode is formed on the AlGaN / GaN superlattice structure on one side; and the drain electrode is formed on the AlGaN / GaN superlattice structure on the other side. In this way, the contact resistance is reduced without being affected by the polarization effect.

The invention discloses a GaN HEMT (High Electron Mobility Transistor) single-particle burnout effect evaluation method, which adapts to the characteristics of various GaN HEMT devices, can evaluate the single-particle burnout effect of a GaN HEMT device for aerospace, serves for aerospace models, and solves the problem of lack of single-particle evaluation methods for aerospace inverted GaN HEMT devices.

A HEMT device includes a substrate, a buffer layer, a channel layer, a barrier layer, and a dielectric layer sequentially disposed in such order in a bottom-up direction and cooperatively forming an active region; a source electrode and a drain electrode disposed oppositely on the active region; and a gate electrode including a comb structure disposed in a gate region between the source electrode and the drain electrode on the active region. The comb structure includes a comb stem portion and comb tooth portions connected to the comb stem portion. The comb tooth portions are spaced apart from each other in a gate width direction. The comb stem portion is disposed on the barrier layer and is parallel to the source electrode or the drain electrode. The comb tooth portions penetrate the dielectric layer to equal depths.

A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode on the p-type semiconductor layer, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode. Preferably, the buffer layer further includes a bottom portion having a first carbon concentration and a top portion having a second carbon concentration, in which the second carbon concentration is less than the first carbon concentration and a thickness of the bottom portion is less than a thickness of the top portion.

The embodiment of the utility model relates to an enhancement mode high electron mobility transistor device. An enhanced mode high electron mobility transistor device includes a semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas. A high electron mobility transistor device includes a gate structure extending over a top surface of a semiconductor body, biased to electrically control a two-dimensional electron gas, and including a functional layer and a gate contact in direct physical and electrical contact with each other. The gate contact is made of a layer of conductive material, and the functional layer is made of a layer of two-dimensional semiconductor material and includes a first doped portion having P-type conductivity extending over a top surface of the semiconductor body and interposed along a first axis between the semiconductor body and the gate contact. According to the embodiment of the invention, the low power consumption of the transistor in use is ensured, and the integration of the transistor into an electronic circuit in a design step is simplified.

The invention provides an enhanced GaN HEMT (High Electron Mobility Transistor) device and a preparation method thereof. The device comprises a substrate; the epitaxial structure is epitaxially grown on the substrate; the secondary epitaxial layer is epitaxially grown on the epitaxial structure; the dielectric layer is arranged on the secondary epitaxial layer; communicated groove regions are arranged in the p-GaN layer, the dielectric layer and the secondary epitaxial layer, and the p-GaN layer epitaxially grows in the groove regions from the upper surface of the epitaxial structure; the grid electrode is arranged on the p-GaN layer; and the source electrode and the drain electrode are respectively arranged at two sides of the epitaxial structure, the secondary epitaxial layer and the dielectric layer. The device has a better high-frequency dynamic characteristic; the stability and the consistency of the grid threshold voltage are improved; the crack generation risk of the epitaxial wafer is low, and the MBE-grown p-GaN does not need to be subjected to subsequent activation treatment; the gate reliability is improved, and the stability of the device is further improved.

A high electron mobility transistor includes a semiconductor structure, a stepped trench, an electrode, and a gate. The semiconductor structure includes a barrier layer and a channel layer. The barrier layer is disposed on the channel layer. A two-dimensional electron gas is formed at an interface between the channel layer and the barrier layer. The stepped trench is disposed in the semiconductor structure. The electrode is disposed in the stepped trench. The gate is disposed on the barrier layer. The stepped trench has a first width and a second width. The first width is greater than the second width.

The present disclosure relates to Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) (100) i.e. a semiconductor device (100) which includes a buffer layer (104) formed on the substrate (120). An unintentionally doped (UID) Gallium Nitride (GaN) channel layer (102) is positioned on the buffer layer (104). A barrier layer (106) is formed on the UID channel layer (102) to enable formation of two-dimensional electron gas (2DEG) at interface between UID GaN channel layer (102) and barrier layer (106). A stress transfer layer (116) having tunable intrinsic compressive mechanical stress is deposited on barrier layer (106) to enhance device performance and reliability. Further, the intrinsic stress in the stress transfer layer (116) is tailored to enhance performance in terms of higher threshold voltage and breakdown voltage, and reliability in terms of reduced dynamic RON under DC and switching stress and stable threshold voltage under ON and OFF state gate stress.

High Electron Mobility Transistors (HEMTs) are described with a circular gate. with a drain region disposed within the circular gates and circular source region disposed around the circular gates. The circular gate and the circular source region may form complete circles.

The invention relates to the technical field of low-noise amplifier optimization, and discloses an HEMT-based S-band low-noise amplifier optimization method, which comprises the following steps: acquiring working parameters of a low-noise amplifier, and performing one-time performance evaluation on the amplifier by comparing the working parameters with preset standard parameters. And comparing the one-time performance score with a preset performance scoring standard, and determining whether the low-noise amplifier needs to be optimized or not. After it is confirmed that optimization needs to be carried out, relevant optimization parameters are obtained, and simulation verification is carried out through the parameters. And performing secondary performance scoring by obtaining the optimized simulation parameters and comparing the optimized simulation parameters with preset working parameters. And finally, comparing the secondary performance score with a preset performance score standard to confirm whether the low-noise amplifier completes the optimization process or not. According to the steps of key working parameters, one-time performance evaluation, simulation verification, secondary performance scoring and the like, comprehensive evaluation and optimization of the performance of the low-noise amplifier are achieved.

The invention relates to an epitaxial structure of a low-specific on-resistivity GaN HEMT and a preparation method thereof, and the preparation method comprises the steps: S1, sequentially growing an initial layer, a buffer layer, a channel layer, a first insertion layer, a first barrier layer, a second insertion layer and a second barrier layer on a substrate from bottom to top, and obtaining a thick barrier epitaxial wafer; s2, preparing a hard mask layer, patterning and etching the hard mask layer, then transferring the hard mask layer to the upper surface of the thick barrier epitaxial wafer, and etching the thick barrier epitaxial wafer to the upper surface of the second insertion layer; s3, secondarily growing a p-GaN layer on the upper surface of the second insertion layer in the gate region; and S4, removing the polycrystalline GaN in a non-gate region, depositing metal on the p-GaN layer to manufacture a gate, and depositing metal on two sides of the structure to manufacture a source and a drain respectively. By selectively growing the p-GaN layer in the grid region, two-dimensional electron gas in a channel is effectively exhausted, and the carrier concentration of the region below the grid is remarkably reduced.

The invention discloses a barrier GaN heterojunction transistor with low source-drain resistance and high Al component and a preparation method thereof, the transistor structurally comprises a substrate, a composite buffer layer, a channel layer, an isolation layer, a barrier layer and a cap layer which are sequentially arranged from bottom to top, source and drain electrodes are arranged at two ends of the surface of the cap layer, and a gate electrode is arranged between the source and drain electrodes. Etching is carried out on a partial region below the source and drain electrodes to form a nano groove array structure, inclined-angle ion implantation activation is carried out, N-type heavy doping is formed near a nano groove, and metal is filled in the nano groove to form the source and drain electrodes. Source and drain electrode metal of the structure is in direct contact with 2DEG, and forms ohmic contact after being annealed together with an N-type heavily doped region, so that the contact resistance is reduced. According to the method, the problem that the resistance value of a source-drain electrode contact resistor prepared by a conventional method of a high-Al-component barrier GaN heterojunction material is large is solved, the output current of a GaN heterojunction high-electron-mobility transistor device is increased, and the preparation process is simple, easy to implement and outstanding in effect.

The embodiment of the invention relates to a high-electron-mobility transistor and a preparation method thereof, and the high-electron-mobility transistor comprises a substrate; the heterojunction structure is located on the substrate and comprises a channel layer and a barrier layer which are sequentially stacked in the direction away from the substrate, and a two-dimensional electron gas channel is formed in the area, close to the barrier layer, of at least part of the channel layer; the source electrode and the drain electrode are distributed on the heterojunction structure at intervals; a gate layer on the heterojunction structure and between the source electrode and the drain electrode; the RESURF structure layer is located on the heterojunction structure and comprises a first structure part adjacent to the gate layer in the direction parallel to the plane where the substrate is located and a second structure part extending from the first structure part to the direction away from the gate layer; the thickness of the part, located between the first structure part and the channel layer, of the barrier layer is smaller than that of the part, located between the second structure part and the channel layer; therefore, the RESURF structure plays a better role in the device.

The invention provides an enhanced gallium nitride high-electron-mobility transistor. The enhanced gallium nitride high-electron-mobility transistor comprises a substrate; the first epitaxial structure is formed on the substrate, and the first epitaxial structure comprises a channel layer and a barrier layer formed on the channel layer; the passivation layer is formed on the first epitaxial structure; the grid electrode comprises a groove, and the groove penetrates through the passivation layer and the barrier layer and extends into the channel layer; the second epitaxial structure part covers the bottom and the side wall of the groove and the upper surface of the passivation layer on the left side and the right side of the top of the groove; and a gate electrode formed on the second epitaxial structure portion. The groove gate enhanced MIS-HEMT device has the beneficial effects that the uniformity, the process repeatability, the robustness and the reliability of the threshold voltage of the groove gate enhanced MIS-HEMT device are improved.

The invention provides a high electron mobility transistor epitaxial structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a sapphire substrate; growing a boron-doped first buffer layer on the sapphire substrate: during growth, gradually reducing a boron component in a reaction material from a first preset value to 0 in a first preset duration, and continuously growing for a second preset duration after the boron component is reduced to 0, so that x in the first buffer layer is gradually reduced, and the boron component is gradually reduced to 0 from bottom to top; a boron-free GaN second buffer layer is grown on the first buffer layer, the growth rate of the second buffer layer is lower than that of the first buffer layer, and the thickness of the second buffer layer is larger than that of the first buffer layer; and sequentially growing a GaN high-resistance layer and a GaN epitaxial layer on the second buffer layer. Compared with the prior art, the defect density of the device can be effectively improved, electric leakage is reduced, and the stability and consistency of the device are improved.

The invention discloses a single-particle-resistant high-electron-mobility transistor which comprises a substrate layer, a buffer layer, a channel layer, a barrier layer and a gate structure layer which are arranged in a stacked mode in the second direction, and the surface, away from the buffer layer, of the channel layer is further provided with a first electrode structure and a second electrode structure. The first electrode structure and the second electrode structure are connected to the two sides of the barrier layer in the first direction respectively, and at least one buried layer is inserted into the buffer layer; wherein a polarization effect and two-dimensional electron gas can be generated between the buffer layer and the channel layer, and each buried layer is made of a p-type GaN material. According to the anti-single-particle high-electron-mobility transistor, the anti-single-particle capability of a device is improved under the condition that the original characteristics of the device are not changed.

The utility model relates to an HEMT (High Electron Mobility Transistor) device, comprising a body provided with a top surface and a heterostructure; a gate region including a semiconductor material disposed on the top surface of the body, the gate region having a first lateral sidewall and a second lateral sidewall opposite the first lateral sidewall; a sealing layer of a non-conductive material extending on and in contact with the first and second lateral sidewalls of the gate region; a passivation layer of a non-conductive material having a surface portion extending laterally to the first lateral sidewall of the gate region on the top surface of the body, the sealing layer and the passivation layer having different geometric parameters; and a spacer region of a non-conductive material between the passivation layer and the sealing layer, the spacer region separating the sealing layer from the passivation layer at a location where the passivation layer is not on the top surface of the body.

A high electron mobility transistor (HEMT) device includes a substrate, a channel layer, a source, a drain, a buffer layer, and a plurality of amorphous regions. The channel layer is located above the substrate. The source is located on the channel layer. The drain is located on the channel layer. The buffer layer is located between the substrate and the channel layer. The plurality of amorphous regions are located in the buffer layer below the source and the drain.