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372 results about "High-electron-mobility transistor" patented technology
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A high-electron-mobility transistor (HEMT), also known as heterostructure FET (HFET) or modulation-doped FET (MODFET), is a field-effect transistor incorporating a junction between two materials with different band gaps (i.e. a heterojunction) as the channel instead of a doped region (as is generally the case for MOSFET). A commonly used material combination is GaAs with AlGaAs, though there is wide variation, dependent on the application of the device. Devices incorporating more indium generally show better high-frequency performance, while in recent years, gallium nitride HEMTs have attracted attention due to their high-power performance. Like other FETs, HEMTs are used in integrated circuits as digital on-off switches. FETs can also be used as amplifiers for large amounts of current using a small voltage as a control signal. Both of these uses are made possible by the FET’s unique current-voltage characteristics. HEMT transistors are able to operate at higher frequencies than ordinary transistors, up to millimeter wave frequencies, and are used in high-frequency products such as cell phones, satellite television receivers, voltage converters, and radar equipment. They are widely used in satellite receivers, in low power amplifiers and in the defense industry.
Field plate structure to reduce self-heating in transistor and related method
A structure includes a transistor, e.g., HEMT, with a field plate positioned laterally to a side of an active gate and including a first portion extending over the active gate. A dielectric layer isolates a lower surface of the first portion from an upper surface of the active gate. A field plate contact includes interconnect layers located directly over the active gate and electrically coupled to the first portion directly over the active gate. The field plate contact allows electrical operation of the field plate, but also acts as a thermally conductive path from the active gate through the interconnect layers to cool likely hot spots within the transistor.
Owner:GLOBALFOUNDRIES US INC
High electron mobility transistor device and method of making the same
A HEMT device includes a substrate, a buffer layer, a channel layer, a barrier layer, and a dielectric layer sequentially disposed in such order in a bottom-up direction and cooperatively forming an active region; a source electrode and a drain electrode disposed oppositely on the active region; and a gate electrode including a comb structure disposed in a gate region between the source electrode and the drain electrode on the active region. The comb structure includes a comb stem portion and comb tooth portions connected to the comb stem portion. The comb tooth portions are spaced apart from each other in a gate width direction. The comb stem portion is disposed on the barrier layer and is parallel to the source electrode or the drain electrode. The comb tooth portions penetrate the dielectric layer to equal depths.
Owner:XIAMEN SANAN INTEGRATED CIRCUIT CO LTD
Enhanced mode high electron mobility transistor device
The embodiment of the utility model relates to an enhancement mode high electron mobility transistor device. An enhanced mode high electron mobility transistor device includes a semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas. A high electron mobility transistor device includes a gate structure extending over a top surface of a semiconductor body, biased to electrically control a two-dimensional electron gas, and including a functional layer and a gate contact in direct physical and electrical contact with each other. The gate contact is made of a layer of conductive material, and the functional layer is made of a layer of two-dimensional semiconductor material and includes a first doped portion having P-type conductivity extending over a top surface of the semiconductor body and interposed along a first axis between the semiconductor body and the gate contact. According to the embodiment of the invention, the low power consumption of the transistor in use is ensured, and the integration of the transistor into an electronic circuit in a design step is simplified.
Owner:STMICROELECTRONICS SRL
Stress transfer layer for a high electron mobility transistor
PendingUS20250324645A1Semiconductor/solid-state device detailsSolid-state devicesDevice materialPhysical chemistry
The present disclosure relates to Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) (100) i.e. a semiconductor device (100) which includes a buffer layer (104) formed on the substrate (120). An unintentionally doped (UID) Gallium Nitride (GaN) channel layer (102) is positioned on the buffer layer (104). A barrier layer (106) is formed on the UID channel layer (102) to enable formation of two-dimensional electron gas (2DEG) at interface between UID GaN channel layer (102) and barrier layer (106). A stress transfer layer (116) having tunable intrinsic compressive mechanical stress is deposited on barrier layer (106) to enhance device performance and reliability. Further, the intrinsic stress in the stress transfer layer (116) is tailored to enhance performance in terms of higher threshold voltage and breakdown voltage, and reliability in terms of reduced dynamic RON under DC and switching stress and stable threshold voltage under ON and OFF state gate stress.
Owner:INDIAN INSTITUTE OF SCIENCE
Epitaxial structure of GaN HEMT (High Electron Mobility Transistor) with low specific conduction resistivity and preparation method thereof
The invention relates to an epitaxial structure of a low-specific on-resistivity GaN HEMT and a preparation method thereof, and the preparation method comprises the steps: S1, sequentially growing an initial layer, a buffer layer, a channel layer, a first insertion layer, a first barrier layer, a second insertion layer and a second barrier layer on a substrate from bottom to top, and obtaining a thick barrier epitaxial wafer; s2, preparing a hard mask layer, patterning and etching the hard mask layer, then transferring the hard mask layer to the upper surface of the thick barrier epitaxial wafer, and etching the thick barrier epitaxial wafer to the upper surface of the second insertion layer; s3, secondarily growing a p-GaN layer on the upper surface of the second insertion layer in the gate region; and S4, removing the polycrystalline GaN in a non-gate region, depositing metal on the p-GaN layer to manufacture a gate, and depositing metal on two sides of the structure to manufacture a source and a drain respectively. By selectively growing the p-GaN layer in the grid region, two-dimensional electron gas in a channel is effectively exhausted, and the carrier concentration of the region below the grid is remarkably reduced.
Owner:HUBEI JIUFENGSHAN LAB
Enhanced gallium nitride high electron mobility transistor and preparation method thereof
The invention provides an enhanced gallium nitride high-electron-mobility transistor. The enhanced gallium nitride high-electron-mobility transistor comprises a substrate; the first epitaxial structure is formed on the substrate, and the first epitaxial structure comprises a channel layer and a barrier layer formed on the channel layer; the passivation layer is formed on the first epitaxial structure; the grid electrode comprises a groove, and the groove penetrates through the passivation layer and the barrier layer and extends into the channel layer; the second epitaxial structure part covers the bottom and the side wall of the groove and the upper surface of the passivation layer on the left side and the right side of the top of the groove; and a gate electrode formed on the second epitaxial structure portion. The groove gate enhanced MIS-HEMT device has the beneficial effects that the uniformity, the process repeatability, the robustness and the reliability of the threshold voltage of the groove gate enhanced MIS-HEMT device are improved.
Owner:SHENZHEN GALLIUM SEMICON TECH CO LTD
Gallium nitride high-electron-mobility transistor integrated with Schottky diode and preparation method of gallium nitride high-electron-mobility transistor
The invention belongs to the field of semiconductor devices, provides a gallium nitride high-electron-mobility transistor integrated with a Schottky diode and a preparation method of the gallium nitride high-electron-mobility transistor, and aims to solve the problem that a conventional gallium nitride high-electron-mobility transistor (GaN HEMT) lacks a body diode. According to the invention, monolithic integration of the SBD and the GaN HEMT is realized through structural design, a low-impedance path is provided for reverse current, and the integration mode not only retains the original high performance characteristic of a GaN device, but also additionally endows the GaN device with reverse conduction and reverse recovery capabilities; moreover, through the structural design, the SBD can be synchronously completed on the basis of the existing GaN HEMT process, a special process or new equipment is not needed, and the cost is effectively controlled while the performance improvement is ensured; compared with an external interconnection diode scheme, parasitic inductance caused by lead bonding is eliminated, the voltage overshoot and ringing phenomena in the switching process are remarkably reduced, high-frequency switching application is facilitated, and switching loss can be greatly reduced.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA
Electrostatic discharge protection device
PendingUS20260068329A1Solid-state devicesEmergency protective circuit arrangementsElectrical connectionElectrostatic discharge protection
An ESD (electrostatic discharge) protection device includes a first enhancement mode HEMT (high-electron-mobility transistor) electrically connected between a protected node and a grounded node, and an RC network electrically connected between the protected node and the grounded node, The time constant of the RC network is set such that a gate of the first enhancement mode HEMT is pulled up to turn on the first enhancement mode HEMT for positive transient pulses at the protected node having a rise time less than the time constant of the RC network. The first enhancement mode HEMT is configured to shunt the protected node to the grounded node when on.
Owner:INFINEON TECH AUSTRIA AG
Electrostatic discharge protection device
PendingCN121646000AEmergency protective circuit arrangementsElectrical connectionElectrostatic discharge protection
An ESD (electrostatic discharge) protection device includes a first enhanced HEMT (High Electron Mobility Transistor) electrically connected between a protected node and a ground node, and an RC network electrically connected between the protected node and the ground node. A time constant of the RC network is set such that a gate of the first enhancement mode HEMT is pulled up to turn on the first enhancement mode HEMT for a positive transient pulse at the protected node having a rise time less than the time constant of the RC network. The first enhanced HEMT is configured to shunt a protected node to a ground node when turned on.
Owner:INFINEON TECH AUSTRIA AG
GaN HEMT WITH LOW THRESHOLD VOLTAGE SHIFT USING A HOLE INJECTOR / COLLECTOR
This invention pertains to the design of a novel Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) with multiple metal contacts to a single contiguous p-GaN island. The invention encompasses various embodiments which introduce innovative mechanisms for threshold voltage (Vth) control through hole injection and removal.
Owner:EFFICIENT POWER CONVERSION CORP
Package of GaN / SiC Cascode Power Device
PendingUS20260129949A1Semiconductor/solid-state device detailsSolid-state devicesCascodeField effect
A GaN / SiC cascode power device is formed with first and second transistor groups. The first transistor group has one or more low-voltage normally-off GaN high-electron-mobility transistors. The second group has one or more high-voltage normally-on SiC junction-field-effect transistors. A backbone layer mechanically supports respective transistors in the two transistor groups and provides electrical connectivity among the respective transistors. The backbone layer is formed by embedding a network of conductive traces on or within an insulating rigid layer. The respective transistors are mounted on the backbone layer and electrically connected via the network of conductive traces. Advantageously, bonding wires are absent in providing intra-connection between the two transistor groups. Undesirable interconnection inductances are considerably reduced such that switching loss and switching oscillation, both overstressing the power device during a switching process, are suppressed.
Owner:THE HONG KONG UNIV OF SCI & TECH
Enhanced GaN HEMT device based on composite gate and gate terminal extension and preparation method thereof
The invention discloses an enhanced GaN HEMT (High Electron Mobility Transistor) device based on a composite gate and gate terminal expansion and a preparation method thereof, the p-InGaN and p-GaN / p + GaN layer heterojunction polarization effect in the composite gate structure of the enhanced GaN HEMT device can generate two-dimensional hole gas on an interface, and more holes are injected into a channel to be compounded with electrons when high leakage voltage is turned off; the electron concentration of the lower channel layer near the gate is reduced, so that electron capture of the buffer layer on the channel layer is inhibited, the dynamic performance of the device is improved, the reliability of the device is enhanced, the gate terminal expansion structure is utilized to expand the composite gate structure, the off-state electric field distribution of the device is optimized, and the reliability of the device is improved. The electric field peak value of the edge of the gate field plate can be redistributed and weakened, the current collapse effect is effectively restrained, and the preparation method of the device is simple in process and low in cost. According to the scheme, the gate stability and the dynamic performance of the device can be improved, and a reliable device basis is provided for a GaN power system with higher frequency, higher efficiency and higher power density.
Owner:NANJING UNIV OF SCI & TECH
Semiconductor device with first type and second type unit cells
A semiconductor device including: a plurality of unit cells arranged side-by-side across a top surface of the semiconductor device, and where the plurality of unit cells are of a first type or a second type, each unit cell of the first type includes a first electrode, a second electrode, and a third electrode formed at the top surface of the semiconductor device. The second electrode is arranged to enclose the first electrode. Each of the first and second electrodes are arranged to enclose the third electrode. The unit cells of the first type form high electron mobility transistor (HEMT) cells, and the unit cells of the second type form Schottky Barrier Diode (SBD) cells.
Owner:HUAWEI DIGITAL POWER TECH CO LTD
Epitaxial structure of gallium nitride HEMT device, gallium nitride HEMT device and preparation method thereof
The invention provides an epitaxial structure of a gallium nitride HEMT (High Electron Mobility Transistor) device. An in-situ nitride layer; a first high carbon concentration layer, wherein the carbon concentration of the first high carbon concentration layer is greater than 1018 cm <-3 >; a low-carbon-concentration channel layer, wherein the carbon concentration of the low-carbon-concentration channel layer is less than 1018 cm <-3 >; and a barrier layer. According to the embodiment of the invention, the existence of the in-situ nitride layer can prevent the dislocation of the bottom layer of the epitaxial structure from continuously extending upwards, and also can promote the turning annihilation of the dislocation. The channel layer is grown after the smooth surface is formed through combination, so that the smooth surface of the epitaxial structure can be obtained without a very thick channel layer, the interface quality of a key layer is further improved, and the performance and the reliability of a gallium nitride high-electron-mobility transistor device manufactured on the basis of the epitaxial structure are further improved.
Owner:SHENZHEN GALLIUM SEMICON TECH CO LTD
Packaged lateral semiconductor device and method of manufacturing same
The invention relates to a packaged lateral semiconductor device and a method of manufacturing the same, where the packaged lateral semiconductor device includes a resistor connected between a device substrate and a package ground. Compared with a traditional packaging structure, the packaging device has the advantages that the adverse effect caused by the floating substrate is reduced, the leakage current of the substrate is reduced, and the breakdown voltage is improved. In addition, by selecting a proper resistance value, the leakage current and the breakdown voltage of the device substrate can be controlled. The device comprises a high-voltage transverse device, such as a GaN or GaAs-based high electron mobility transistor (HEMT), and the packaging mode can realize high breakdown voltage and has good dynamic performance.
Owner:苏州量芯微电子有限公司
A composite channel structure high electron mobility transistor and a method for manufacturing the same
The application discloses a composite channel structure high electron mobility transistor and a preparation method thereof, and the transistor comprises a semi-insulating InP substrate, an undoped InAlAs buffer layer, an InP auxiliary channel, a first undoped In 0.22 Ga 0.78 As auxiliary channel, an undoped In 0.7 Ga 0.3 As main channel, a second undoped In 0.22 Ga 0.78 As auxiliary channel, an undoped InAlAs isolation layer, a delta-doping layer, an undoped InAlAs barrier layer, an n + InGaAs source cap layer, an n + InGaAs drain cap layer, a source electrode, a drain electrode, a passivation layer and a gate electrode. The application can improve the breakdown voltage of the InP-based HEMT, maintain the output characteristics and cutoff frequency of the high In-component channel, improve the stability of transistor uniformity and repeatability, and meet the application requirements of the InP-based electronic device in the low-power low-noise and digital circuit field.
Owner:XIDIAN UNIV
Manufacturing method of gallium nitride HEMT device
The invention discloses a gallium nitride HEMT (high electron mobility transistor) device manufacturing method, which comprises the steps that an epitaxial layer is formed on a growth substrate through an MOCVD (metal organic chemical vapor deposition) and / or HVPE (high voltage plasma etching) process, and the epitaxial layer comprises a gallium nitride channel layer and an AlGaN barrier layer; forming a dielectric layer on the AlGaN barrier layer through a deposition process; photoetching and defining regions of a source electrode and a drain electrode on the epitaxial layer and the dielectric layer, and etching and opening a source electrode contact window and a drain electrode contact window; metal pattern areas of a source electrode, a drain electrode and a grid electrode are defined on the dielectric layer and the epitaxial layer in a photoetching mode, a first Ti layer, a middle Al layer and a second Ti layer are sequentially evaporated on the metal pattern areas to form a Ti / Al / Ti metal laminated layer, synchronous annealing is carried out on the Ti / Al / Ti metal laminated layer within a first temperature range, and a second Ti layer is formed within a second temperature range; the Ti / Al / Ti metal lamination is alloyed to form a source electrode, a drain electrode and a grid electrode, and the first temperature range is 500-600 DEG C. Compared with the prior art, the process can be effectively simplified, the cost is reduced, and the wafer Vth uniformity is improved.
Owner:SINO NITRIDE SEMICON
High-linearity depletion type high electron mobility transistor and preparation method thereof
The invention relates to a high-linearity depletion type high-electron-mobility transistor and a preparation method thereof. The high-electron-mobility transistor comprises a substrate, a nucleating layer, a buffer layer, a channel layer, an intermediate layer, a barrier layer, a cap layer, a source electrode, a drain electrode, a passivation layer, a gate dielectric layer, a plurality of first gate metal and a plurality of second gate metal. The substrate, the nucleating layer, the buffer layer, the channel layer, the intermediate layer, the barrier layer and the cap layer are stacked in sequence; the source electrode and the drain electrode are respectively located at two ends of the cap layer; the passivation layer is located on the cap layer between the source electrode and the drain electrode, and a groove extending to the cap layer is formed in the gate region; the gate dielectric layer covers the passivation layer and the surface of the groove; a plurality of first gate metals are distributed in the groove at intervals along the gate width direction; the second gate metal covers the plurality of first gate metals and the gate dielectric layer between the first gate metals; the work function of the first gate metal and the work function of the second gate metal are different. The transistor reduces the nonlinear distortion of the output signal.
Owner:WUHU RES INST OF XIAN UNIV OF ELECTRONIC SCI & TECH
Method for making depletion-mode high-electron-mobility transistor
The manufacturing method of the depletion-mode high electron mobility transistor of the present invention comprises the following steps: (a) providing a semiconductor substrate comprising a channel layer and a barrier layer above the channel layer, (b) isolating a platform, (c) forming a dielectric layer above the semiconductor substrate, (d) forming a first field plate above the dielectric layer, (e) forming a second field plate above the first field plate, (f) patterning the first field plate and the second field plate to expose the position of the dielectric layer in relation to a source opening, a gate opening, and a drain opening, (g) patterning the dielectric layer to expose the position of semiconductor substrate in relation to the source opening and the drain opening, (h) patterning an ohmic contact metal layer to cover the position of the semiconductor substrate in relation to the source opening and the drain opening, and alloying the ohmic contact metal layer.
Owner:ULTRABAND TECH INC
High electron mobility transistors with hysteretic gates
Disclosed herein are high electron mobility transistors (HEMTs) with hysteretic gates, and related IC structures, devices, and techniques. In one aspect, a HEMT may include a channel structure comprising a heterojunction of a first semiconductor material and a second semiconductor material, a gate electrode material, and a gate insulator material, wherein the gate insulator material is between the channel structure and the gate electrode material and includes a hysteretic element.
Owner:INTEL CORP
A silicon-based high electron mobility transistor and its fabrication method
ActiveCN114709261BPolycrystalline material growthFrom chemically reactive gasesBoron atomElectron mobility
This invention discloses a silicon-based high electron mobility transistor and its fabrication method, relating to the field of semiconductor process technology. The silicon-based high electron mobility transistor includes: a substrate; an AlN nucleation layer, a high-resistivity buffer layer, a channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer sequentially disposed on the substrate; wherein the AlN nucleation layer includes a roughened first high-temperature AlN nucleation layer and a second high-temperature AlN nucleation layer, with the first high-temperature AlN nucleation layer disposed on the substrate. The first high-temperature AlN nucleation layer effectively blocks impurities in the substrate. Surface roughening of the first high-temperature AlN nucleation layer releases stress between the substrate and the epitaxial layer. The second high-temperature AlN nucleation layer is disposed on the roughened first high-temperature AlN nucleation layer to further release the stress accumulated in the first high-temperature AlN nucleation layer. This invention solves the technical problem in the prior art where boron atoms diffuse from the silicon substrate to the epitaxial layer, resulting in significant stress between the silicon substrate and the epitaxial layer, leading to a decrease in the crystal quality of the epitaxial layer.
Owner:JIANGXI ZHAO CHI SEMICON CO LTD
Fabricating Method of Semiconductor Device
PendingUS20260020304A1Semiconductor/solid-state device manufacturingDevice materialElectron mobility
The present disclosure provides a fabricating method of a high electron mobility transistor device, including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.
Owner:UNITED MICROELECTRONICS CORP
Low-temperature deposition of high-quality aluminum nitride films for heat spreading applications
ActiveUS12557651B2Semiconductor/solid-state device detailsSolid-state devicesLow temperature depositionMaterials science
Provided are high quality metal-nitride, such as aluminum nitride (AlN), films for heat dissipation and heat spreading applications, methods of preparing the same, and deposition of high thermal conductivity heat spreading layers for use in RF devices such as power amplifiers, high electron mobility transistors, etc. Aspects of the inventive concept can be used to enable heterogeneously integrated compound semiconductor on silicon devices or can be used in in non-RF applications as the power densities of these highly scaled microelectronic devices continues to increase.
Owner:RAYTHEON CO +2
Power microelectronic device
Title: Microelectronic Power Device The invention relates to a power device comprising: - High electron mobility transistors (T1, T2, T3) formed on an active layer (11), each transistor (T1, T2, T3) comprising a source finger (S), a drain finger (D), and a gate finger (G), - A source contact (S') common to the source fingers (S), - A drain contact (D') common to the drain fingers (D), - A gate contact (G') common to the gate fingers (G). Advantageously, at least one gate finger is not connected to the gate contact (G') and forms a Schottky contact (CS) with the active layer (11). This gate finger (CS) advantageously forms, with the adjacent drain finger (D), a Schottky diode (DS) configured to measure an operating temperature within the power device. Figure for the abstract: Fig. 2A
Owner:COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Superlattice structure, GaN HEMT device epitaxial structure and preparation method
The invention discloses a superlattice structure, a GaN HEMT (High Electron Mobility Transistor) device epitaxial structure and a preparation method, the superlattice structure is formed by periodically and alternately stacking an AlN thin layer, an Al < x > Ga < 1-x > N thin layer and an Al < y > Ga < 1-y > N thin layer, 50, y < lt >; 50; the thicknesses of the AlN thin layer, the Al < x > Ga < 1-x > N thin layer and the Al < y > Ga < 1-y > N thin layer are t1, t2 and t3 respectively, and the thickness ratio of the three layers is that (t1 + t2): t3 is more than or equal to 1: 15 and less than or equal to 1: 50. By increasing the thickness ratio of the AlN thin layer to the AlGaN thin layer, the surface roughness of the superlattice structure is obviously improved, the vertical collapse pressure of the device from inside to outside is obviously improved, the poor vertical collapse pressure in the central area in the device can be obviously improved, the overall uniformity of the vertical collapse pressure of the device is greatly improved, and the performance of the device is improved. Therefore, the electrical property of the device is obviously improved, and no edge crack defect is generated in the range.
Owner:WAFER WORKS ZHENGZHOU CORP
Field plate biasing of high electron mobility transistor
The biasing of one or more field plates of a high electron mobility transistor (a HEMT) with a non-zero voltage to thereby affect the electric field profile of the HEMT. The non-zero voltage may be a constant DC voltage, or perhaps may be a voltage that changes over time. The use of a non-zero voltage allows for greater ability to regulate and reduce the electric field occurring in the semiconductor channel region, especially at the field plate. Further, when the electric field occurring at the field plate is reduced, the overall size of the HEMT can also be reduced as compared to applying a zero voltage to the field plate. Alternatively, or in addition, applying a non-zero voltage to the field plate allows the voltage levels handled by the HEMT to be increased as compared to simply grounding the field plate.
Owner:GAN SYST INC
High electron mobility transistor and manufacturing method
The invention relates to the technical field of semiconductor devices, and provides a high-electron-mobility transistor and a manufacturing method, and the high-electron-mobility transistor comprises a substrate structure; the source electrode and the drain electrode are arranged on the substrate structure; the P-type gallium nitride layer is arranged on the substrate structure; the N-type gallium nitride layer is arranged on the P-type gallium nitride layer, and the N-type gallium nitride layer is provided with a first opening part located at the edge part; and the charge release layer is arranged on the P-type gallium nitride layer and is positioned in the first opening part. The N-type gallium nitride layer is arranged on the P-type gallium nitride layer to form a PN junction to replace a Schottky junction, so that the problem that the reliability of the gate is reduced due to the degeneration of the Schottky junction is fundamentally avoided, the reliability of the gate structure is improved, the charge release layer can provide a path for releasing trapped charges more quickly compared with the N-type gallium nitride layer, and the reliability of the gate structure is improved. Trapped charges in the P-type gallium nitride layer are quickly released, the influence of the trapped charges on threshold voltage is reduced, and the overall stability of the transistor is improved.
Owner:INNOSCIENCE (ZHUHAI) TECH CO LTD
Induction machine
PendingUS20250357812A1Single-phase induction motor startersElectric motor controlElectric aircraftElectric machine
There is provided an induction machine (100) comprising a rotor (120); a stator (140); and a phase-shift oscillator (160). The stator comprises: a first winding (141); and a second winding (142), arranged at a first angle (101) relative to said first winding. The phase-shift oscillator comprises: a transistor (170), the transistor (170) being a high-electron mobility transistor, HEMT; and a phase-shift network (180). The first winding is connected to a first node (181) of the phase-shift network and wherein the second winding is connected to a second node (182) of the phase-shift network, wherein the phase-shift oscillator is configured to provide a first phase electric signal at the first node and a second phase electric signal at the second node, wherein a difference between the first and second phase corresponds to the first angle. There is also provided an electric aircraft propulsion system comprising the induction machine.
Owner:EPINOVATECH AB
Semiconductor device having first type unit cells and second type unit cells
The present invention relates to a semiconductor device (100) comprising: a plurality of unit cells (120a, 120b) arranged side by side across a top surface of the semiconductor device (100) wherein the plurality of unit cells (120a, 120b) have a first type (120a) or a second type (120b), each of the first type unit cells (120a) includes a first electrode (121), a second electrode (122), and a third electrode (123) formed at the top surface of the semiconductor device (100); the second electrode (122) is arranged so as to surround the first electrode (121); each of the first electrode (121) and the second electrode (122) is arranged so as to surround the third electrode (123); the first type unit cell (120a) forms a high electron mobility transistor (HEMT) cell, and the second type unit cell (120a) forms a high electron mobility transistor (HEMT) cell. The second type of unit cells (120b) form a Schottky barrier diode (SBD) cell, and the second type of unit cells (120b) form a Schottky barrier diode (SBD) cell.
Owner:HUAWEI DIGITAL POWER TECH CO LTD
HEMT (High Electron Mobility Transistor) And Method Therefor
PendingUS20260114249A1Semiconductor/solid-state device manufacturingSemiconductor devicesCarbon layerDevice material
A heterogeneous epitaxial structure formed on a SiC (silicon carbide) substrate. An intermediate layer comprising AIN is formed overlying the SiC substrate. The surface of the intermediate layer comprises AIN formed by lateral epitaxial growth. The lateral epitaxial growth merges to form the surface comprising a MELO layer (merged epitaxial lateral overgrowth). The intermediate layer includes a carbon layer underlying the MELO layer. At least one device layer comprising GaN (gallium nitride) is formed overlying the surface of the intermediate layer in which one or more semiconductor devices are formed. The carbon layer is heated to fracture portions of the intermediate layer to separate the SiC substrate from the intermediate layer. The SiC substrate is not consumed by the separation thereby allowing perpetual reuse in semiconductor wafer processing.
Owner:THINSIC INC