535 results about "High-electron-mobility transistor" patented technology

A structure includes a transistor, e.g., HEMT, with a field plate positioned laterally to a side of an active gate and including a first portion extending over the active gate. A dielectric layer isolates a lower surface of the first portion from an upper surface of the active gate. A field plate contact includes interconnect layers located directly over the active gate and electrically coupled to the first portion directly over the active gate. The field plate contact allows electrical operation of the field plate, but also acts as a thermally conductive path from the active gate through the interconnect layers to cool likely hot spots within the transistor.

The invention discloses a junction temperature testing device and method for a high-electron-mobility transistor. A current measuring module in the junction temperature testing device for the high-electron-mobility transistor is used for acquiring current flowing through a tested device; the power supply module is electrically connected with the other end of the switch module, and the power supply module and the switch module are connected in parallel with the bus capacitor; the control module is electrically connected with the control end, the driving end and the regulation and control end of the switch module, and the control module is used for providing switching signals for the control end, the driving end and the regulation and control end of the switch module so as to control the switching states of the switch protection module, the tested device and the switch module; the heating plate is used for heating a tested device; the temperature detection module is used for measuring the temperature of the detected device; and the waveform analysis module is electrically connected with the control module, the temperature detection module and the current measurement module, and is used for obtaining and forming an experimental oscillogram of the tested device at the temperature according to the temperature, the current and the conduction time of the tested device controlled by the control module.

The invention relates to the technical field of transistor structures, and provides a region activation mixed gate structure, a high electron mobility transistor and a manufacturing method, and the structure comprises a substrate structure, and a source electrode and a drain electrode which are disposed on the substrate structure. The gate depletion layer is arranged on the substrate structure and between the source electrode and the drain electrode; an activation enhancement region is formed between the activation enhancement layer and the gate depletion layer; the gate lead-out layer is arranged on the activation enhancement area and the area, not covered by the activation enhancement layer, of the gate consumption layer, and the area, making contact with the gate consumption layer, of the gate lead-out layer forms a low-leakage area. An activation enhancement region with high grid leakage is formed through an activation enhancement layer, a path for rapidly releasing trapped charges in a grid consumption layer is provided, and by adjusting the proportion of the activation enhancement region to a low leakage region, the grid performance is guaranteed while the trapped charges are rapidly released, the influence of the trapped charges is reduced, and the threshold voltage drift is improved. The switch performance and stability are improved.

There is provided a field-programmable gate array, FPGA, device (100) comprising a configurable logic block, CLB, (110) comprising a logic inverter (120) comprising a high-electron-mobility transistor, HEMT, (130), wherein the HEMT comprises: a Si substrate (384); an AlyGay-1N layer structure (380), wherein 0<y≤1; a GaN layer structure (382); and a crystal transition layer structure (386) arranged on the Si substrate. The crystal transition layer comprises: a plurality of vertical nanowire structures (388) perpendicularly arranged on the Si substrate, and an AlxGax-1N layer structure (389), wherein 0≤x<1, wherein the AlxGax-1N layer structure is arranged to vertically and laterally enclose the vertical nanowire structures. There is also provided an AI processing system comprising said FPGA device (100).

The invention provides a non-polar gallium nitride-based enhanced HEMT (High Electron Mobility Transistor) with low source-drain contact resistance, and relates to the technical field of semiconductors. Comprising an m-plane substrate, an unintentionally doped GaN buffer layer, a Fe doped GaN layer, a GaN channel layer, an AlN insertion layer and an AlGaN barrier layer which are sequentially arranged from bottom to top, the plurality of grooves are arranged in the edge areas of the two sides of the AlGaN barrier layer at intervals, penetrate through the AlGaN barrier layer and are in contact with the upper surface of the AlN insertion layer, and target GaN is arranged in each groove so as to form longitudinal AlGaN / GaN superlattice structures on the two sides; the GaN cap layer is formed on the middle region of the AlGaN barrier layer; the grid electrode is formed on the GaN cap layer; the source electrode is formed on the AlGaN / GaN superlattice structure on one side; and the drain electrode is formed on the AlGaN / GaN superlattice structure on the other side. In this way, the contact resistance is reduced without being affected by the polarization effect.

A HEMT device includes a substrate, a buffer layer, a channel layer, a barrier layer, and a dielectric layer sequentially disposed in such order in a bottom-up direction and cooperatively forming an active region; a source electrode and a drain electrode disposed oppositely on the active region; and a gate electrode including a comb structure disposed in a gate region between the source electrode and the drain electrode on the active region. The comb structure includes a comb stem portion and comb tooth portions connected to the comb stem portion. The comb tooth portions are spaced apart from each other in a gate width direction. The comb stem portion is disposed on the barrier layer and is parallel to the source electrode or the drain electrode. The comb tooth portions penetrate the dielectric layer to equal depths.

A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode on the p-type semiconductor layer, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode. Preferably, the buffer layer further includes a bottom portion having a first carbon concentration and a top portion having a second carbon concentration, in which the second carbon concentration is less than the first carbon concentration and a thickness of the bottom portion is less than a thickness of the top portion.

The embodiment of the utility model relates to an enhancement mode high electron mobility transistor device. An enhanced mode high electron mobility transistor device includes a semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas. A high electron mobility transistor device includes a gate structure extending over a top surface of a semiconductor body, biased to electrically control a two-dimensional electron gas, and including a functional layer and a gate contact in direct physical and electrical contact with each other. The gate contact is made of a layer of conductive material, and the functional layer is made of a layer of two-dimensional semiconductor material and includes a first doped portion having P-type conductivity extending over a top surface of the semiconductor body and interposed along a first axis between the semiconductor body and the gate contact. According to the embodiment of the invention, the low power consumption of the transistor in use is ensured, and the integration of the transistor into an electronic circuit in a design step is simplified.

The invention provides an enhanced GaN HEMT (High Electron Mobility Transistor) device and a preparation method thereof. The device comprises a substrate; the epitaxial structure is epitaxially grown on the substrate; the secondary epitaxial layer is epitaxially grown on the epitaxial structure; the dielectric layer is arranged on the secondary epitaxial layer; communicated groove regions are arranged in the p-GaN layer, the dielectric layer and the secondary epitaxial layer, and the p-GaN layer epitaxially grows in the groove regions from the upper surface of the epitaxial structure; the grid electrode is arranged on the p-GaN layer; and the source electrode and the drain electrode are respectively arranged at two sides of the epitaxial structure, the secondary epitaxial layer and the dielectric layer. The device has a better high-frequency dynamic characteristic; the stability and the consistency of the grid threshold voltage are improved; the crack generation risk of the epitaxial wafer is low, and the MBE-grown p-GaN does not need to be subjected to subsequent activation treatment; the gate reliability is improved, and the stability of the device is further improved.

A high electron mobility transistor includes a semiconductor structure, a stepped trench, an electrode, and a gate. The semiconductor structure includes a barrier layer and a channel layer. The barrier layer is disposed on the channel layer. A two-dimensional electron gas is formed at an interface between the channel layer and the barrier layer. The stepped trench is disposed in the semiconductor structure. The electrode is disposed in the stepped trench. The gate is disposed on the barrier layer. The stepped trench has a first width and a second width. The first width is greater than the second width.

The present disclosure relates to Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) (100) i.e. a semiconductor device (100) which includes a buffer layer (104) formed on the substrate (120). An unintentionally doped (UID) Gallium Nitride (GaN) channel layer (102) is positioned on the buffer layer (104). A barrier layer (106) is formed on the UID channel layer (102) to enable formation of two-dimensional electron gas (2DEG) at interface between UID GaN channel layer (102) and barrier layer (106). A stress transfer layer (116) having tunable intrinsic compressive mechanical stress is deposited on barrier layer (106) to enhance device performance and reliability. Further, the intrinsic stress in the stress transfer layer (116) is tailored to enhance performance in terms of higher threshold voltage and breakdown voltage, and reliability in terms of reduced dynamic RON under DC and switching stress and stable threshold voltage under ON and OFF state gate stress.

The invention relates to an epitaxial structure of a low-specific on-resistivity GaN HEMT and a preparation method thereof, and the preparation method comprises the steps: S1, sequentially growing an initial layer, a buffer layer, a channel layer, a first insertion layer, a first barrier layer, a second insertion layer and a second barrier layer on a substrate from bottom to top, and obtaining a thick barrier epitaxial wafer; s2, preparing a hard mask layer, patterning and etching the hard mask layer, then transferring the hard mask layer to the upper surface of the thick barrier epitaxial wafer, and etching the thick barrier epitaxial wafer to the upper surface of the second insertion layer; s3, secondarily growing a p-GaN layer on the upper surface of the second insertion layer in the gate region; and S4, removing the polycrystalline GaN in a non-gate region, depositing metal on the p-GaN layer to manufacture a gate, and depositing metal on two sides of the structure to manufacture a source and a drain respectively. By selectively growing the p-GaN layer in the grid region, two-dimensional electron gas in a channel is effectively exhausted, and the carrier concentration of the region below the grid is remarkably reduced.

The invention provides an enhanced gallium nitride high-electron-mobility transistor. The enhanced gallium nitride high-electron-mobility transistor comprises a substrate; the first epitaxial structure is formed on the substrate, and the first epitaxial structure comprises a channel layer and a barrier layer formed on the channel layer; the passivation layer is formed on the first epitaxial structure; the grid electrode comprises a groove, and the groove penetrates through the passivation layer and the barrier layer and extends into the channel layer; the second epitaxial structure part covers the bottom and the side wall of the groove and the upper surface of the passivation layer on the left side and the right side of the top of the groove; and a gate electrode formed on the second epitaxial structure portion. The groove gate enhanced MIS-HEMT device has the beneficial effects that the uniformity, the process repeatability, the robustness and the reliability of the threshold voltage of the groove gate enhanced MIS-HEMT device are improved.

The invention discloses a single-particle-resistant high-electron-mobility transistor which comprises a substrate layer, a buffer layer, a channel layer, a barrier layer and a gate structure layer which are arranged in a stacked mode in the second direction, and the surface, away from the buffer layer, of the channel layer is further provided with a first electrode structure and a second electrode structure. The first electrode structure and the second electrode structure are connected to the two sides of the barrier layer in the first direction respectively, and at least one buried layer is inserted into the buffer layer; wherein a polarization effect and two-dimensional electron gas can be generated between the buffer layer and the channel layer, and each buried layer is made of a p-type GaN material. According to the anti-single-particle high-electron-mobility transistor, the anti-single-particle capability of a device is improved under the condition that the original characteristics of the device are not changed.

A high electron mobility transistor (HEMT) device includes a substrate, a channel layer, a source, a drain, a buffer layer, and a plurality of amorphous regions. The channel layer is located above the substrate. The source is located on the channel layer. The drain is located on the channel layer. The buffer layer is located between the substrate and the channel layer. The plurality of amorphous regions are located in the buffer layer below the source and the drain.

The invention belongs to the field of semiconductor devices, provides a gallium nitride high-electron-mobility transistor integrated with a Schottky diode and a preparation method of the gallium nitride high-electron-mobility transistor, and aims to solve the problem that a conventional gallium nitride high-electron-mobility transistor (GaN HEMT) lacks a body diode. According to the invention, monolithic integration of the SBD and the GaN HEMT is realized through structural design, a low-impedance path is provided for reverse current, and the integration mode not only retains the original high performance characteristic of a GaN device, but also additionally endows the GaN device with reverse conduction and reverse recovery capabilities; moreover, through the structural design, the SBD can be synchronously completed on the basis of the existing GaN HEMT process, a special process or new equipment is not needed, and the cost is effectively controlled while the performance improvement is ensured; compared with an external interconnection diode scheme, parasitic inductance caused by lead bonding is eliminated, the voltage overshoot and ringing phenomena in the switching process are remarkably reduced, high-frequency switching application is facilitated, and switching loss can be greatly reduced.

An ESD (electrostatic discharge) protection device includes a first enhancement mode HEMT (high-electron-mobility transistor) electrically connected between a protected node and a grounded node, and an RC network electrically connected between the protected node and the grounded node, The time constant of the RC network is set such that a gate of the first enhancement mode HEMT is pulled up to turn on the first enhancement mode HEMT for positive transient pulses at the protected node having a rise time less than the time constant of the RC network. The first enhancement mode HEMT is configured to shunt the protected node to the grounded node when on.

A High-Electron-Mobility-Transistor that may include a substrate with a buffer layer formed on the substrate. A recess formed in the buffer layer. A barrier layer formed on the buffer layer. A gate recess formed in the barrier layer, the gate recess overlaps the recess in the buffer layer. A drain terminal formed at a first side of the barrier layer. A source terminal formed at a second side of the barrier layer. An isolation structure formed within the gate recess proximate the drain terminal. A doped structure formed adjacent to the isolation structure within the gate recess proximate the source terminal. A gate terminal formed on the doped structure.

The epitaxial structure comprises a substrate layer, a polymerization layer, a high-resistance layer, a middle layer, a channel layer and a barrier layer which are sequentially arranged from bottom to top, the polymerization layer comprises a combination of a buffer layer and a transition layer, the channel layer is provided with a two-dimensional electron conducting channel, and the high-resistance layer is arranged between the high-resistance layer and the middle layer. The material composition of the barrier layer is ALInGaN, and the channel layer is formed at the interface of the barrier layer and the intermediate layer. According to the epitaxial structure disclosed in the technical scheme, AlInGaN is adopted as a barrier layer material to replace a traditional AlGaN barrier layer, the lattice constant of the barrier layer can be adjusted by introducing the In element, lattice mismatch between the barrier layer and a GaN channel layer is reduced, and meanwhile high polarization intensity is kept, so that the two-dimensional electron gas concentration is improved, and meanwhile the performance of the epitaxial structure is improved. The interface defects are reduced, and the electron mobility is improved.

An ESD (electrostatic discharge) protection device includes a first enhanced HEMT (High Electron Mobility Transistor) electrically connected between a protected node and a ground node, and an RC network electrically connected between the protected node and the ground node. A time constant of the RC network is set such that a gate of the first enhancement mode HEMT is pulled up to turn on the first enhancement mode HEMT for a positive transient pulse at the protected node having a rise time less than the time constant of the RC network. The first enhanced HEMT is configured to shunt a protected node to a ground node when turned on.

This invention pertains to the design of a novel Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) with multiple metal contacts to a single contiguous p-GaN island. The invention encompasses various embodiments which introduce innovative mechanisms for threshold voltage (Vth) control through hole injection and removal.

A GaN / SiC cascode power device is formed with first and second transistor groups. The first transistor group has one or more low-voltage normally-off GaN high-electron-mobility transistors. The second group has one or more high-voltage normally-on SiC junction-field-effect transistors. A backbone layer mechanically supports respective transistors in the two transistor groups and provides electrical connectivity among the respective transistors. The backbone layer is formed by embedding a network of conductive traces on or within an insulating rigid layer. The respective transistors are mounted on the backbone layer and electrically connected via the network of conductive traces. Advantageously, bonding wires are absent in providing intra-connection between the two transistor groups. Undesirable interconnection inductances are considerably reduced such that switching loss and switching oscillation, both overstressing the power device during a switching process, are suppressed.

The invention discloses an enhanced GaN HEMT (High Electron Mobility Transistor) device based on a composite gate and gate terminal expansion and a preparation method thereof, the p-InGaN and p-GaN / p + GaN layer heterojunction polarization effect in the composite gate structure of the enhanced GaN HEMT device can generate two-dimensional hole gas on an interface, and more holes are injected into a channel to be compounded with electrons when high leakage voltage is turned off; the electron concentration of the lower channel layer near the gate is reduced, so that electron capture of the buffer layer on the channel layer is inhibited, the dynamic performance of the device is improved, the reliability of the device is enhanced, the gate terminal expansion structure is utilized to expand the composite gate structure, the off-state electric field distribution of the device is optimized, and the reliability of the device is improved. The electric field peak value of the edge of the gate field plate can be redistributed and weakened, the current collapse effect is effectively restrained, and the preparation method of the device is simple in process and low in cost. According to the scheme, the gate stability and the dynamic performance of the device can be improved, and a reliable device basis is provided for a GaN power system with higher frequency, higher efficiency and higher power density.

A semiconductor device including: a plurality of unit cells arranged side-by-side across a top surface of the semiconductor device, and where the plurality of unit cells are of a first type or a second type, each unit cell of the first type includes a first electrode, a second electrode, and a third electrode formed at the top surface of the semiconductor device. The second electrode is arranged to enclose the first electrode. Each of the first and second electrodes are arranged to enclose the third electrode. The unit cells of the first type form high electron mobility transistor (HEMT) cells, and the unit cells of the second type form Schottky Barrier Diode (SBD) cells.

The invention provides an epitaxial structure of a gallium nitride HEMT (High Electron Mobility Transistor) device. An in-situ nitride layer; a first high carbon concentration layer, wherein the carbon concentration of the first high carbon concentration layer is greater than 1018 cm <-3 >; a low-carbon-concentration channel layer, wherein the carbon concentration of the low-carbon-concentration channel layer is less than 1018 cm <-3 >; and a barrier layer. According to the embodiment of the invention, the existence of the in-situ nitride layer can prevent the dislocation of the bottom layer of the epitaxial structure from continuously extending upwards, and also can promote the turning annihilation of the dislocation. The channel layer is grown after the smooth surface is formed through combination, so that the smooth surface of the epitaxial structure can be obtained without a very thick channel layer, the interface quality of a key layer is further improved, and the performance and the reliability of a gallium nitride high-electron-mobility transistor device manufactured on the basis of the epitaxial structure are further improved.

The invention relates to a packaged lateral semiconductor device and a method of manufacturing the same, where the packaged lateral semiconductor device includes a resistor connected between a device substrate and a package ground. Compared with a traditional packaging structure, the packaging device has the advantages that the adverse effect caused by the floating substrate is reduced, the leakage current of the substrate is reduced, and the breakdown voltage is improved. In addition, by selecting a proper resistance value, the leakage current and the breakdown voltage of the device substrate can be controlled. The device comprises a high-voltage transverse device, such as a GaN or GaAs-based high electron mobility transistor (HEMT), and the packaging mode can realize high breakdown voltage and has good dynamic performance.

The application discloses a composite channel structure high electron mobility transistor and a preparation method thereof, and the transistor comprises a semi-insulating InP substrate, an undoped InAlAs buffer layer, an InP auxiliary channel, a first undoped In 0.22 Ga 0.78 As auxiliary channel, an undoped In 0.7 Ga 0.3 As main channel, a second undoped In 0.22 Ga 0.78 As auxiliary channel, an undoped InAlAs isolation layer, a delta-doping layer, an undoped InAlAs barrier layer, an n + InGaAs source cap layer, an n + InGaAs drain cap layer, a source electrode, a drain electrode, a passivation layer and a gate electrode. The application can improve the breakdown voltage of the InP-based HEMT, maintain the output characteristics and cutoff frequency of the high In-component channel, improve the stability of transistor uniformity and repeatability, and meet the application requirements of the InP-based electronic device in the low-power low-noise and digital circuit field.

A semiconductor device (500), such as a GaN-based high electron mobility transistor, includes a hybrid drain contact structure over a channel layer (510) and a barrier layer (520). The hybrid drain contact structure includes a first drain contact (550) electrically coupled to the channel layer (510), a semiconductor layer (552) over the barrier layer (520) and including a first semiconductor portion and a second semiconductor portion, and a second drain contact on the semiconductor layer (552) and electrically coupled to the first drain contact (550). The second drain contact includes a first metal portion (554) and a second metal portion (556). The first metal portion (554) and the first semiconductor portion form a first junction (570) having a first energy barrier height. The second metal portion (556) and the second semiconductor portion form a second junction (574) having a second energy barrier height lower than the first energy barrier height.

The invention discloses a gallium nitride HEMT (high electron mobility transistor) device manufacturing method, which comprises the steps that an epitaxial layer is formed on a growth substrate through an MOCVD (metal organic chemical vapor deposition) and / or HVPE (high voltage plasma etching) process, and the epitaxial layer comprises a gallium nitride channel layer and an AlGaN barrier layer; forming a dielectric layer on the AlGaN barrier layer through a deposition process; photoetching and defining regions of a source electrode and a drain electrode on the epitaxial layer and the dielectric layer, and etching and opening a source electrode contact window and a drain electrode contact window; metal pattern areas of a source electrode, a drain electrode and a grid electrode are defined on the dielectric layer and the epitaxial layer in a photoetching mode, a first Ti layer, a middle Al layer and a second Ti layer are sequentially evaporated on the metal pattern areas to form a Ti / Al / Ti metal laminated layer, synchronous annealing is carried out on the Ti / Al / Ti metal laminated layer within a first temperature range, and a second Ti layer is formed within a second temperature range; the Ti / Al / Ti metal lamination is alloyed to form a source electrode, a drain electrode and a grid electrode, and the first temperature range is 500-600 DEG C. Compared with the prior art, the process can be effectively simplified, the cost is reduced, and the wafer Vth uniformity is improved.

The invention discloses a gallium nitride high-electron-mobility transistor and a manufacturing method thereof. The gallium nitride high-electron-mobility transistor comprises a transistor structure, a heat dissipation structure and a conductive structure, the transistor structure comprises a composite semiconductor layer and an electrode unit. The composite semiconductor layer has a gallium nitride layer portion. The heat dissipation structure comprises a heat dissipation insulating layer and a heat dissipation metal plate arranged on the side face, away from the composite semiconductor layer, of the heat dissipation insulating layer. The heat dissipation metal plate has a molybdenum substrate portion. The heat dissipation structure and the transistor structure jointly define at least one channel which is formed on one side face, adjacent to the heat dissipation metal plate, of the heat dissipation insulating layer and penetrates through the electrode unit. The conductive structure is arranged in the channel, and two opposite ends of the conductive structure are electrically connected with the heat dissipation metal plate and the electrode unit respectively. By arranging the transistor structure on the molybdenum substrate part of which the heat conduction coefficient is higher than that of a sapphire material, the heat energy generated during the operation of the transistor structure can be quickly radiated to the external environment through the molybdenum substrate part, thereby achieving the effect of improving the heat dissipation performance.