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219 results about "High-electron-mobility transistor" patented technology
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A high-electron-mobility transistor (HEMT), also known as heterostructure FET (HFET) or modulation-doped FET (MODFET), is a field-effect transistor incorporating a junction between two materials with different band gaps (i.e. a heterojunction) as the channel instead of a doped region (as is generally the case for MOSFET). A commonly used material combination is GaAs with AlGaAs, though there is wide variation, dependent on the application of the device. Devices incorporating more indium generally show better high-frequency performance, while in recent years, gallium nitride HEMTs have attracted attention due to their high-power performance. Like other FETs, HEMTs are used in integrated circuits as digital on-off switches. FETs can also be used as amplifiers for large amounts of current using a small voltage as a control signal. Both of these uses are made possible by the FET’s unique current-voltage characteristics. HEMT transistors are able to operate at higher frequencies than ordinary transistors, up to millimeter wave frequencies, and are used in high-frequency products such as cell phones, satellite television receivers, voltage converters, and radar equipment. They are widely used in satellite receivers, in low power amplifiers and in the defense industry.
High electron mobility transistor device and method of making the same
A HEMT device includes a substrate, a buffer layer, a channel layer, a barrier layer, and a dielectric layer sequentially disposed in such order in a bottom-up direction and cooperatively forming an active region; a source electrode and a drain electrode disposed oppositely on the active region; and a gate electrode including a comb structure disposed in a gate region between the source electrode and the drain electrode on the active region. The comb structure includes a comb stem portion and comb tooth portions connected to the comb stem portion. The comb tooth portions are spaced apart from each other in a gate width direction. The comb stem portion is disposed on the barrier layer and is parallel to the source electrode or the drain electrode. The comb tooth portions penetrate the dielectric layer to equal depths.
Owner:XIAMEN SANAN INTEGRATED CIRCUIT CO LTD
Enhanced mode high electron mobility transistor device
The embodiment of the utility model relates to an enhancement mode high electron mobility transistor device. An enhanced mode high electron mobility transistor device includes a semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas. A high electron mobility transistor device includes a gate structure extending over a top surface of a semiconductor body, biased to electrically control a two-dimensional electron gas, and including a functional layer and a gate contact in direct physical and electrical contact with each other. The gate contact is made of a layer of conductive material, and the functional layer is made of a layer of two-dimensional semiconductor material and includes a first doped portion having P-type conductivity extending over a top surface of the semiconductor body and interposed along a first axis between the semiconductor body and the gate contact. According to the embodiment of the invention, the low power consumption of the transistor in use is ensured, and the integration of the transistor into an electronic circuit in a design step is simplified.
Owner:STMICROELECTRONICS SRL
Enhanced gallium nitride high electron mobility transistor and preparation method thereof
The invention provides an enhanced gallium nitride high-electron-mobility transistor. The enhanced gallium nitride high-electron-mobility transistor comprises a substrate; the first epitaxial structure is formed on the substrate, and the first epitaxial structure comprises a channel layer and a barrier layer formed on the channel layer; the passivation layer is formed on the first epitaxial structure; the grid electrode comprises a groove, and the groove penetrates through the passivation layer and the barrier layer and extends into the channel layer; the second epitaxial structure part covers the bottom and the side wall of the groove and the upper surface of the passivation layer on the left side and the right side of the top of the groove; and a gate electrode formed on the second epitaxial structure portion. The groove gate enhanced MIS-HEMT device has the beneficial effects that the uniformity, the process repeatability, the robustness and the reliability of the threshold voltage of the groove gate enhanced MIS-HEMT device are improved.
Owner:SHENZHEN GALLIUM SEMICON TECH CO LTD
Electrostatic discharge protection device
PendingUS20260068329A1Solid-state devicesEmergency protective circuit arrangementsElectrical connectionElectrostatic discharge protection
An ESD (electrostatic discharge) protection device includes a first enhancement mode HEMT (high-electron-mobility transistor) electrically connected between a protected node and a grounded node, and an RC network electrically connected between the protected node and the grounded node, The time constant of the RC network is set such that a gate of the first enhancement mode HEMT is pulled up to turn on the first enhancement mode HEMT for positive transient pulses at the protected node having a rise time less than the time constant of the RC network. The first enhancement mode HEMT is configured to shunt the protected node to the grounded node when on.
Owner:INFINEON TECH AUSTRIA AG
Electrostatic discharge protection device
PendingCN121646000AEmergency protective circuit arrangementsElectrical connectionElectrostatic discharge protection
An ESD (electrostatic discharge) protection device includes a first enhanced HEMT (High Electron Mobility Transistor) electrically connected between a protected node and a ground node, and an RC network electrically connected between the protected node and the ground node. A time constant of the RC network is set such that a gate of the first enhancement mode HEMT is pulled up to turn on the first enhancement mode HEMT for a positive transient pulse at the protected node having a rise time less than the time constant of the RC network. The first enhanced HEMT is configured to shunt a protected node to a ground node when turned on.
Owner:INFINEON TECH AUSTRIA AG
Package of GaN / SiC Cascode Power Device
PendingUS20260129949A1Semiconductor/solid-state device detailsSolid-state devicesCascodeField effect
A GaN / SiC cascode power device is formed with first and second transistor groups. The first transistor group has one or more low-voltage normally-off GaN high-electron-mobility transistors. The second group has one or more high-voltage normally-on SiC junction-field-effect transistors. A backbone layer mechanically supports respective transistors in the two transistor groups and provides electrical connectivity among the respective transistors. The backbone layer is formed by embedding a network of conductive traces on or within an insulating rigid layer. The respective transistors are mounted on the backbone layer and electrically connected via the network of conductive traces. Advantageously, bonding wires are absent in providing intra-connection between the two transistor groups. Undesirable interconnection inductances are considerably reduced such that switching loss and switching oscillation, both overstressing the power device during a switching process, are suppressed.
Owner:THE HONG KONG UNIV OF SCI & TECH
Enhanced GaN HEMT device based on composite gate and gate terminal extension and preparation method thereof
The invention discloses an enhanced GaN HEMT (High Electron Mobility Transistor) device based on a composite gate and gate terminal expansion and a preparation method thereof, the p-InGaN and p-GaN / p + GaN layer heterojunction polarization effect in the composite gate structure of the enhanced GaN HEMT device can generate two-dimensional hole gas on an interface, and more holes are injected into a channel to be compounded with electrons when high leakage voltage is turned off; the electron concentration of the lower channel layer near the gate is reduced, so that electron capture of the buffer layer on the channel layer is inhibited, the dynamic performance of the device is improved, the reliability of the device is enhanced, the gate terminal expansion structure is utilized to expand the composite gate structure, the off-state electric field distribution of the device is optimized, and the reliability of the device is improved. The electric field peak value of the edge of the gate field plate can be redistributed and weakened, the current collapse effect is effectively restrained, and the preparation method of the device is simple in process and low in cost. According to the scheme, the gate stability and the dynamic performance of the device can be improved, and a reliable device basis is provided for a GaN power system with higher frequency, higher efficiency and higher power density.
Owner:NANJING UNIV OF SCI & TECH
Epitaxial structure of gallium nitride HEMT device, gallium nitride HEMT device and preparation method thereof
The invention provides an epitaxial structure of a gallium nitride HEMT (High Electron Mobility Transistor) device. An in-situ nitride layer; a first high carbon concentration layer, wherein the carbon concentration of the first high carbon concentration layer is greater than 1018 cm <-3 >; a low-carbon-concentration channel layer, wherein the carbon concentration of the low-carbon-concentration channel layer is less than 1018 cm <-3 >; and a barrier layer. According to the embodiment of the invention, the existence of the in-situ nitride layer can prevent the dislocation of the bottom layer of the epitaxial structure from continuously extending upwards, and also can promote the turning annihilation of the dislocation. The channel layer is grown after the smooth surface is formed through combination, so that the smooth surface of the epitaxial structure can be obtained without a very thick channel layer, the interface quality of a key layer is further improved, and the performance and the reliability of a gallium nitride high-electron-mobility transistor device manufactured on the basis of the epitaxial structure are further improved.
Owner:SHENZHEN GALLIUM SEMICON TECH CO LTD
A composite channel structure high electron mobility transistor and a method for manufacturing the same
The application discloses a composite channel structure high electron mobility transistor and a preparation method thereof, and the transistor comprises a semi-insulating InP substrate, an undoped InAlAs buffer layer, an InP auxiliary channel, a first undoped In 0.22 Ga 0.78 As auxiliary channel, an undoped In 0.7 Ga 0.3 As main channel, a second undoped In 0.22 Ga 0.78 As auxiliary channel, an undoped InAlAs isolation layer, a delta-doping layer, an undoped InAlAs barrier layer, an n + InGaAs source cap layer, an n + InGaAs drain cap layer, a source electrode, a drain electrode, a passivation layer and a gate electrode. The application can improve the breakdown voltage of the InP-based HEMT, maintain the output characteristics and cutoff frequency of the high In-component channel, improve the stability of transistor uniformity and repeatability, and meet the application requirements of the InP-based electronic device in the low-power low-noise and digital circuit field.
Owner:XIDIAN UNIV
Manufacturing method of gallium nitride HEMT device
The invention discloses a gallium nitride HEMT (high electron mobility transistor) device manufacturing method, which comprises the steps that an epitaxial layer is formed on a growth substrate through an MOCVD (metal organic chemical vapor deposition) and / or HVPE (high voltage plasma etching) process, and the epitaxial layer comprises a gallium nitride channel layer and an AlGaN barrier layer; forming a dielectric layer on the AlGaN barrier layer through a deposition process; photoetching and defining regions of a source electrode and a drain electrode on the epitaxial layer and the dielectric layer, and etching and opening a source electrode contact window and a drain electrode contact window; metal pattern areas of a source electrode, a drain electrode and a grid electrode are defined on the dielectric layer and the epitaxial layer in a photoetching mode, a first Ti layer, a middle Al layer and a second Ti layer are sequentially evaporated on the metal pattern areas to form a Ti / Al / Ti metal laminated layer, synchronous annealing is carried out on the Ti / Al / Ti metal laminated layer within a first temperature range, and a second Ti layer is formed within a second temperature range; the Ti / Al / Ti metal lamination is alloyed to form a source electrode, a drain electrode and a grid electrode, and the first temperature range is 500-600 DEG C. Compared with the prior art, the process can be effectively simplified, the cost is reduced, and the wafer Vth uniformity is improved.
Owner:SINO NITRIDE SEMICON
High-linearity depletion type high electron mobility transistor and preparation method thereof
The invention relates to a high-linearity depletion type high-electron-mobility transistor and a preparation method thereof. The high-electron-mobility transistor comprises a substrate, a nucleating layer, a buffer layer, a channel layer, an intermediate layer, a barrier layer, a cap layer, a source electrode, a drain electrode, a passivation layer, a gate dielectric layer, a plurality of first gate metal and a plurality of second gate metal. The substrate, the nucleating layer, the buffer layer, the channel layer, the intermediate layer, the barrier layer and the cap layer are stacked in sequence; the source electrode and the drain electrode are respectively located at two ends of the cap layer; the passivation layer is located on the cap layer between the source electrode and the drain electrode, and a groove extending to the cap layer is formed in the gate region; the gate dielectric layer covers the passivation layer and the surface of the groove; a plurality of first gate metals are distributed in the groove at intervals along the gate width direction; the second gate metal covers the plurality of first gate metals and the gate dielectric layer between the first gate metals; the work function of the first gate metal and the work function of the second gate metal are different. The transistor reduces the nonlinear distortion of the output signal.
Owner:WUHU RES INST OF XIAN UNIV OF ELECTRONIC SCI & TECH
Fabricating Method of Semiconductor Device
PendingUS20260020304A1Semiconductor/solid-state device manufacturingDevice materialElectron mobility
The present disclosure provides a fabricating method of a high electron mobility transistor device, including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.
Owner:UNITED MICROELECTRONICS CORP
Low-temperature deposition of high-quality aluminum nitride films for heat spreading applications
ActiveUS12557651B2Semiconductor/solid-state device detailsSolid-state devicesLow temperature depositionMaterials science
Provided are high quality metal-nitride, such as aluminum nitride (AlN), films for heat dissipation and heat spreading applications, methods of preparing the same, and deposition of high thermal conductivity heat spreading layers for use in RF devices such as power amplifiers, high electron mobility transistors, etc. Aspects of the inventive concept can be used to enable heterogeneously integrated compound semiconductor on silicon devices or can be used in in non-RF applications as the power densities of these highly scaled microelectronic devices continues to increase.
Owner:RAYTHEON CO +2
Power microelectronic device
Title: Microelectronic Power Device The invention relates to a power device comprising: - High electron mobility transistors (T1, T2, T3) formed on an active layer (11), each transistor (T1, T2, T3) comprising a source finger (S), a drain finger (D), and a gate finger (G), - A source contact (S') common to the source fingers (S), - A drain contact (D') common to the drain fingers (D), - A gate contact (G') common to the gate fingers (G). Advantageously, at least one gate finger is not connected to the gate contact (G') and forms a Schottky contact (CS) with the active layer (11). This gate finger (CS) advantageously forms, with the adjacent drain finger (D), a Schottky diode (DS) configured to measure an operating temperature within the power device. Figure for the abstract: Fig. 2A
Owner:COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Field plate biasing of high electron mobility transistor
The biasing of one or more field plates of a high electron mobility transistor (a HEMT) with a non-zero voltage to thereby affect the electric field profile of the HEMT. The non-zero voltage may be a constant DC voltage, or perhaps may be a voltage that changes over time. The use of a non-zero voltage allows for greater ability to regulate and reduce the electric field occurring in the semiconductor channel region, especially at the field plate. Further, when the electric field occurring at the field plate is reduced, the overall size of the HEMT can also be reduced as compared to applying a zero voltage to the field plate. Alternatively, or in addition, applying a non-zero voltage to the field plate allows the voltage levels handled by the HEMT to be increased as compared to simply grounding the field plate.
Owner:GAN SYST INC
High electron mobility transistor and manufacturing method
The invention relates to the technical field of semiconductor devices, and provides a high-electron-mobility transistor and a manufacturing method, and the high-electron-mobility transistor comprises a substrate structure; the source electrode and the drain electrode are arranged on the substrate structure; the P-type gallium nitride layer is arranged on the substrate structure; the N-type gallium nitride layer is arranged on the P-type gallium nitride layer, and the N-type gallium nitride layer is provided with a first opening part located at the edge part; and the charge release layer is arranged on the P-type gallium nitride layer and is positioned in the first opening part. The N-type gallium nitride layer is arranged on the P-type gallium nitride layer to form a PN junction to replace a Schottky junction, so that the problem that the reliability of the gate is reduced due to the degeneration of the Schottky junction is fundamentally avoided, the reliability of the gate structure is improved, the charge release layer can provide a path for releasing trapped charges more quickly compared with the N-type gallium nitride layer, and the reliability of the gate structure is improved. Trapped charges in the P-type gallium nitride layer are quickly released, the influence of the trapped charges on threshold voltage is reduced, and the overall stability of the transistor is improved.
Owner:INNOSCIENCE (ZHUHAI) TECH CO LTD
Semiconductor device having first type unit cells and second type unit cells
The present invention relates to a semiconductor device (100) comprising: a plurality of unit cells (120a, 120b) arranged side by side across a top surface of the semiconductor device (100) wherein the plurality of unit cells (120a, 120b) have a first type (120a) or a second type (120b), each of the first type unit cells (120a) includes a first electrode (121), a second electrode (122), and a third electrode (123) formed at the top surface of the semiconductor device (100); the second electrode (122) is arranged so as to surround the first electrode (121); each of the first electrode (121) and the second electrode (122) is arranged so as to surround the third electrode (123); the first type unit cell (120a) forms a high electron mobility transistor (HEMT) cell, and the second type unit cell (120a) forms a high electron mobility transistor (HEMT) cell. The second type of unit cells (120b) form a Schottky barrier diode (SBD) cell, and the second type of unit cells (120b) form a Schottky barrier diode (SBD) cell.
Owner:HUAWEI DIGITAL POWER TECH CO LTD
HEMT (High Electron Mobility Transistor) And Method Therefor
PendingUS20260114249A1Semiconductor/solid-state device manufacturingSemiconductor devicesCarbon layerDevice material
A heterogeneous epitaxial structure formed on a SiC (silicon carbide) substrate. An intermediate layer comprising AIN is formed overlying the SiC substrate. The surface of the intermediate layer comprises AIN formed by lateral epitaxial growth. The lateral epitaxial growth merges to form the surface comprising a MELO layer (merged epitaxial lateral overgrowth). The intermediate layer includes a carbon layer underlying the MELO layer. At least one device layer comprising GaN (gallium nitride) is formed overlying the surface of the intermediate layer in which one or more semiconductor devices are formed. The carbon layer is heated to fracture portions of the intermediate layer to separate the SiC substrate from the intermediate layer. The SiC substrate is not consumed by the separation thereby allowing perpetual reuse in semiconductor wafer processing.
Owner:THINSIC INC
Semiconductor device
A semiconductor device includes a semiconductor layer on a first surface of a substrate with a first conductivity type, a drain electrode on a second surface of the substrate, first and second well regions in the semiconductor layer, a conductivity type of each of the first and second well regions being a second conductivity type, a doping region between the first and second well regions, a conductivity type of the doping region being the first conductivity type, and a pair of high electron mobility transistors on the semiconductor layer. Each of the first and second well regions includes a first portion adjacent to the source electrode, and a second portion adjacent to the first surface. A maximum distance between the first portions of the first and second well regions is longer than a maximum distance between the second portions of the first and second well regions.
Owner:SAMSUNG ELECTRONICS CO LTD
Method and apparatus for measuring background carrier concentration of high electron mobility transistor
The embodiment of the present disclosure provides a kind of measurement method and device for the background carrier concentration of high electron mobility transistor, belong to semiconductor technical field.The measurement method includes: obtaining unit area reference capacitance and the first measured gate-source capacitance of HEMT, unit area reference capacitance is the capacitance of unit area laminated structure, and the film layer stack structure of laminated structure is identical with the film layer stack structure of HEMT;According to unit area reference capacitance and the first measured gate-source capacitance, determine the equivalent gate-source capacitance area of HEMT;According to the first measured gate-source capacitance and equivalent gate-source capacitance area, determine the unit area calibration capacitance of HEMT;According to unit area calibration capacitance and the channel depth of HEMT, determine the background carrier concentration of HEMT.The embodiment of the present disclosure can effectively improve the accuracy of the background carrier concentration of HEMT measured.
Owner:HC SEMITEK ZHEJIANG CO LTD
Capacitive networks for enhancing high voltage operation of high electron mobility transistors and methods therein
Provided herein are capacitance networks for enhancing high voltage operation of high electron mobility transistors (HEMTs). Integrated and / or external capacitance networks can be provided with a fixed number of capacitively coupled field plates to distribute the electric field in the drift region. The capacitively coupled field plates can advantageously be fabricated on the same metal layer to reduce cost; and a capacitance network can be provided to control the field plate potentials. The potential on each field plate can be predetermined by the capacitance network, resulting in a uniform and / or substantially uniform electric field distribution along the drift region.
Owner:POWER INTEGRATIONS INC
High electron mobility transistor and preparation method thereof
According to the high-electron-mobility transistor and the preparation method thereof, the graphene field plate is used for replacing a traditional metal field plate, compared with a metal material, the carrier mobility of the graphene material is higher, the resistance of the graphene material is far lower than that of the metal material in a high-frequency state, the resistance loss of a device can be reduced, and the performance of the device is improved. The metal field plate has a certain requirement on the thickness of a dielectric layer below the field plate due to the relationship between surface roughness and stress, and graphene is a two-dimensional material and can be in close contact with a dielectric without defects, so that the thickness of the dielectric layer below the field plate can be thinner, and the gate-drain capacitance is reduced; a fringe electric field is prevented from being introduced into the side wall of the field plate, so that parasitic components of gate-drain capacitance can be reduced.
Owner:SHANGHAI XINWEI SEMICON CO LTD
GaN-based high electron mobility transistor integrated device structure and fabrication method
This invention relates to a GaN-based high electron mobility transistor integrated device structure and its manufacturing method. The device structure includes: a channel layer; a barrier layer disposed on the channel layer; a first gate structure disposed on the barrier layer, the first gate structure being made of P-type doped GaN; a first gate electrode disposed on the first gate structure; a dielectric layer disposed on the barrier layer; a second gate electrode disposed on the dielectric layer; a source electrode disposed on the barrier layer and located on the side of the first gate structure away from the second gate electrode; and a drain electrode disposed on the barrier layer and located on the side of the second gate electrode away from the first gate structure. This invention can reduce the peak electric field at the P-type gate edge near the drain, effectively improving the reliability of the device.
Owner:WUXI CHINA RESOURCES MICROELECTRONICS
Preparation method of GaN HEMT (High Electron Mobility Transistor) with special source field plate structure
The invention provides a preparation method of a GaN HEMT with a special source field plate structure, relates to the field of GaN HEMT devices, and aims to simplify the process and improve the process efficiency by optimizing the field plate process of the device. The device comprises a substrate, an epitaxial layer, a protection layer medium, a passivation layer, a source electrode, a grid electrode and a drain electrode. According to the device, SiN is activated in active regions on the two sides through ion implantation and high temperature, ohmic contact windows of a gate pin, a source electrode and a drain electrode are formed in the corresponding positions of a passivation layer through etching, and then gate metal is evaporated and passivated through a medium; and after ohmic contact windows of the source electrode and the drain electrode are etched, the source electrode field plate and the drain electrode with special structures are prepared through a one-step evaporation / electroplating process. According to the method for preparing the source field plate in one step, the technological process is effectively simplified, and the technological cost is reduced. The method has the characteristics of simple manufacturing process and high manufacturing efficiency.
Owner:SUZHOU LIANG DONGXIN MICROELECTRONICS CO LTD
HEMT packaging structure
The invention relates to the technical field of semiconductors, in particular to an HEMT (High Electron Mobility Transistor) packaging structure, which comprises a plastic packaging body, and the plastic packaging body comprises a first surface, a second surface and a peripheral side part, an active region of the semiconductor device comprises a plurality of cellular units, and each cellular unit comprises a substrate, an III-V epitaxial layer arranged on the front surface of the substrate, a first electrode and a second electrode which are arranged on the III-V epitaxial layer, a control electrode arranged between the first electrode and the second electrode, and a dielectric layer covering the first electrode, the second electrode and the control electrode; the first heat dissipation metal body covers the surface of the active region and is configured to expose the first surface of the plastic package body, and the first heat dissipation metal body is insulated from the first electrode, the second electrode and the control electrode; the second heat dissipation metal body covers the back surface of the substrate and is configured to expose the second surface of the plastic package body. Compared with the prior art, the packaging structure adopts a double-sided heat dissipation packaging design and other structures, so that the heat dissipation capability of the semiconductor device is remarkably enhanced, and the heat dissipation efficiency is improved.
Owner:PIONEER ORIGINAL (SHANGHAI) NEW TECHNOLOGY RESEARCH CO LTD
A P-type gate gallium nitride high electron mobility transistor
This application relates to the field of transistor technology and provides a P-type gate gallium nitride (GaN) high electron mobility transistor. The P-type gate GaN high electron mobility transistor includes a substrate, an aluminum nitride (ANH) nucleation layer, a gallium nitride (GaN) buffer layer, an ANH barrier layer, and a passivation layer. The passivation layer contains a source, a drain, and a P-type gate structure in contact with the ANH barrier layer. The P-type gate structure includes a gate and N non-contacting GaN P-type structures. The gate is disposed on the side of the passivation layer away from the ANH barrier layer. The N GaN P-type structures are arranged sequentially along the contact surface between the passivation layer and the ANH barrier layer, and all N GaN P-type structures are embedded in the gate. The doping concentrations of the different GaN P-type structures are all different. This solution not only improves the threshold voltage of the P-type gate GaN high electron mobility transistor but also does not lead to a decrease in switching speed or an increase in switching losses.
Owner:SHENZHEN SIRIUS SEMICON CO LTD
High electron mobility transistors with low specific on-resistance
A transistor includes a layered semiconductor structure comprising multiple electrodes electrically connected to a source, gate, and drain forming the transistor. The layered semiconductor structure includes a channel layer having a shape formed by a set of fins, and a barrier layer on the channel layer such that the barrier layer coats the fins of the channel layer to define a shape formed by a series of wells. The series of wells of the barrier layer are alternately arranged with the series of fins of the channel layer. The barrier layer is formed of a polar piezoelectric material having a first lattice constant, and the channel layer is formed of a polar material having a second lattice constant, wherein the second lattice constant is greater than the first lattice constant.
Owner:MITSUBISHI ELECTRIC CORP
High electron mobility transistors and methods
The invention relates to a high electron mobility transistor and a method. An HEMT structure includes an epitaxial stack, the epitaxial stack including: a channel layer including a first III-V type semiconductor; and a barrier layer grown on the channel layer in an epitaxial manner and including a second III-V type semiconductor. The first III-V semiconductor and the second III-V semiconductor cause a heterojunction between the channel layer and the barrier layer to form a two-dimensional electron gas (2DEG) within the channel layer. A gate node is disposed over the barrier layer, and a source node is disposed at a lateral side of the gate node so as to be in conductive contact with the 2DEG at least when the 2DEG is continuous below the gate node. A floating p-doped region is disposed over the barrier layer and on a second lateral side of the gate node opposite the source node, the floating p-doped region including a third III-V type semiconductor material.
Owner:INFINEON TECH AUSTRIA AG
Electronic device comprising two high electron mobility transistors
The disclosure concerns an electronic device comprising a HEMT transistor, called main transistor, and at least another HEMT transistor, called additional transistor, stacked on each other. The main transistor and the additional transistor comprise a common drain electrode and, respectively, a main source electrode and an additional source electrode, arranged so that electric conduction paths likely to be formed by the two conduction layers are connected in parallel when one and the other of the HEMT transistors are in the conductive state.
Owner:STMICROELECTRONICS FRANCE
Low surface trap state GaN HEMT device based on pseudo-single crystal passivation and preparation method thereof
The invention discloses a low surface trap state GaN HEMT (High Electron Mobility Transistor) device based on quasi-single crystal passivation and a preparation method thereof. The preparation method comprises the following steps: sequentially forming a nucleating layer, a buffer layer, a channel layer and a barrier layer on a substrate layer; a pseudo-single crystal passivation layer is formed in the gap region, and the pseudo-single crystal passivation layer is in direct contact with the upper interface of the barrier layer; the gap region includes a region between the source region and the gate region, and includes a region between the drain region and the gate region. According to the method provided by the invention, the first passivation layer is deposited on the barrier layer, and the first passivation layer is rapidly annealed to realize quasi-single crystallization, so that the interface state between the passivation layer and the barrier layer is improved, and the reliability of the device is improved.
Owner:XIDIAN UNIV +1