31 results about "Low temperature deposition" patented technology

Provided are high quality metal-nitride, such as aluminum nitride (AlN), films for heat dissipation and heat spreading applications, methods of preparing the same, and deposition of high thermal conductivity heat spreading layers for use in RF devices such as power amplifiers, high electron mobility transistors, etc. Aspects of the inventive concept can be used to enable heterogeneously integrated compound semiconductor on silicon devices or can be used in in non-RF applications as the power densities of these highly scaled microelectronic devices continues to increase.

The invention discloses a cutter composite coating, a preparation method and a cutter, and relates to the technical field of material surface treatment. An AlTiTaN base serves as a base layer attached to a tool base body, a tetrahedron amorphous carbon film layer serves as a functional top layer, and a transition layer with the AlTiTaN base / carbon element proportion gradually changing is arranged between the base layer and the top layer and serves as a supporting and combining part. The problem that in the prior art, due to the fact that the interface bonding force between a tool base body and a strengthening coating is weak, and the internal stress is large, the service life of a tool is short or the machining quality of the tool is poor is effectively solved. Besides, an innovative low-temperature deposition process is further developed for the coating, temperature contradiction in the deposition process is effectively coordinated, firm combination with the top layer can be achieved on the premise that the performance of the AlTiTaN base layer is not sacrificed, and the service life of the AlTiTaN base layer is prolonged. Therefore, the comprehensive performance coating with ultrahigh wear resistance, excellent lubricity, high bonding strength and long service life and the corresponding cutter are obtained.

The application discloses a method for forming a fin structure of a device, comprising: obtaining a substrate formed with a first fin, a shallow trench isolation and a well region; performing first low-temperature oxidation on the surface of the first fin to conformally form a first oxide layer on the surface of the first fin; performing in-situ removal on the first oxide layer to conformally form an intrinsic layer on the surface of the first fin; performing second low-temperature oxidation on the intrinsic layer to conformally form a second oxide layer on the surface of the intrinsic layer; forming a first gate oxide layer on the second oxide layer by using a low-temperature deposition process; and performing hardening and low-temperature annealing treatment on the first gate oxide layer and the second oxide layer to form a dense second gate oxide layer composed of the first gate oxide layer and the second oxide layer below the first gate oxide layer, and a size-repaired second fin composed of the intrinsic layer and the first fin inside the intrinsic layer. The application can repair the fin size and damaged lattice, and form a densified gate oxide layer, thereby improving the device performance.

This invention discloses a method for preparing high sheet resistance shallow pn junction single-crystal silicon wafers based on rapid boron diffusion, comprising the following steps: S1: depositing a boron-containing precursor on the textured silicon wafer surface; S2: depositing a low-temperature oxide layer on the surface of the boron-containing precursor; S3: placing the silicon wafer with the deposited low-temperature oxide layer in a rapid thermal processing device, rapidly heating it to 1050-1350℃ at a heating rate of 5-200℃ / s, holding it at this temperature for 20-600s, and then rapidly cooling it to complete the diffusion and activation of boron atoms in the silicon wafer. This invention employs a combination of low-temperature deposition and rapid boron diffusion, which can significantly shorten the boron diffusion time, reduce energy consumption, and shorten the high-temperature processing time. It also suppresses the formation of oxygen precipitate defects at the source, eliminating problems such as black cores and black rings in batteries, and significantly improving carrier lifetime and material electrical performance.

The invention provides a 3D MIM capacitor structure and a preparation method thereof, and the method comprises the steps: firstly depositing a first TiN lower electrode layer with a (200) crystal face under a low-temperature deposition condition of a TiN material through a low-temperature template method, and then depositing a second TiN lower electrode layer at a temperature required by the deposition of a TiN material with a (111) crystal face, thereby forming a TiN lower electrode layer of the 3D MIM capacitor structure, and finally, annealing the TiN lower electrode by adopting a nitrogen-containing supercritical fluid to finally obtain a TiN lower electrode layer with low surface roughness and ensure small impedance Rs of the TiN lower electrode layer.

Described herein are composite battery electrode structures and methods of forming such structures. Composite battery electrode structures comprise active electrode material structures and polymer structures such that at least a portion of the polymer structures at least partially protrudes into some of the high capacity structures. Some of these polymer structures may be fully enclosed by the active electrode material structures. Other polymer structures may only partially extend inside the active electrode material structures. Furthermore, additional polymer structures may be bound to the external surface of the active electrode material structures. Composite battery electrode structures may be formed using low-temperature deposition techniques, such as solvent-thermal synthesis, direct chemical reduction, and electrochemical deposition. More specifically, composite battery electrode structures may be formed from a solution comprising active electrode material precursors and polymer precursors, e.g., dissolved polymers, monomers, and / or conductive polymers electrically coupled to the working electrodes.

The invention relates to a chromium film for a photomask and a preparation method thereof. The preparation method comprises the following steps: pretreating a substrate; depositing a transition layer on the pretreated substrate; performing oxygen-containing plasma interface activation on the transition layer; depositing a chromium main functional layer on the activated transition layer at low temperature and regulating stress to obtain a chromium film; and performing post-treatment to stabilize the structure and stress of the chromium film. The chromium film comprises a substrate which is a supporting carrier of the chromium film; the chromium main functional layer is a carrier for photoetching of the photomask, and the chromium main functional layer is arranged on the substrate; and the transition layer is configured to realize high bonding and stress buffering of the substrate and the chromium main functional layer, and the transition layer is arranged between the substrate and the chromium main functional layer. According to the invention, the stress of the film layer is fundamentally reduced, ultrahigh binding force is realized at ultralow temperature, and the pattern precision and uniformity are synchronously improved.

The invention provides a method for depositing a thin film on the surface of a wafer. The method at least comprises the following steps: S1, providing a wafer subjected to dry etching treatment; s2, performing rapid thermal annealing treatment on the wafer to repair surface damage caused by dry etching; and S3, depositing a dielectric film on the surface of the wafer subjected to the rapid thermal annealing treatment through a plasma enhanced chemical vapor deposition process. According to the collaborative film deposition method, silicon wafer surface damage caused by dry etching is eliminated, precise control over the film thickness and optimization of the fitting degree of the measurement result can be achieved, the reliability of the film measurement result is improved, the method is combined with efficient annealing of RTP and low-temperature deposition of PECVD, and the reliability of the film measurement result is improved. Cooperative regulation and control of the film thickness, the crystallinity, the interface quality and the measurement fitting degree are achieved, and the method has great significance in promoting miniaturization of semiconductor devices.

Technologies for a high gradient of dopant concentration in gate-all-around transistors are disclosed. In an illustrative embodiment, a source / drain region of a gate-all-around transistor may have a relatively high dopant concentration, such as a dopant concentration of over 1020 cm−3, and an adjacent channel region may have a relatively low dopant concentration, such as a dopant concentration of less than 1018 cm−3. At an interface between the source / drain region and the channel region, the logarithmic slope of the dopant concentration may be high, such as two orders of magnitude in less than a nanometer. In order to maintain such a high dopant concentration, the source / drain region with a high dopant concentration is deposited using a low-temperature deposition technique after high-temperature processing steps are completed.

This invention relates to the field of wastewater treatment technology and discloses a composite catalytic electrode based on titanium suboxide and its preparation method. The composite catalytic electrode consists of a titanium plate substrate, a conductive titanium suboxide transition layer, and a BDD catalytic layer grown under core-shell seed conditions. Its preparation method comprises five steps: titanium plate substrate pretreatment, preparation of the conductive titanium suboxide transition layer, surface composite modification, construction of the core-shell seed layer, and low-temperature CatCVD deposition. This invention solves the problems of high interfacial stress, insufficient bonding strength, high-temperature oxidation, and difficulty in bonding between the titanium substrate and BDD in existing BDD-based electrodes. The electrode interfacial bonding strength is ≥6.0 MPa, the BDD crystallinity is ≥88%, and in the treatment of high-concentration, recalcitrant organic wastewater with COD ≥1000 mg / L, the COD removal rate is ≥98.0%, with excellent cycle stability, demonstrating significant practical application value.

The invention discloses a low-expansion low-internal-resistance CVD (chemical vapor deposition) silicon-carbon composite material as well as a preparation method and application thereof. The preparation method comprises the following steps: S1, mixing and cross-linking oxygen cross-linked asphalt and an aromatic boron source, and crushing; s2, dispersing and carbonizing the cross-linked particles in a catalytic acid solution; s3, performing integrated carbonization-activation on the carbonized skeleton and an activating agent to obtain porous carbon; s4, depositing silicon on the porous carbon at a low temperature, and then heating for boron doping; and S5, carrying out carbon layer coating to obtain a final product. According to the invention, through oxygen-boron synergistic crosslinking and low-temperature two-step CVD process, the material structure is regulated and controlled on the molecular level, and the prepared silicon-carbon composite material has a unique porous carbon-silicon-carbon coating layer composite structure and has low volume expansion rate (lt; 18%), low resistivity and high gram capacity characteristics, while exhibiting excellent flexibility, bending radius lt; and the material is suitable for a plurality of fields such as power batteries, flexible wearable equipment, super capacitors and the like.

The invention relates to a phase shift photomask and a preparation method thereof. The preparation method comprises the following steps: sequentially depositing a first transition layer and a MoSi phase shift layer on a substrate; depositing a second transition layer on the MoSi phase shift layer; and depositing a Cr shading layer on the second transition layer at low temperature, wherein the temperature in the deposition process is less than or equal to 50 DEG C. The phase shift photomask comprises a substrate which is a base of the phase shift photomask and a plurality of phase shift photomasks which are sequentially arranged from bottom to top, the first transition layer is configured to improve the adhesion strength of the first transition layer on the substrate; the MoSi phase shift layer is a carrier for realizing phase shift; the second transition layer is configured to improve the interface bonding force of the MoSi phase shift layer and the Cr shading layer; and a Cr light shielding layer which realizes light shielding so as to shield a non-pattern area of the photoetching light. The MoSi / Cr interface bonding force Lc can reach 36.8 N or above.

The invention relates to a method for improving process defects of a low-temperature deposition process. The method comprises the following steps: preparing a spacer layer in a deposition reaction cavity through the low-temperature deposition process; after deposition is completed, reactive purging is conducted on the deposition reaction cavity so that chlorine-containing by-products in the deposition reaction cavity can be removed; wherein the purging gas for reactive purging comprises ammonia gas. The method can effectively improve the process defects caused by chlorine-containing by-product residues in the low-temperature deposition process, significantly improve the yield and consistency of semiconductor device products, reduce the production cost increase caused by defective product detection or reworking, is suitable for various advanced semiconductor manufacturing processes, and has wide application prospects. And the method has remarkable industrial application value and popularization potential.

The present invention relates to a low-temperature deposition material, a method for forming a low-temperature deposition film, and semiconductor substrates and semiconductor devices manufactured thereby. By applying a predetermined substance that can act as a strong reducing agent even in low-temperature processes, the present invention not only effectively manufactures thin films and / or metal nitride films with low resistance in low-temperature processes, but also reduces impurities in the film caused by ligands such as carbon, thereby improving physical properties such as resistivity and crystallinity.

The present application relates to the field of photovoltaic cells, and particularly relates to a variable-temperature diffusion process based on photovoltaic cells. Specifically, it comprises the following steps: (1) low-temperature deposition on a silicon wafer with completed tunneling oxide layer and intrinsic amorphous silicon at 760-790 degrees Celsius; (2) low-temperature promotion at a temperature increased by 30-40 degrees Celsius; (3) high-temperature deposition at a temperature increased by 60-70 degrees Celsius; (4) high-temperature promotion at the temperature of step (3); (5) medium-temperature deposition at a temperature decreased by 20-50 degrees Celsius; and (6) low-temperature deposition at a temperature decreased by 80-100 degrees Celsius. The present application reduces the amount of phosphorus elements penetrating the tunneling oxide layer and increases the concentration of phosphorus in the doped polysilicon through gradient temperature rising diffusion, promotion and gradient temperature decreasing diffusion.

The application provides a long-range ferromagnetic GaN material and a preparation method and application thereof. In the preparation method, the low temperature corresponding to the square wave pulse temperature is 500-700 DEG C, a stack mismatched wurtzite GaN structure layer is formed on a substrate during low-temperature deposition, the high temperature corresponding to the square wave pulse temperature is 800-1000 DEG C, a wurtzite structure GaN layer is deposited on the stack mismatched wurtzite GaN structure layer during high-temperature deposition, and the stack mismatched wurtzite GaN structure layer is buried. The stack mismatched grain boundary with long-range ferromagnetic sequence is formed in the GaN by controlling the temperature to change periodically in the square wave pulse, other magnetic impurities are not introduced, and the reaction chamber is not polluted. The energy band of the stack mismatched wurtzite GaN structure is simulated, the spin polarization property is confirmed to exist, on the basis, the Curie temperature is predicted according to the mean field approximation, and it is confirmed that the long-range magnetic sequence can still be kept under the condition that the temperature is higher than room temperature.

This disclosure provides a method of forming a hard mask film over a semiconductor device. The method includes determining a film stress of the hard mask film based on an internal stress of the semiconductor device, performing a tungsten silicide (WSi) deposition at a cryogenic temperature over the semiconductor device to form the hard mask film, determining a time period of an annealing process to be performed based on the determined film stress of the WSi hard mask film, and performing the annealing process to the WSi hard mask film based on the determined time period.

The invention discloses a helium-assisted low-temperature thin film deposition method and device, and belongs to the technical field of thin film deposition. The method mainly comprises the steps that when reaction gas is introduced into a deposition cavity loaded with a to-be-deposited substrate, helium with the preset flow is introduced into the deposition cavity at the same time; helium and reaction gas are excited through a radio frequency electric field to generate mixed plasmas, low-temperature thin film deposition is carried out in a deposition cavity of the mixed plasmas, helium is preferentially ionized under the action of the radio frequency electric field to generate helium high-energy electrons, the helium high-energy electrons provide energy for dissociation of the reaction gas into the plasmas, and in addition, the reaction gas is separated into the mixed plasmas. Local heat generated in the helium plasma discharging process is conducted to the cavity outer wall cooling device through high thermal conductivity of helium high-energy electrons, and therefore temperature fluctuation in the cavity is reduced. The plasma enhancement and energy transfer characteristics of helium are utilized, and on the premise that the low-temperature deposition temperature is guaranteed, the deposition rate and the film performance are synchronously improved.

The invention relates to a solar cell and a preparation method and preparation equipment thereof. The method comprises the step of forming a passivation contact structure on at least one side of a substrate, wherein the passivation contact structure comprises a tunneling oxide layer and a plurality of silicon doping layers. The multi-layer silicon doping layer is formed on one side, deviating from the substrate, of the tunneling oxide layer, and doping elements of the multi-layer silicon doping layer comprise metal doping elements and conductive type doping elements; the doping concentration of the metal doping element in each silicon doping layer is sequentially increased along the direction deviating from the substrate, and the doping concentration of the conductive type doping element in each silicon doping layer is sequentially reduced along the direction deviating from the substrate; a metal electrode is formed in the contact area of the side, away from the substrate, of the passivation contact structure, the metal electrode makes contact with the outermost silicon doping layer in the multiple silicon doping layers, and the outermost silicon doping layer is further used for blocking diffusion of metal elements in the metal electrode. The method is used for synchronously realizing high passivation quality, low contact resistance and strong metal diffusion barrier under a low-temperature deposition process so as to improve the battery performance.

A method and system are provided for the low temperature deposition of tungsten (W) and W-based thin films through the planned and engineered ex-situ or in-situ creation of vapor phase metastable clusters or metastable complexes to achieve precise film conformality, composition, morphology, structure, and thickness. The tungsten based thin film deposition techniques include chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed CVD, molecular layer deposition (MLD), self-assembled monolayer (SAM) deposition, and Click chemistry deposition (CCD).

The invention relates to a low-temperature strengthening method and system for photomask coating, and the method comprises the following steps: providing a substrate on which a thin film is deposited, or depositing the thin film on the substrate through a PVD (Physical Vapor Deposition) process at a low temperature; and placing the substrate deposited with the thin film in the nanofluid, and performing laser scanning on the surface of the thin film by using laser to obtain a photomask semi-finished product so as to cooperatively release local stress of the thin film and improve the hardness and compactness of the thin film. The system includes a low temperature PVD deposition module configured to deposit a target as a thin film; and a laser-nanofluid synergistic post-processing module configured to modify the thin film. On the premise of not changing the macrographic and optical functions of the film, the microstructure of the film is obviously strengthened, the hardness, compactness, chemical washing resistance and particle impact resistance of the film are improved, the service life of a mask is prolonged, and in addition, the optical constant of the film can be regulated and controlled.

The systems, apparatus, and methods include a detector including a plurality of detection elements comprising a portion of a silicon substrate, the portion of the silicon substrate including: a front side of the portion of the silicon substrate including a PIN or NIP diode including a p-type region and an n-type region; and a back side of the portion of the silicon substrate opposite the front side, the back side including a low-temperature deposited passivation layer that configures the PIN or NIP diode to detect electrons entering the back side of the portion of the silicon substrate when a bias is applied.

The invention relates to the technical field of semiconductor wafers, in particular to a preparation method of a semiconductor graphical epitaxial thin film, an embedded electrode structure and application, and the method comprises the following steps: S1, carrying out the pretreatment of a substrate layer, and carrying out the low-temperature deposition of a high-temperature-resistant hard mask layer on the surface of the pretreated substrate layer; s2, performing segmented etching treatment on the deposited high-temperature-resistant hard mask layer and part of the substrate layer according to a photoetching pattern, and removing the photoresist after etching treatment to obtain a first substrate; s3, the first substrate is placed in a PLD cavity, a bottom electrode thin film layer is epitaxially deposited on the etching face of the first substrate, the thickness of the bottom electrode thin film layer is the same as the etched depth of the substrate layer, and a second substrate is obtained; and S4, performing wet etching on the second substrate until the high-temperature-resistant hard mask layer is completely removed, and performing post-processing to obtain the embedded electrode structure. According to the technical scheme, the problems of high-temperature failure, cavity carbon pollution, pattern collapse, surface roughness and the like of traditional optical cement are solved.

The invention relates to a continuous preparation method of an interface phase with uniformity and high thermal stability, and belongs to the technical field of ceramic matrix composite material preparation. In order to solve the problems that an interface phase prepared by low-temperature chemical vapor deposition is uniform but poor in stability, and interface phase pollution is easily caused by off-line high-temperature heat treatment, the invention provides a continuous preparation method. The method comprises the steps that a flexible fiber substrate firstly penetrates through a low-temperature chemical vapor deposition area, and a uniform initial interface phase is obtained; and then directly entering a real-time online high-temperature heat treatment area without passing through an atmospheric environment, and carrying out real-time online high-temperature crystallization treatment at 1350-1800 DEG C. According to the method, through series integration of low-temperature deposition and online high-temperature heat treatment, online continuous completion of the whole deposition-crystallization process of the interface phase is achieved, water and oxygen pollution in the interface phase transfer process is fundamentally avoided, and finally the interface phase has excellent uniformity and high thermal stability; and a reliable base interface phase preparation technology is provided for the high-performance ceramic-based composite material.

The invention discloses a method, equipment and a micro-display device for low-temperature atomic layer deposition of a film, and a hafnium oxide film is deposited at a low temperature through circulation steps of surface activation, hafnium source adsorption, ligand promotion and oxidation film formation. The method specifically comprises the following steps: activating the substrate surface by ammonia plasma; introducing a hafnium precursor to adsorb the hafnium precursor; mixed gas of trifluoroacetic acid and ozone is introduced, trifluoroacetic acid serves as an acid accelerant to be subjected to ligand exchange with the adsorbed hafnium precursor to generate an active intermediate, and the intermediate is oxidized into hafnium oxide through ozone at the low temperature. By introducing the ligand promotion step, the traditional oxidation path is changed, the low-temperature deposition bottleneck of the high-quality hafnium oxide thin film is successfully broken through, the method is particularly suitable for thin film packaging of micro-display devices sensitive to temperature, and the advantages of high dielectric, low electric leakage and high thermal stability of hafnium oxide can be exerted while an organic functional layer is protected. The invention also provides special atomic layer deposition equipment for implementing the method.

Technologies for achieving a high gradient of dopant concentration in gate all-around transistors are disclosed. In an illustrative embodiment, a source / drain region of a gate all-around transistor can have a relatively high dopant concentration, for example, a concentration greater than 10²⁰ cm⁻³, and an adjacent channel region can have a relatively low dopant concentration, for example, a concentration less than 10¹⁸ cm⁻³. At an interface between the source / drain region and the channel region, the logarithmic slope of the dopant concentration can be high, for example, two orders of magnitude in less than one nanometer. To maintain such a high dopant concentration, the source / drain region with the high dopant concentration is deposited after completion of the high-temperature processing steps using a low-temperature deposition technique.

The application discloses a low-temperature synthesis method of a long-acting self-sterilizing coating and belongs to the technical field of inorganic nano-coating low-temperature curing manufacturing. + -(Ti(O2)) 2‑ Preparation of a complex precursor solution; (2) spraying of the Ag + -(Ti(O2)) 2‑ complex precursor solution; (3) baking, curing and obtaining of a high-temperature-intolerant treatment substrate with a low-temperature deposited nano-silver-titanium dioxide coating by using the cured Ag + -(Ti(O2)) 2‑ complex precursor solution coating prepared in the above steps. The application breaks through the limitation that the traditional high-temperature thermal deposition titanium dioxide nano-coating technology cannot be applied to high-temperature-intolerant substrate materials, realizes low-temperature deposition of a nano-silver-titanium dioxide coating capable of absorbing visible light on the surface of a high-temperature-intolerant substrate material, and the low-temperature deposited nano-silver-titanium dioxide coating has a long-acting antibacterial self-sterilizing function on the surface of the substrate material.

This disclosure provides a method of forming a hard mask film over a semiconductor device. The method includes determining a film stress of the hard mask film based on an internal stress of the semiconductor device, performing a tungsten silicide (WSi) deposition at a cryogenic temperature over the semiconductor device to form the hard mask film, determining a time period of an annealing process to be performed based on the determined film stress of the WSi hard mask film, and performing the annealing process to the WSi hard mask film based on the determined time period.

The present application relates to a kind of micro-nano structure manufacturing method, by the improvement of traditional reactive ion beam etching technology, first using colloidal ball self-assembly technology to prepare nanosphere array of periodic structure on the surface of element, then etching colloidal ball using wide-beam ion source, and control process conditions such as working gas pressure, temperature, time, etching power, adjust the duty cycle between colloidal ball.Then using the low-temperature deposition method of film, thin film mask is plated into the gap between colloidal ball, then colloidal ball is removed using matching solution.Finally, using wide-beam ion source etching element, the pattern of thin film mask is transferred to element, and finally micro-nano structure element is obtained.The present application can provide sample for the experimental research or industrial production of high-power laser window.

This invention discloses a method for preparing erbium-doped gallium oxide thin films via fog chemical vapor deposition and its applications. The method includes: preparing a solution containing gallium oxide and erbium precursors, adding a stabilizer; forming micron-sized droplets through ultrasonic or pneumatic atomization; depositing the film at a low temperature of 200-600℃ on substrates such as sapphire or silicon using nitrogen or argon as a carrier gas; and annealing to optimize crystal quality. The resulting thin films have an erbium doping concentration of 0.1-5 at.%, a thickness of 100-500 nm, a β-phase structure, a photoluminescence peak at 1.54 μm, a quantum yield of 12.0-20.1%, and a uniformity of 95-99%, making them suitable for fiber optic communication waveguide amplifiers and deep ultraviolet photodetectors. This method is low-temperature efficient, compatible with various substrates, reduces thermal stress, and significantly improves film quality and device performance.