57 results about "Low temperature deposition" patented technology

The invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is internally provided with a first region and a drift region, and the first region is adjacent to the drift region; forming a first dielectric material layer on the substrate by adopting a thermal oxidation process; a part of the first dielectric material layer is removed to obtain a first dielectric layer, the first dielectric layer covers the first region and a part of the drift region adjacent to the first region, and the first dielectric layer above the part of the drift region adjacent to the first region serves as a first field dielectric layer; and forming a second field dielectric layer on the first field dielectric layer. Compared with a mode of directly forming the field dielectric layer with the first thickness on the surface of the drift region through a low-temperature deposition process, the first field dielectric layer is formed through a thermal oxidation process, so that the interface defect density of the field dielectric layer and the drift region can be reduced, and the reliability of the semiconductor structure is improved.

The invention relates to the technical field of semiconductor materials, in particular to a method for preparing a semiconductor material from high-purity quartz sand. The method comprises the following steps: firstly, grafting and modifying the surface of quartz sand through 3-aminopropyltriethoxysilane, complexing metal impurities by using amino functional groups, and improving the purity of a precursor from the source; secondly, hydrogen / deuterium gas pulse back-and-forth switching is adopted, surface hydrogen atom dynamics is regulated and controlled through the isotope effect, and an etching-nucleation synergistic window is created; and finally, through sequential alternate supply of silane and disilane, time separation of a weak bond etching period and a high-activity nucleation period is realized. The prepared semiconductor material shows excellent performance, and compared with a traditional method, the technical problem of low-temperature deposition of a high-quality semiconductor film is solved through full-process optimization from a material source to a deposition end.

The application provides a kind of light waveguide microfluid detection system based on CMOS image sensing, comprising: microfluid chip, spectral collection device and analysis device;Microfluid chip includes: light waveguide and micro flow channel, light waveguide is used to guide light into micro flow channel along horizontal direction;Microfluid chip further includes: CMOS image sensing layer, lower cladding layer, waveguide layer, upper cladding layer and flow channel cover plate are sequentially arranged from bottom to top, waveguide layer is formed by silicon nitride material at 25-150 DEG C deposition temperature, waveguide layer is used to form light waveguide;Micro flow channel penetrates upper cladding layer, waveguide layer and lower cladding layer from top to bottom to expose CMOS image sensing layer;Micro flow channel width is 10-100 μm.It has beneficial effects: low-temperature deposition of silicon nitride light waveguide with adjustable optical performance on CMOS image sensing layer and high molecular polymer material, without damaging CMOS image sensing layer, reducing the preparation work such as adjusting the collection light path in the experiment, improving the experimental efficiency;Improve the portability of detection system, greatly increase the application scene of system.

Provided are high quality metal-nitride, such as aluminum nitride (AlN), films for heat dissipation and heat spreading applications, methods of preparing the same, and deposition of high thermal conductivity heat spreading layers for use in RF devices such as power amplifiers, high electron mobility transistors, etc. Aspects of the inventive concept can be used to enable heterogeneously integrated compound semiconductor on silicon devices or can be used in in non-RF applications as the power densities of these highly scaled microelectronic devices continues to increase.

The invention discloses a cutter composite coating, a preparation method and a cutter, and relates to the technical field of material surface treatment. An AlTiTaN base serves as a base layer attached to a tool base body, a tetrahedron amorphous carbon film layer serves as a functional top layer, and a transition layer with the AlTiTaN base / carbon element proportion gradually changing is arranged between the base layer and the top layer and serves as a supporting and combining part. The problem that in the prior art, due to the fact that the interface bonding force between a tool base body and a strengthening coating is weak, and the internal stress is large, the service life of a tool is short or the machining quality of the tool is poor is effectively solved. Besides, an innovative low-temperature deposition process is further developed for the coating, temperature contradiction in the deposition process is effectively coordinated, firm combination with the top layer can be achieved on the premise that the performance of the AlTiTaN base layer is not sacrificed, and the service life of the AlTiTaN base layer is prolonged. Therefore, the comprehensive performance coating with ultrahigh wear resistance, excellent lubricity, high bonding strength and long service life and the corresponding cutter are obtained.

The invention discloses semiconductor processing equipment and a semiconductor processing method. The process equipment comprises: a reaction chamber in which a substrate is placed; the ultraviolet light source is positioned above the reaction cavity; the light barrier is arranged between the ultraviolet light source and the reaction cavity, and the duration of the ultraviolet light participating in the deposition reaction is controlled by opening or closing the light barrier; the controller is configured to respond to the situation that the metal source in the reaction cavity is adsorbed on the surface of the substrate, an oxygen source is introduced into the reaction cavity, and the light barrier is opened, so that the oxygen source reacts with the metal source under the irradiation of the ultraviolet light, and an oxide thin film is generated; and closing the light barrier before the metal source of the next deposition reaction is introduced into the reaction cavity. The reaction activity of the oxygen source in the low-temperature deposition reaction can be improved, so that the content of carbon impurities in the oxide thin film is reduced, the compactness of the thin film is improved, and the requirements of productivity and packaging performance are met.

The application discloses a method for forming a fin structure of a device, comprising: obtaining a substrate formed with a first fin, a shallow trench isolation and a well region; performing first low-temperature oxidation on the surface of the first fin to conformally form a first oxide layer on the surface of the first fin; performing in-situ removal on the first oxide layer to conformally form an intrinsic layer on the surface of the first fin; performing second low-temperature oxidation on the intrinsic layer to conformally form a second oxide layer on the surface of the intrinsic layer; forming a first gate oxide layer on the second oxide layer by using a low-temperature deposition process; and performing hardening and low-temperature annealing treatment on the first gate oxide layer and the second oxide layer to form a dense second gate oxide layer composed of the first gate oxide layer and the second oxide layer below the first gate oxide layer, and a size-repaired second fin composed of the intrinsic layer and the first fin inside the intrinsic layer. The application can repair the fin size and damaged lattice, and form a densified gate oxide layer, thereby improving the device performance.

This invention discloses a method for preparing high sheet resistance shallow pn junction single-crystal silicon wafers based on rapid boron diffusion, comprising the following steps: S1: depositing a boron-containing precursor on the textured silicon wafer surface; S2: depositing a low-temperature oxide layer on the surface of the boron-containing precursor; S3: placing the silicon wafer with the deposited low-temperature oxide layer in a rapid thermal processing device, rapidly heating it to 1050-1350℃ at a heating rate of 5-200℃ / s, holding it at this temperature for 20-600s, and then rapidly cooling it to complete the diffusion and activation of boron atoms in the silicon wafer. This invention employs a combination of low-temperature deposition and rapid boron diffusion, which can significantly shorten the boron diffusion time, reduce energy consumption, and shorten the high-temperature processing time. It also suppresses the formation of oxygen precipitate defects at the source, eliminating problems such as black cores and black rings in batteries, and significantly improving carrier lifetime and material electrical performance.

An amorphous carbon hard mask is formed having low hydrogen content and low sp3 carbon bonding but high modulus and hardness. The amorphous carbon hard mask is formed by depositing an amorphous carbon layer at a low temperature in a plasma deposition chamber and treating the amorphous carbon layer to a dual plasma-thermal treatment. The dual plasma-thermal treatment includes exposing the amorphous carbon layer to inert gas plasma for implanting an inert gas species in the amorphous carbon layer and exposing the amorphous carbon layer to a high temperature. The amorphous carbon hard mask has high etch selectivity relative to underlying materials.

The invention provides a 3D MIM capacitor structure and a preparation method thereof, and the method comprises the steps: firstly depositing a first TiN lower electrode layer with a (200) crystal face under a low-temperature deposition condition of a TiN material through a low-temperature template method, and then depositing a second TiN lower electrode layer at a temperature required by the deposition of a TiN material with a (111) crystal face, thereby forming a TiN lower electrode layer of the 3D MIM capacitor structure, and finally, annealing the TiN lower electrode by adopting a nitrogen-containing supercritical fluid to finally obtain a TiN lower electrode layer with low surface roughness and ensure small impedance Rs of the TiN lower electrode layer.

Described herein are composite battery electrode structures and methods of forming such structures. Composite battery electrode structures comprise active electrode material structures and polymer structures such that at least a portion of the polymer structures at least partially protrudes into some of the high capacity structures. Some of these polymer structures may be fully enclosed by the active electrode material structures. Other polymer structures may only partially extend inside the active electrode material structures. Furthermore, additional polymer structures may be bound to the external surface of the active electrode material structures. Composite battery electrode structures may be formed using low-temperature deposition techniques, such as solvent-thermal synthesis, direct chemical reduction, and electrochemical deposition. More specifically, composite battery electrode structures may be formed from a solution comprising active electrode material precursors and polymer precursors, e.g., dissolved polymers, monomers, and / or conductive polymers electrically coupled to the working electrodes.

The invention relates to a chromium film for a photomask and a preparation method thereof. The preparation method comprises the following steps: pretreating a substrate; depositing a transition layer on the pretreated substrate; performing oxygen-containing plasma interface activation on the transition layer; depositing a chromium main functional layer on the activated transition layer at low temperature and regulating stress to obtain a chromium film; and performing post-treatment to stabilize the structure and stress of the chromium film. The chromium film comprises a substrate which is a supporting carrier of the chromium film; the chromium main functional layer is a carrier for photoetching of the photomask, and the chromium main functional layer is arranged on the substrate; and the transition layer is configured to realize high bonding and stress buffering of the substrate and the chromium main functional layer, and the transition layer is arranged between the substrate and the chromium main functional layer. According to the invention, the stress of the film layer is fundamentally reduced, ultrahigh binding force is realized at ultralow temperature, and the pattern precision and uniformity are synchronously improved.

The invention provides a method for depositing a thin film on the surface of a wafer. The method at least comprises the following steps: S1, providing a wafer subjected to dry etching treatment; s2, performing rapid thermal annealing treatment on the wafer to repair surface damage caused by dry etching; and S3, depositing a dielectric film on the surface of the wafer subjected to the rapid thermal annealing treatment through a plasma enhanced chemical vapor deposition process. According to the collaborative film deposition method, silicon wafer surface damage caused by dry etching is eliminated, precise control over the film thickness and optimization of the fitting degree of the measurement result can be achieved, the reliability of the film measurement result is improved, the method is combined with efficient annealing of RTP and low-temperature deposition of PECVD, and the reliability of the film measurement result is improved. Cooperative regulation and control of the film thickness, the crystallinity, the interface quality and the measurement fitting degree are achieved, and the method has great significance in promoting miniaturization of semiconductor devices.

A titanium complex useful for producing a titanium-containing thin film under low temperature deposition conditions without using an oxidative gas is provided. A titanium complex represented by the general formula (1) (wherein each of R1 and R2 is independently a C1-6 alkyl group which may be bonded with each other to form a ring, X is CR3 or a N atom, Y is CR4 or a N atom, Z is CR5 or a N atom, each of R3, R4 and R5 is independently a hydrogen atom or a C1-6 alkyl group, and n is an integer of from 1 to 3).

Technologies for a high gradient of dopant concentration in gate-all-around transistors are disclosed. In an illustrative embodiment, a source / drain region of a gate-all-around transistor may have a relatively high dopant concentration, such as a dopant concentration of over 1020 cm−3, and an adjacent channel region may have a relatively low dopant concentration, such as a dopant concentration of less than 1018 cm−3. At an interface between the source / drain region and the channel region, the logarithmic slope of the dopant concentration may be high, such as two orders of magnitude in less than a nanometer. In order to maintain such a high dopant concentration, the source / drain region with a high dopant concentration is deposited using a low-temperature deposition technique after high-temperature processing steps are completed.

The present invention relates to a deposition material for a metalloid nitride film, a method for forming a metalloid nitride film, and a semiconductor substrate and a semiconductor device manufactured thereby, which have the effect of providing a low-temperature deposition material for a metalloid nitride film, a method for forming a metalloid nitride film, and a semiconductor substrate and a semiconductor device manufactured thereby. According to the present invention, a halogen-free precursor is deposited on a substrate by sequentially or simultaneously injecting a low-temperature deposition substance into a metalloid precursor compound that does not contain halogen as a ligand and by replacing the ligand of the halogen-free precursor with the low-temperature deposition substance, such that the reactivity with a reactive substance injected subsequently in the deposition process is improved, and thus the low-temperature deposition substance is deposited on the substrate. Therefore, the growth speed of the film is improved, and the density and refractive index of the deposited film are remarkably improved.

The invention relates to a memory cell encapsulant material in a three-dimensional memory array. After forming the memory cells, an encapsulant material may be formed. The encapsulant material may include some materials on the memory cell having a relatively high dielectric constant. The sealant material may be positioned between the memory cell and a pillar and may prevent or reduce diffusion between the memory cell and the pillar while supporting access to the memory cell. The sealant material may be formed as one or more layers of material and may be associated with a relatively high dielectric constant such that the sealant material may support low temperature deposition.

Methods, systems, and devices for a memory cell sealant material in a three-dimensional memory array are described. After forming a memory cell, a sealant material may be formed. The sealant material may include some material with a relatively high dielectric constant on the memory cell. The sealant material may be located between the memory cell and a pillar and may prevent or reduce diffusion between the memory cell and the pillar while supporting the memory cell being accessed. The sealant material may be formed as one or more layers of materials and may be associated with a relatively high dielectric constant, such that the sealant material may support low temperature deposition.

This invention relates to the field of wastewater treatment technology and discloses a composite catalytic electrode based on titanium suboxide and its preparation method. The composite catalytic electrode consists of a titanium plate substrate, a conductive titanium suboxide transition layer, and a BDD catalytic layer grown under core-shell seed conditions. Its preparation method comprises five steps: titanium plate substrate pretreatment, preparation of the conductive titanium suboxide transition layer, surface composite modification, construction of the core-shell seed layer, and low-temperature CatCVD deposition. This invention solves the problems of high interfacial stress, insufficient bonding strength, high-temperature oxidation, and difficulty in bonding between the titanium substrate and BDD in existing BDD-based electrodes. The electrode interfacial bonding strength is ≥6.0 MPa, the BDD crystallinity is ≥88%, and in the treatment of high-concentration, recalcitrant organic wastewater with COD ≥1000 mg / L, the COD removal rate is ≥98.0%, with excellent cycle stability, demonstrating significant practical application value.

The invention discloses a low-expansion low-internal-resistance CVD (chemical vapor deposition) silicon-carbon composite material as well as a preparation method and application thereof. The preparation method comprises the following steps: S1, mixing and cross-linking oxygen cross-linked asphalt and an aromatic boron source, and crushing; s2, dispersing and carbonizing the cross-linked particles in a catalytic acid solution; s3, performing integrated carbonization-activation on the carbonized skeleton and an activating agent to obtain porous carbon; s4, depositing silicon on the porous carbon at a low temperature, and then heating for boron doping; and S5, carrying out carbon layer coating to obtain a final product. According to the invention, through oxygen-boron synergistic crosslinking and low-temperature two-step CVD process, the material structure is regulated and controlled on the molecular level, and the prepared silicon-carbon composite material has a unique porous carbon-silicon-carbon coating layer composite structure and has low volume expansion rate (lt; 18%), low resistivity and high gram capacity characteristics, while exhibiting excellent flexibility, bending radius lt; and the material is suitable for a plurality of fields such as power batteries, flexible wearable equipment, super capacitors and the like.

The invention relates to a phase shift photomask and a preparation method thereof. The preparation method comprises the following steps: sequentially depositing a first transition layer and a MoSi phase shift layer on a substrate; depositing a second transition layer on the MoSi phase shift layer; and depositing a Cr shading layer on the second transition layer at low temperature, wherein the temperature in the deposition process is less than or equal to 50 DEG C. The phase shift photomask comprises a substrate which is a base of the phase shift photomask and a plurality of phase shift photomasks which are sequentially arranged from bottom to top, the first transition layer is configured to improve the adhesion strength of the first transition layer on the substrate; the MoSi phase shift layer is a carrier for realizing phase shift; the second transition layer is configured to improve the interface bonding force of the MoSi phase shift layer and the Cr shading layer; and a Cr light shielding layer which realizes light shielding so as to shield a non-pattern area of the photoetching light. The MoSi / Cr interface bonding force Lc can reach 36.8 N or above.

The invention relates to a method for improving process defects of a low-temperature deposition process. The method comprises the following steps: preparing a spacer layer in a deposition reaction cavity through the low-temperature deposition process; after deposition is completed, reactive purging is conducted on the deposition reaction cavity so that chlorine-containing by-products in the deposition reaction cavity can be removed; wherein the purging gas for reactive purging comprises ammonia gas. The method can effectively improve the process defects caused by chlorine-containing by-product residues in the low-temperature deposition process, significantly improve the yield and consistency of semiconductor device products, reduce the production cost increase caused by defective product detection or reworking, is suitable for various advanced semiconductor manufacturing processes, and has wide application prospects. And the method has remarkable industrial application value and popularization potential.

A chip package is provided. The chip package may include: at least one chip; an exposed metal region; a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation, the protection layer structure comprising a low temperature deposited oxide; and a hydrothermally converted metal oxide layer over the protective layer structure.

The utility model discloses a diamond-like carbon film low-temperature deposition device which comprises a microwave dissociation chamber and a radio frequency dissociation chamber which are communicated with each other, the microwave dissociation chamber is communicated with a gas tank of process gas through a gas pipeline, and the microwave dissociation chamber is connected with a microwave source through a microwave waveguide. The radio frequency dissociation chamber is connected with a radio frequency port of a radio frequency power supply through a radio frequency column, and a wafer carrying table is arranged in the radio frequency dissociation chamber. According to the low-temperature deposition device for the diamond-like carbon film, dissociation of process gas is more sufficient, the content of SP3 bonds of the deposited diamond-like carbon film is increased, the hardness of the deposited diamond-like carbon film is improved, and the deposition uniformity of the diamond-like carbon film is better.

The present invention relates to a low-temperature deposition material, a method for forming a low-temperature deposition film, and semiconductor substrates and semiconductor devices manufactured thereby. By applying a predetermined substance that can act as a strong reducing agent even in low-temperature processes, the present invention not only effectively manufactures thin films and / or metal nitride films with low resistance in low-temperature processes, but also reduces impurities in the film caused by ligands such as carbon, thereby improving physical properties such as resistivity and crystallinity.

The invention provides a method for preparing a gradient absorption layer and a solar cell using the absorption layer, and the method for preparing the CIGS gradient absorption layer comprises the following two steps: 1, preparing a low-temperature amorphous CIGS prefabricated layer: sputtering a CIGS quaternary target material in an argon environment through a magnetron sputtering method, an amorphous CIGS prefabricated layer with the thickness of 40-100 nm is deposited on the molybdenum electrode layer at low temperature; and 2, preparing a high-temperature crystalline CIGS gradient absorption layer, namely sputtering and depositing a wide-band-gap copper-indium-gallium-sulfur regulation and control layer near the front surface or the back surface of the CIGS absorption layer when the high-temperature crystalline CIGS absorption layer is deposited by adopting a magnetron sputtering method, and then annealing to prepare the CIGS gradient absorption layer. Therefore, the preparation method has the advantages that the problem that the efficiency of the prepared CIGS thin film solar cell is low due to the fact that element distribution of a common CIGS absorption layer subjected to sputtering deposition is difficult to control, a V-shaped gradient band gap cannot be effectively formed and the defect density is high is solved.

The present application relates to the field of photovoltaic cells, and particularly relates to a variable-temperature diffusion process based on photovoltaic cells. Specifically, it comprises the following steps: (1) low-temperature deposition on a silicon wafer with completed tunneling oxide layer and intrinsic amorphous silicon at 760-790 degrees Celsius; (2) low-temperature promotion at a temperature increased by 30-40 degrees Celsius; (3) high-temperature deposition at a temperature increased by 60-70 degrees Celsius; (4) high-temperature promotion at the temperature of step (3); (5) medium-temperature deposition at a temperature decreased by 20-50 degrees Celsius; and (6) low-temperature deposition at a temperature decreased by 80-100 degrees Celsius. The present application reduces the amount of phosphorus elements penetrating the tunneling oxide layer and increases the concentration of phosphorus in the doped polysilicon through gradient temperature rising diffusion, promotion and gradient temperature decreasing diffusion.

The application provides a long-range ferromagnetic GaN material and a preparation method and application thereof. In the preparation method, the low temperature corresponding to the square wave pulse temperature is 500-700 DEG C, a stack mismatched wurtzite GaN structure layer is formed on a substrate during low-temperature deposition, the high temperature corresponding to the square wave pulse temperature is 800-1000 DEG C, a wurtzite structure GaN layer is deposited on the stack mismatched wurtzite GaN structure layer during high-temperature deposition, and the stack mismatched wurtzite GaN structure layer is buried. The stack mismatched grain boundary with long-range ferromagnetic sequence is formed in the GaN by controlling the temperature to change periodically in the square wave pulse, other magnetic impurities are not introduced, and the reaction chamber is not polluted. The energy band of the stack mismatched wurtzite GaN structure is simulated, the spin polarization property is confirmed to exist, on the basis, the Curie temperature is predicted according to the mean field approximation, and it is confirmed that the long-range magnetic sequence can still be kept under the condition that the temperature is higher than room temperature.

The invention provides a heterojunction cell and a preparation method and application thereof, and belongs to the technical field of photovoltaic.The preparation method comprises the steps that first intrinsic amorphous layers are deposited on the surface and the side face of one side of a substrate, and a second intrinsic amorphous layer and an N-type doped microcrystalline silicon layer are sequentially deposited on the surface and the side face of the other side of the substrate; depositing a P-type doped microcrystalline silicon layer on the surface of the first intrinsic amorphous layer and the side surface of the substrate, wherein the P-type doped microcrystalline silicon layer is overlapped with the N-type doped microcrystalline silicon layer on the side surface of the substrate; preparing a back TCO film layer and a front TCO film layer; preparing metal electrodes on the surfaces of the back TCO film layer and the front TCO film layer respectively; the deposition temperature of the P-type doped microcrystalline silicon layer is less than 160 DEG C and greater than or equal to 130 DEG C. Through low-temperature deposition of the P-type doped microcrystalline silicon layer, the problems that the efficiency of the heterojunction cell is reduced and the power of the assembly is reduced after lamination are avoided, so that the efficiency, the thermal stability and the power of the assembly of the heterojunction cell are effectively improved.

This disclosure provides a method of forming a hard mask film over a semiconductor device. The method includes determining a film stress of the hard mask film based on an internal stress of the semiconductor device, performing a tungsten silicide (WSi) deposition at a cryogenic temperature over the semiconductor device to form the hard mask film, determining a time period of an annealing process to be performed based on the determined film stress of the WSi hard mask film, and performing the annealing process to the WSi hard mask film based on the determined time period.