The invention discloses a P<+> sidewall non-junction device. The P<+> sidewall non-junction device consists of dual gates, a source region, a drain region, a channel region, gate dielectric layers, P<+> sidewalls and isolation layers. For a conventional non-junction device, when the length of a gate is reduced to 10nm, a leakage current is greatly increased, so that the inhibition of the magnitude of the leakage current becomes an important task of a small-sized device. For the conventional non-junction device, a turn-off current of the device in a turn-off state cannot be effectively controlled only by the control capability of the gate. According to the P<+> sidewall non-junction device, PN junction depletion can be formed for assisting in depletion of the device, and when the device is turned on, the gate controls a P<+> region for weakening the PN junction depletion, so that a turn-on current is not influenced. Compared with the conventional non-junction device, the novel P<+> sidewall tri-gate nanowire non-junction device has great advantages, and the advantages are especially remarkable when the gate is very short. The novel device mainly can improve the characteristics of a sub-threshold slope, a turn-on and turn-off current ratio and the like of the conventional non-junction device.