Ferroelectric floating gate memory unit string and preparation method

Abstract

The invention discloses a ferroelectric floating gate memory unit string and a preparation method thereof, and the ferroelectric floating gate memory unit string is characterized in that a channel layer is arranged on the upper side of an insulating substrate, a tunneling dielectric layer is arranged on the channel layer, and a composite unit is arranged on the upper side of the tunneling dielectric layer; the composite unit comprises a floating gate metal layer, a ferroelectric dielectric layer and a first control gate metal layer which are sequentially arranged from bottom to top, and at least two ends of the floating gate metal layer and the first control gate metal layer are covered with first insulating dielectric layers; and a source electrode metal layer and a drain electrode metallayer are embedded at two ends of the upper side of the insulating substrate. According to the ferroelectric floating gate memory unit string provided by the invention, electronic behaviors are controlled through the floating gate metal layer, the constraint effect of a ferroelectric polarization electric field generated by the ferroelectric dielectric layer on charges can be maximized, the storage time is effectively prolonged, the response time is reduced, and the overall performance of the ferroelectric floating gate memory unit string is improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, in particular to a ferroelectric floating gate memory unit string and a preparation method. Background technique [0002] The continuous update of the semiconductor manufacturing process makes the integration of the current integrated circuit higher and higher, and the storage density of the storage device is also higher and higher. At present, the industry generally uses silicon-based devices as units of floating gate memories, and integrated structures of two-dimensional memory devices and three-dimensional memory devices have been developed. [0003] However, with the improvement of integration density, the feature scale of the device is continuously shrinking, including the channel length of the transistor and the thickness of various dielectric layers. Therefore, the short channel effect caused by the reduction of the feature size and the leakage of the floating gate layer caused by ...

AI Technical Summary

Problems solved by technology

[0005] To sum up, the defects of the existing technology are: the existing transistor has short channel effect, and there is leakage phenomenon of the floating gate layer, which greatly restricts the switching ratio and holding time of the floating gate storage device.

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