Integrated chip of enhanced and depletion type HEMT device and preparation method

Abstract

The invention relates to an integrated chip of an enhanced and depletion type HEMT (High Electron Mobility Transistor) device and a preparation method. The correlation between the influence of the stress of a dielectric layer on the threshold voltage of the device and the gate line width of the device is used to regulate and control the stress of a barrier layer below a P-type nitride gate layer and change the polarization electric field intensity of the barrier layer. Finally, monolithic integration of P-type nitride gate enhanced and depletion type HEMT devices is realized. When the depletion type semiconductor device is prepared, the P type nitride layer below the gate metal does not need to be etched, etching damage does not exist on the contact interface of the gate metal and the semiconductor, gate electric leakage of the device can be effectively reduced, the switching current ratio of the device is increased, and power consumption is reduced. Compared with a conventional P-type nitride gate enhanced HEMT, the enhanced semiconductor device prepared by the invention has the advantages that the polarization electric field intensity of the barrier layer below the P-type nitride gate layer is weakened, the polarization charge surface density of a heterojunction interface is reduced, and the threshold voltage of the enhanced semiconductor device is further improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, and more specifically relates to an integrated chip of an enhanced and depleted HEMT device, and a method for preparing the integrated chip of an enhanced and depleted HEMT device. Background technique [0002] Due to its superior characteristics, silicon-based GaN HEMTs have broad development prospects in the field of power switches. Among them, commercial power GaN HEMTs are mainly P-type nitride gate enhancement HEMT devices. However, due to the low threshold voltage and small gate swing of P-type nitride gate-enhanced HEMT devices, in order to give full play to the advantages of GaN materials, it is necessary to monolithically integrate the gate drive circuit with the power GaN HEMT. [0003] In the prior art, based on the p-GaN / AlGaN / GaN epitaxial structure, a common method for achieving monolithic integration of enhancement-mode and depletion-mode semiconductor devices is: using a dr...

AI Technical Summary

Problems solved by technology

[0004] However, when the depletion-mode GaN HEMT device is prepared by completely etching the P-type nitride layer in the above method, there is dry etching damage on the surface of the AlGaN layer below the gate region, which will cause a large amount of damage on the surface of the AlGaN layer. Defects, resulting in uneven distribution of device threshold voltage and large gate leakage current

At the same time, the enhanced HEMT device prepared by selectively etching the P-type nitride layer has a low threshold voltage. In actual circuit applications, there is a risk of false turn-on, which affects circuit safety.

Images