80results about How to "Reduce gate leakage" patented technology

A sensor for use in the detection of a molecular interaction comprises a field effect transistor (FET) having a core structure and an extended gate structure, the core structure and the extended gate structure being located on substantially separate regions of a substrate, the extended gate structure including an exposed metal sensor electrode on which probe molecules can be immobilized, wherein, in use, the sensor is operative to produce a change in an electrical characteristic of the FET in response to molecular interaction at the exposed surface of the metal sensor electrode. The sensor is particularly suitable for detecting biomolecular interactions such as the hybridization of DNA, when the sensor is prepared with suitable probe molecules immobilized on the exposed gate metal.

A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This dispersion is large enough to reduce the peak electric field in the channel, but low enough in order not to cause a significant decrease in the output power of the device. In this design, the whole transistor is passivated against dispersion with the exception of a small region 50 to 100 nm wide right next to the drain side of the gate. In that region, surface traps cause limited amounts of dispersion, that will spread the high electric field under the gate edge, therefore increasing the breakdown voltage. Three different methods to introduce dispersion in the 50 nm closest to the gate are described: (1) introduction of a small gap between the passivation and the gate metal, (2) gradually reducing the thickness of the passivation, and (3) gradually reducing the thickness of the AlGaN cap layer in the region close the gate.

An SRAM device and a method of operating an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) a sleep mode voltage controller configured to provide both an array high supply voltage V_ADD that is lower than a high operating voltage V_DD and an array low supply voltage V_ASS that is higher than a low operating voltage V_SS to the SRAM array during a sleep mode.

A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A first BOX region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a second BOX region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.

A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric. The insertion of the band-gap disrupting dielectric results in lower gate leakage without resulting in any substantial changes in the threshold voltage characteristics and effective oxide thickness.

A novel technique to quench electrical defects in CVD Al₂O₃ layers is disclosed. A small amount of silicon dopant to the aluminum oxide film reduces the leakage current as well as the gap interface trap density at the dielectric/silicon interface. The implanted silicon gives a better interface and improves the leakage characteristics of the dielectric.

A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate, forming a transistor in the substrate, the transistor having a gate structure that includes a dummy gate structure, forming an inter-layer dielectric (ILD), performing a first chemical mechanical polishing (CMP) to expose a top surface of the dummy gate structure, removing a portion of the ILD such that a top surface of the ILD is at a distance below the top surface of the dummy gate structure, forming a material layer over the ILD and dummy gate structure, performing a second CMP on the material layer to expose the top surface of the dummy gate structure, removing the dummy gate structure thereby forming a trench, forming a metal layer to fill in the trench, and performing a third CMP that substantially stops at the top surface of the ILD.

A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.

The invention belongs to the semiconductor material and device field and discloses a GaN-based field effect transistor with a high quality MIS structure and a preparation method of the GaN-based field effect transistor, in particular, a GaN MISFET device gate dielectric layer and an improvement method of a dielectric layer and GaN interface. The device includes a substrate, an epitaxial layer grown on the substrate as well as a gate electrode, a source electrode, a drain electrode and an insulating layer; the epitaxial layer includes a stress buffer layer which is formed through primary epitaxial growth, a GaN epitaxial layer as well as a second epitaxial layer and a third epitaxial layer which are grown on selective regions on the GaN epitaxial layer; a GaN/AlGaN heterostructure is formed through secondary epitaxial growth, and groove channels are formed; an AlN thin layer is formed through third epitaxial growth; the AlN thin layer is partially oxidized so as to form an AlN/oxide dielectric layer stack structure; gate metal covers the groove channels; a source electrode region and a drain electrode region are formed at two ends; and the source electrode region and the drain electrode region are covered with metal, so that the source electrode and the drain electrode can be formed. The device and preparation process of the invention are simple and reliable. With the preparation method adopted, the high quality MIS structure can be formed, and the performance of the GaN MISFET device can be improved. The preparation method can play a key role in decreasing the electric leakage of the gate electrode, decreasing the resistance of the channels and stabilizing threshold voltage.

An enhancement-depletion-mode inverter includes a load transistor and a drive transistor. The load transistor has a top gate architecture with a first source, a first drain, a load channel region, a first semiconductor layer, and a first gate electrode. A load gate dielectric is in the load channel region, and has a load dielectric thickness. The load transistor is configured to operate in a depletion mode. The drive transistor has a bottom gate architecture with a second source, a second drain, a drive channel region, a second semiconductor layer, and a second gate electrode. A drive gate dielectric is in the drive channel region, and has a drive dielectric thickness that is different from the load dielectric thickness. The drive transistor is configured to operate in a normal mode or an enhancement mode. The first source is electrically connected to the second drain and the first gate.

A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.