217results about How to "Improve short channel effect" patented technology

A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device includes a doped substrate having an epitaxial layer thereover having source and drain implant regions and body and lightly doped drain regions formed therein. The channel region and lightly doped drain regions are doped to a depth to abut the top surface of the substrate. In alternative embodiments, a buffer region of the second conductivity type and having dopant concentration greater than or equal to about the channel region is formed over the top surface of the substrate between the top surface of the substrate and the channel region and lightly doped drain region, wherein the channel region and lightly doped drain regions are doped to a depth to abut the buffer region.

A semiconductor device and related method of manufacture are disclosed. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on opposite sides of the gate electrode within the active region. The spaces are formed by etching a semiconductor layer formed below the gate electrode in the active region.

A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a trench having a sidewall and a bottom using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the trench to form a doped region. The semiconductor substrate underlying the trench is etched to form an extended portion. A gate insulating layer is formed on the trench and the extended portion. A trench gate is formed in the trench and the extended portion.

The method of manufacturing a recess type MOS transistor improves a refresh characteristic. In the method, a channel impurity region is formed by ion implanting a first conductive impurity in an active region of a semiconductor substrate. Thereon, a second conductive impurity and the first conductive impurity are ion-implanted each alternately into the active region, to thus sequentially form first to third impurity regions having a dual diode structure on the channel impurity region, the second conductive impurity having conductivity opposite to the first conductive impurity. A trench is formed, and a gate insulation layer is formed in a gate region to produce a gate stack. The first conductive impurity is selectively ion-implanted in a source region, to thus form a fourth impurity region. A spacer is then formed in a sidewall of the gate stack, and the second conductive impurity is ion-implanted in the source/drain regions, to form a fifth impurity region.

The invention relates to a semiconductor device and a manufacture method thereof, wherein the manufacture method comprises the following steps of: providing a semiconductor underlay; etching the semiconductor underlay so as to form a barrier region block; forming barrier walls at both sides of the barrier region block; forming an underlay coating on the semiconductor underlay, wherein the barrier walls and the surface of the underlay coating have fall; forming a gate oxide and a grid electrode on the underlay coating and the semiconductor underlay; carrying out low-doping ion implantation in the semiconductor underlay; carrying out rapid thermal annealing to form a low-doping source/drain region in the semiconductor underlay; forming isolation layers at opposite sides of the gate oxide and the grid electrode; and forming a heavy-doping source/drain region in the semiconductor underlay. The invention has technical scheme that the barrier walls are formed in the semiconductor underlay, thereby effectively separating the interpenetration between the source region and the drain region, obviously improving the short channel effect of the semiconductor device, avoiding the generation of a punch-through effect between the source region and the drain region and improving the electrical behaviour of the semiconductor device. Meanwhile, a bigger process regulating space is provided for the reduction of junction capacitance and the enlargement of process window in the ultra shallow junction process.

A method for manufacturing a semiconductor memory apparatus may include forming a channel region and a gate region through a self-alignment etching process on a cell region; and forming a three-dimensional multi-channel region through an etching process using a first multi-channel mask on a core region and a peripheral region and forming a gate region through an etching process using a second multi-channel mask, thereby preventing mis-arrangement of gates.

The present invention relates to a SON MOSFET and method of manufacturing the same, in which a blister is formed within a silicon substrate, thus improving the disadvantages of a bulk structure and a Silicon-On-Insulator (SOI) structure at the same time. The SON MOSFET according to the present invention comprises isolation insulating films formed at both upper sides of a silicon substrate, a gate insulating film and a gate electrode that are sequentially formed on a surface of the silicon substrate between the isolation insulating films, a source region and a drain region that are formed on the silicon substrate between the gate insulating film and the isolation insulating films, a blister formed within the silicon substrate under the gate insulating film, and a silicon channel, which is surrounded by the blister, the source region and the drain region, within the silicon substrate, wherein the blister is formed of hydrogen or helium ion.

Provided are an MOS transistor and a forming method thereof. The method for forming the MOS transistor comprises the steps of providing a semiconductor substrate and enabling the surface of the semiconductor substrate to be provided with a grid structure; etching the semiconductor substrate on two sides of the grid structure to form grooves; forming a diffusion barrier layer on the surface of a side wall of one side of each groove close to the grid structure, enabling the diffusion barrier layer to cover two sides of a channel area; and forming sources and drains in the grooves. The method for forming the MOS transistor can improve short channel effect of the transistor and improve performance of the transistor.

A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.

The present disclosure provides a superjunction based design for normally-OFF HEMT that has two key components: (i) a recessed high-K metal gate and (ii) a superjunction layer under the gate, which is embedded within the N-type GaN buffer layers and separated from recessed gate. Recess gate is to deplete the 2DEG from the channel region (under the gate) when the transistor is under OFF state. The present disclosure provides a new, improved, efficient and technically advanced HEMT device which can provide higher breakdown voltage, when compared to designs available in the prior-art, without affecting the performance figure of merits. Further, the new HEMT device offers improved breakdown voltage as compared to ON-resistance trade-off, improved the short channel effects, improved gate control over channel, improved switching speed for a given breakdown voltage, and improved device reliability. Furthermore, the new HEMT device lowers gate-to-drain (miller) capacitance and is available at low cost.

A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.

The invention discloses a nitride power transistor and a manufacturing method thereof. The nitride power transistor comprises a silicon substrate, a nitride nucleating layer which is arranged on the silicon substrate, a nitride buffering layer which is arranged on the nitride nucleating layer, a nitride channel layer which is arranged on the nitride buffering layer, a source and a drain which are in contact with the nitride channel layer, and a grid which is arranged between the source and the drain, wherein the silicon substrate comprises a differently doped semiconductor composite structure which is used for forming a space charge depletion region. By introducing the differently doped semiconductor compound structure which can form the space charge depletion region in the silicon substrate of the nitride power transistor, the nitride power transistor is enabled to be able to withstand higher external voltage and the breakdown voltage of a device is improved.

A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.

A non-volatile integrated circuit memory device includes a substrate including first and second source/drain regions therein and a channel region therebetween, a first memory cell on the channel region adjacent the first source/drain region, and a second memory cell on the channel region adjacent the second source/drain region. The first memory cell includes a first conductive gate on the channel region and a first multi-layered charge storage structure therebetween. Similarly, the second memory cell includes a second conductive gate on the channel region and a second multi-layered charge storage structure therebetween. A single-layer insulating layer on the channel region extends between the first and second memory cells along sidewalls thereof. The single-layer insulating layer may not include a charge-trapping layer, and may separate the first and second conductive gates by a distance of less than a thickness of the first multi-layered charge storage structure. Related fabrication methods are also discussed.

The invention provides a method for manufacturing an MOS transistor. The method provides a substrate including a gate structure. Then a pre-non-crystallization technology is carried out and a non-crystallization region is formed in the substrate at two sides of the gate structure; the co-injection technology is carried out, and the impurity for co-injection is injected in the non-crystallization region. A first ion injection technology and a first quick-annealing technology are carried out in such a manner that a slight-doping drain electrode is formed. Finally, a separation wall is respectively formed at two sides of the gate structure in such a manner that a source cathode or a drain electrode is formed.

The invention provides a manufacturing method of a metal-oxide-semiconductor field effect transistor (MOSFET), comprising the following steps: manufacturing a hard mask on the surface of a silicon substrate on a source region and a drain region before a conductive channel is formed, and carrying out ion implantation at twice from different angles by using the hard mask as a shield in the process for forming the conductive channel through ion implantation to form a nonuniform conductive channel, thus, the doping concentration of the part of the conductive channel near the edge of the drain region is reduced on the premise that the whole doping concentration of the nonuniform conductive channel is not remarkably changed, on the one hand, the short channel effect of the MOSFET is prevented from increasing, and on the other hand, the band-gap tunneling effect and drain leakage current are reduced, shutdown current is reduced, and the service life of the MOSFET device is prolonged.

An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a lightly doped source and drain (LDD) region that acts as an etch stop. The LDD region may act as an etch stop during an etching process implemented to form a recess in the substrate that defines a source and drain region of the device.