Nonplanar device with thinned lower body portion and method of fabrication

Abstract

A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to the field of semiconductor devices and more particularly to a nonplanar tri-gate transistor having a thinned lower body portion and method of fabrication. [0003] 2. Discussion of Related Art [0004] In order to increase the performance of modern integrated circuits, such as microprocessors, silicon on insulator (SOI) transistors have been proposed. Silicon on insulator (SOI) transistors have an advantage in that they can be operated in a fully depleted manner. Fully depleted transistors have an advantage of ideal subthreshold gradients for optimized ON current / OFF current ratios. [0005] An example of a proposed SOI transistor which can be operated in a fully depleted manner is a tri-gate transistor 100, such as illustrated in FIG. 1. Tri-gate transistor 100 includes a silicon body 104 formed on an insulating substrate 102 having a buried oxide layer 103 formed on a monocrystalline sil...

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Problems solved by technology

Unfortunately, the fourth side, the bottom part of the channel is isolated from the g

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