Semiconductor apparatus and method for fabricating the same

Abstract

The invention provides a semiconductor apparatus and method for fabricating the same. The method comprises providing a substrate comprising a first material; forming at least one gate stack over the substrate; forming one or more recesses in the substrate, wherein the one or more recesses define at least one source region and at least one drain region; and forming a pocket, a first layer comprising a second material, and a second layer comprising a third material in the one or more recesses, the pocket being disposed between the first layer and the substrate. The pockets 234 of the invention,essentially providing an abrupt junction between the source / drain region and substrate interface, may lead to significant improvement in SCEs (short channel effect) and / or reduce current leakage. Improvement in SCEs can allow continual semiconductor device scaling down. Further, in the present embodiment, the method may reduce strain relaxation within the SiGe portions of the source / drain regions, which can improve the performance of semiconductor device. the invention also reduces the channel doping degree.

Description

technical field [0001] The present invention relates to a manufacturing method of a semiconductor device, in particular to a manufacturing method of a semiconductor device related to improving device performance and / or improving control of short channel effect. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in successive generations of IC production, each with smaller and more complex circuits than the previous generation. However, these advances have also increased the complexity of the manufacturing IC process, so the IC process also needs to have the same progress in order to achieve a more advanced integrated circuit IC process. [0003] In the course of IC innovation, functional density (ie, the number of interconnected devices per wafer area) has generally increased, while geometry size (ie, the smallest element (or line) that can be created ...

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Problems solved by technology

However, these advances have also increased the complexity of the manufacturing IC process, so the IC process needs to have the same progress to achieve more advanced integrated circuit IC process

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