Disclosed is a strain vertical MOS device manufacturing method. The method comprises the steps of conducting pattern transfer on a substrate, forming a metal mask, forming a silicon column through etching, reducing the diameter of the silicon column, preparing silicon nanowires and growing a gate oxide layer; conducting polycrystalline silicon deposition, doping and foreign ion activation to form an annular grid electrode; depositing a stress silicon nitride film outside the grid electrode to form a stress liner layer; conducting ion injection to form a drain terminal n- doping area; conducting ion injection on the peripheral annular area of the substrate to form a drain terminal n+ doping area; conducting P+ ion injection on the upper portions of the silicon nanowires to form a Halo doping structure, and conducting n type ion injection to form a source terminal; depositing metal and alloy. According to the method, the grid-control capacity of devices in a nanometer node integrated circuit is improved, the short-channel effect and hot carrier effect are restrained, carrier mobility is improved, current driving capacity is improved, the size of the devices is reduced on the premise that the performance of the devices is not reduced, and then requirements for miniaturization of the devices are met.