30results about How to "Reduced impact ionization" patented technology

A field effect transistor comprising a silicon containing body is provided. After formation of a gate dielectric, gate electrode, and a first gate spacer, a drain side trench is formed and filled with a wide band gap semiconductor material. Optionally, a source side trench may be formed and filled with a silicon germanium alloy to enhance an on-current of the field effect transistor. Halo implantation and source and drain ion implantation are performed to form various doped regions. Since the wide band gap semiconductor material as a wider band gap than that of silicon, impact ionization is reduced due to the use of the wide band gap semiconductor material in the drain, and consequently, a breakdown voltage of the field effect transistor is increased compared to transistors employing silicon in the drain region.

A MOSFET device for RF applications that uses a trench gate in place of the lateral gate used in lateral MOSFET devices is described. The trench gate in the devices of the invention is provided with a single, short channel for high frequency gain. The device of the invention is also provided with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Such features allow these devices to maintain the advantages of the LDMOS structure (better linearity), thereby increasing the RF power gain. The trench gate LDMOS of the invention also reduces the hot carrier effects when compared to regular LDMOS devices by reducing the peak electric field and impact ionization. Thus, the devices of the invention will have a better breakdown capability.

A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a depth. A non-amorphizing implantation implants dopants of the same conductivity type into the semiconductor body. This ion implantation step implants dopants throughout the defect area. The dopants can then be activated by heating the semiconductor body for less than 10 ms, e.g., using a flash anneal or a laser anneal.

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) preparation method for efficiently collecting substrate current, wherein the method comprises the following steps: adopting standard preparation technology of LDMOS, and realizing the LSMOS capable of efficiently collecting the substrate current just through the following layout design, namely, using an active region, an N-type drift region and a P-type body region to form the drain region, the source region and the body leading-out region of an LDMOS device; defining a channel region by using polycrystalline; and realizing the drain electrode, the source electrode and the body leading-out electrode by using N+ injection and P+ injection. The regions used for source electrode leading-out N+ injection and the regions used for body leading-out P+ injection are arranged alternatively in the source region. In the invention, the body leading-out position is closer to the channel region formed by a hot carrier and the corresponding substrate current; therefore, the substrate current can be more efficiently collected, parasitical NPN (Negative-Positive-Negative) bipolar transistor is prevented from being turned on due to overlarge substrate current, the device is prevented from entering Snapback state for burning, and the purpose of enlarging safe work area of the LDMOS is achieved.

The invention relates to a lateral double-diffused metal oxide semiconductor device. The lateral double-diffused metal oxide semiconductor device comprises a device part, a terminal part and a P type substrate; a high-voltage N type region, an N type drift region, a P type body region 4A1 and a P type body region 4A2 are arranged over the P type substrate; the P type body region 4A1 is positioned in the device part; the P type body region 4A2 is positioned in the terminal part, and formed by diffusion of the P type body region 4A1 in the device part; a gate oxidization layer and a polycrystalline silicon gate field plate are also arranged over the high-voltage N type region; the device part further comprises an N type drain region, an N type source region, a P type region and a metal contact, wherein a shallow trench isolation region is arranged in the N type drift region; the shallow trench isolation region is shaped as a straight bar; the shallow trench isolation region extends to the terminal part from the device part; namely, the width of the shallow trench isolation region is the same as that of the N type drift region; and furthermore, the N type drain region, the N type source region, the P type region and the metal contact are not arranged over the P type body region 4A2 and the N type drift region of the terminal part. By means of the lateral double-diffused metal oxide semiconductor device disclosed by the invention, the breakdown voltage is improved when various performance parameters of an LDMOS device are kept same.

The invention discloses an LDMOS device which comprises a P-type epitaxial layer, an N-well, a P-well, a first N-type drift region, a first P-type layer, a second N-type drift region, a second P-type layer, a gate oxide layer and gate polysilicon. The P-well, the second N-type drift region, the first N-type drift region and the N-well are sequentially contiguous from left to right at the upper part of the P-type epitaxial layer. The second N-type drift region is shallower than the first N-type drift region. The second P-type layer is adjacent to the lower part of the second N-type drift region. The first P-type layer is adjacent to the lower part of the first N-type drift region. The second P-type layer is shallower than the first P-type layer. The second P-type layer has a higher doping concentration than the first P-type layer. The invention further discloses a manufacturing method for the LDMOS device. According to the invention, the LDMOS device has lower on-resistance, and can satisfy off-state breakdown voltage and on-state breakdown voltage at the same time.

The invention provides a LDMOS (Lateral Diffusion MOS) structure. The LDMOS structure comprises a semiconductor substrate, a first drift area and a second drift area which are located in the semiconductor substrate and are arranged separately, a source which is located in the first drift area, a drain which is located in the second drift area, a gate structure which is located on the semiconductorsubstrate and whose two sides are contacted with the first drift area and the second drift area respectively, a first isolation structure which is located in the first drift area and isolates the source and the gate structure, and a second isolation structure which is located in the second drift area and isolates the drain and the gate structure, wherein both the first isolation structure and thesecond isolation structure are provided with floating field plates. One or more floating field plates is arranged on the isolation structures between the source-gate and the drain-gate, the area of adepleted area can be increased, collision ionization can be reduced, higher breakdown voltage and saturation leakage current Idsat can thus be acquired, and the gate-drain capacitance Cgd and the gate-source capacitance Cgs of the device are not deteriorated.

The invention proposes a half-cell structure of a gate power MOSFET anti-single-particle-burnout device. According to the structure, an N-type buffer layer with an N-type local doped region is manufactured in the drain (cathode) electrode region of a semiconductor power device, which can significantly reduce the electric field peak and impact ionization degree of a semiconductor power device driftregion and high and low junctions of a substrate. The number of carriers generated by avalanche multiplication caused by impact ionization can be reduced. The transient current acting on a parasiticbipolar transistor is greatly reduced, so that the parasitic bipolar transistor is difficultly turned on. The device's ability to resist single particle burnout can be improved without sacrificing basic electrical characteristics.

The invention belongs to the technical field of semiconductor devices, and in particular relates to a hybrid PIN Schottky diode and a preparation method thereof. The hybrid PIN Schottky diode disclosed by the invention comprises a GaN substrate, a GaN epitaxial layer, a rectangular-ambulatory-plane GaN structure array, a double-edge terminal structure and a first metal structure, wherein the GaN epitaxial layer is formed on the GaN substrate; the rectangular-ambulatory-plane GaN structure array comprises a plurality of rectangular-ambulatory-plane GaN structures adjacent to each other and is formed on the GaN epitaxial layer; each rectangular-ambulatory-plane GaN structure comprises a GaN peripheral region and a GaN central region; the double-edge terminal structure is positioned on the periphery of the rectangular-ambulatory-plane GaN structure array and comprises a whole edge terminal compensation layer and a partial edge terminal compensation layer, wherein the whole edge terminal compensation layer is positioned on the partial edge terminal compensation layer; and the first metal structure is positioned on the rectangular-ambulatory-plane GaN structure array and is in Schottky contact with the GaN peripheral region. The relatively high reverse breakdown voltage can be obtained in the event that the area of a chip cannot be lost; simultaneously, the problem that the device performance is degraded due to the dislocation problem can be avoided; and thus, the hybrid PIN Schottky diode and the preparation method thereof disclosed by the invention can be well applied in the field of power electronics.

This invention provides an LDMOS device and a manufacturing method thereof. The LDMOS device comprises a semiconductor substrate, a body region and a drift region arranged in the semiconductor substrate, a gate arranged on the semiconductor substrate and a drain electrode arranged in the drift region, and the drift region also comprises a drift blocking part which blocks drift region hot carrier drift. According to the LDMOS device and the manufacturing method, the drift of a hot carrier to a gate direction can be blocked by the drift blocking part arranged at the drift region, the electric field intensity under the gate can be reduced, the position of strongest electric field generation moves downward to be far from the gate oxide layer of the gate. The electric field intensity is reduced, the breakdown voltage of the drift region is raised, and the generation of impact ionization is reduced, which means that the number of hot carrier generation is reduced. Since the position of the strongest electric field moves downward, the distance to the gate oxide layer is increased, the number of the hot carriers which act on the gate oxide layer actually is reduced, thus the effect of blocking the hot carriers is realized finally, and the reliability of the device is improved.

Each of cells arranged on a substrate surface along a first direction includes at least one unit transistor. Collector electrodes are arranged between two adjacent cells. A first cell, which is at least one of the cells, includes unit transistors arranged along the first direction. The unit transistors are connected in parallel to each another. In the first cell, the base electrode and the emitter electrode in each unit transistor are arranged along the first direction, and the order of arrangement of the base electrode and the emitter electrode is the same among the unit transistors. When looking at one first cell, a maximum value of distances in the first direction between the emitter electrodes of two adjacent unit transistors in the first cell being looked at is shorter than ½ of a shorter one of distances between the first cell being looked at and adjacent cells.

The invention discloses a power device single particle burnout resistant reinforced structure and a preparation method thereof. The method comprises the steps of arranging an N-type multi-buffer layer region structure in a drain electrode region of a semiconductor power device; forming a groove at a source electrode and a neck region electrode and forming a metal electrode; arranging an integrated transistor below the neck region; and arranging an N-type field stop layer between a P-type body region and a drift region. By adopting the technical scheme of the invention, the electric field peak value and collision ionization at the homojunction of a drift region and a substrate of the semiconductor power device can be greatly reduced, the number of carriers generated by avalanche multiplication caused by collision ionization is reduced, and meanwhile, the current density in the device is greatly reduced, so that the heat generated by a current heat effect is reduced, and the SEB safe working voltage of the device is remarkably improved.