30results about How to "Reduced impact ionization" patented technology

A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a depth. A non-amorphizing implantation implants dopants of the same conductivity type into the semiconductor body. This ion implantation step implants dopants throughout the defect area. The dopants can then be activated by heating the semiconductor body for less than 10 ms, e.g., using a flash anneal or a laser anneal.

The invention provides a transverse insulated gate bipolar transistor with high thermal carrier reliability, which comprises a P-type substrate with a buried oxide layer. An N-type epitaxial layer is provided on the buried oxide layer. In the N-type epitaxial layer, an N-type buffer well and a P-type body region are provided. In the N-type buffer well, a P-type positive region is provided. In the P-type body region, an N-type negative region and a P-type body contact region are provided. The surface of the N-type epitaxial layer is provided with a gate oxide layer and a field oxide layer. A polysilicon gate is provided on the surface of the gate oxide layer, and polysilicon is arranged on the right upper surface of the field oxide layer. The P-type positive region consists of block shaped N-type regions arranged in rows; in the N-type buffer region, a floating hollow N-type contact region is provided. The P-type positive region is arranged in the floating hollow N-type contact region, and each of the block shaped N-type regions is surrounded by the floating hollow N-type contact region on three sides. And the other end of the field oxide layer extends toward the P-type positive region and ends at the floating hollow N-type contact region. According to the invention, it is possible to reduce the emission efficiency of a parasitic PNP transistor, reduce the hot carrier damage in the on-state and the switching state, and improve the reliability of devices.

The invention discloses a power device anti-single event burning reinforced structure electrode and a preparation method thereof. An N-type multi-buffer layer structure is arranged in the drain electrode region of a semiconductor power device; a groove is formed at the source electrode and the neck region electrode and A metal electrode is formed; an integrated transistor is arranged under the neck region; an N-type field stop layer is arranged between the P-type body region and the drift region. Adopting the technical scheme of the present invention can greatly reduce the electric field peak value and impact ionization at the drift region of the semiconductor power device and the substrate homojunction, and reduce the number of carriers generated by the avalanche multiplication caused by the impact ionization; The current density is greatly reduced, thereby reducing the heat generated by the thermal effect of the current, and the SEB safe working voltage of the device is significantly improved.

Nanoscale field-emission devices are presented, wherein the devices include at least a pair of electrodes separated by a gap through which field emission of electrons from one electrode to the other occurs. The gap is dimensioned such that only a low voltage is required to induce field emission. As a result, the emitted electrons energy that is below the ionization potential of the gas or gasses that reside within the gap. In some embodiments, the gap is small enough that the distance between the electrodes is shorter than the mean-free path of electrons in air at atmospheric pressure. As a result, the field-emission devices do not require a vacuum environment for operation.

The invention relates to a GaN planar Gunn diode based on a composite heat dissipation anode and a preparation method thereof. The planar Gunn diode comprises: an AlGaN back barrier layer; a GaN channel layer located on the AlGaN back barrier layer; an AlGaN barrier layer, located on the GaN channel layer; ohmic contact anode and ohmic contact cathode, respectively located at the two ends of the AlGaN back barrier layer, the GaN channel layer and the AlGaN barrier layer; and Schottky The extension layer is located on the AlGaN barrier layer and covers the ohmic contact anode. The planar Gunn diode Schottky extension forms a depletion layer in the channel of the planar Gunn diode, which weakens the strength of the high-energy dipole domains, thereby dissipating the energy of the electronic domains and lowering the anode terminal of the planar Gunn diode. The impact ionization buffers the generation of heat, thereby effectively suppressing the self-heating effect of the device, and improving the negative resistance effect, power and frequency of the device.

The invention belongs to the technical field of semiconductor devices, and in particular relates to a hybrid PIN Schottky diode and a preparation method thereof. The hybrid PIN Schottky diode disclosed by the invention comprises a GaN substrate, a GaN epitaxial layer, a rectangular-ambulatory-plane GaN structure array, a double-edge terminal structure and a first metal structure, wherein the GaN epitaxial layer is formed on the GaN substrate; the rectangular-ambulatory-plane GaN structure array comprises a plurality of rectangular-ambulatory-plane GaN structures adjacent to each other and is formed on the GaN epitaxial layer; each rectangular-ambulatory-plane GaN structure comprises a GaN peripheral region and a GaN central region; the double-edge terminal structure is positioned on the periphery of the rectangular-ambulatory-plane GaN structure array and comprises a whole edge terminal compensation layer and a partial edge terminal compensation layer, wherein the whole edge terminal compensation layer is positioned on the partial edge terminal compensation layer; and the first metal structure is positioned on the rectangular-ambulatory-plane GaN structure array and is in Schottky contact with the GaN peripheral region. The relatively high reverse breakdown voltage can be obtained in the event that the area of a chip cannot be lost; simultaneously, the problem that the device performance is degraded due to the dislocation problem can be avoided; and thus, the hybrid PIN Schottky diode and the preparation method thereof disclosed by the invention can be well applied in the field of power electronics.

The invention discloses an LDMOS device which comprises a P-type epitaxial layer, an N-well, a P-well, a first N-type drift region, a first P-type layer, a second N-type drift region, a second P-type layer, a gate oxide layer and gate polysilicon. The P-well, the second N-type drift region, the first N-type drift region and the N-well are sequentially contiguous from left to right at the upper part of the P-type epitaxial layer. The second N-type drift region is shallower than the first N-type drift region. The second P-type layer is adjacent to the lower part of the second N-type drift region. The first P-type layer is adjacent to the lower part of the first N-type drift region. The second P-type layer is shallower than the first P-type layer. The second P-type layer has a higher doping concentration than the first P-type layer. The invention further discloses a manufacturing method for the LDMOS device. According to the invention, the LDMOS device has lower on-resistance, and can satisfy off-state breakdown voltage and on-state breakdown voltage at the same time.

Nanoscale field-emission devices are presented, wherein the devices include at least a pair of electrodes separated by a gap through which field emission of electrons from one electrode to the other occurs. The gap is dimensioned such that only a low voltage is required to induce field emission. As a result, the emitted electrons energy that is below the ionization potential of the gas or gasses that reside within the gap. In some embodiments, the gap is small enough that the distance between the electrodes is shorter than the mean-free path of electrons in air at atmospheric pressure. As a result, the field-emission devices do not require a vacuum environment for operation.

Disclosed relates to multi electric potential field electrode plate high-pressured N-typed metal oxide semiconductor of high-voltaged component, comprising N-typed substrate, P-typed epitaxial layer, source and drain, multi- silicon polycrystal, field oxide layer and oxide layer, silicon polycrystal field electrode plate above field oxide layer and between drain and silicon polycrystal gate , which is connected to drain. The invention brings in silicon polycrystal field electrode plate with the same electric potential of drain end, which makes the surface of floating area deviation area below silicon polycrystal field electrode plate in accumulation condition of current carrier, greatly reducing peak electric field between drain end and silicon polycrystal field electrode plate when in operation work condition and impact ionization of current carrier on drain end, so Kirk effect(the effect of breakdown voltage reduction caused by electric field accumulating under large current ) is notably decreased, breakdown voltage and area of safe operation are increased.