30 results about "Gate source capacitance" patented technology

The application relates to a power device and a preparation method thereof and electronic equipment. The device comprises a substrate, a first surface of the substrate comprising an epitaxial layer; the epitaxial layer comprising source regions, base regions and shielding regions arranged along a first direction towards the substrate via a top surface; a plurality of gates spaced along a second direction parallel to the first surface and penetrating the source regions and the base regions along the first direction and partially embedded in the shielding regions; the gate comprising a gate conductive layer and a gate oxide layer arranged along the first direction; an interlayer dielectric layer located on the top surface of the epitaxial layer and comprising an extension penetrating the gate conductive layer along the first direction and in contact with the gate oxide layer; and a metal layer located on the top surface of the interlayer dielectric layer and comprising a first source electrode extending into the gate via the top surface of the extension; the width and depth of the first source electrode being related to the gate-source capacitance of the power device. The channel density can be ensured while improving the reliability of the gate oxide layer.

The invention provides a silicon carbide power switch driving circuit, and relates to the technical field of power electronic driving, the silicon carbide power switch driving circuit comprises a pulse generation module, an isolation transformer and a driving output module, the pulse generation module converts an input direct current voltage into an alternating pulse voltage with dead time and outputs the alternating pulse voltage to a primary winding of the isolation transformer; the driving output module comprises a charging loop, an active discharge loop and a discharge resistor assembly, the active discharge loop comprises a normally-on switch tube, the control end of the normally-on switch tube is connected with one winding section of the secondary winding, and a discharge path bypassing the secondary winding is provided for the gate-source capacitor in the dead zone time. The discharge resistor assembly comprises a first discharge resistor and a second discharge resistor which are arranged in series and located outside and inside the active discharge loop respectively. The discharge falling edge is effectively accelerated, the contradiction of mutual restriction of the discharge speed and oscillation suppression is solved, the structure is simple, and the cost is low.

The embodiment of the present disclosure provides a kind of measurement method and device for the background carrier concentration of high electron mobility transistor, belong to semiconductor technical field.The measurement method includes: obtaining unit area reference capacitance and the first measured gate-source capacitance of HEMT, unit area reference capacitance is the capacitance of unit area laminated structure, and the film layer stack structure of laminated structure is identical with the film layer stack structure of HEMT;According to unit area reference capacitance and the first measured gate-source capacitance, determine the equivalent gate-source capacitance area of HEMT;According to the first measured gate-source capacitance and equivalent gate-source capacitance area, determine the unit area calibration capacitance of HEMT;According to unit area calibration capacitance and the channel depth of HEMT, determine the background carrier concentration of HEMT.The embodiment of the present disclosure can effectively improve the accuracy of the background carrier concentration of HEMT measured.

During formation of a nanostructure field-effect transistor (NSFET) device, a dielectric wall is used to cut the replacement gate structure into separate replacement gate structures. The dielectric wall may be formed by replacing a portion of the replacement gate structure disposed between two adjacent fins / channel stacks / stacked nanostructures with one or more dielectric materials. The dielectric wall reduces the size of the replacement gate structure, thereby reducing the gate-source capacitance (e.g., a parasitic capacitance), which in turn reduces the RC delay and the power consumption of the device formed. Due to the self-aligned manner of formation for the dielectric wall, the distance between adjacent fins / channel stacks / stacked nanostructures can be scaled down further to achieve higher level of integration.

The invention discloses a super junction device, which is characterized in that a super junction structure is at least formed in an active region, device unit structures are formed in the active region, each device unit structure comprises a gate unit structure, and each gate unit structure forms a two-dimensional mesh gate structure. The two-dimensional mesh gate structure comprises a plurality of first gate strips which extend in a first direction and are arranged in parallel, and a first gate spacer region is arranged between every two adjacent first gate strips. A plurality of second gate segments and grid regions located between the second gate segments are formed in each first gate spacer region, and a forming region of each device unit structure comprises a corresponding grid region; and each second grid section is also connected with the first grid strips on the two sides, and grid connection nodes are formed at the connection positions. According to the invention, the gate parasitic capacitance such as the gate source capacitance and the gate drain capacitance can be improved, and the synchronization level of each device unit structure, namely the primitive cell, can be improved at the same time, so that the voltage and current overshoot can be inhibited, and the EMI can be reduced.

The invention discloses an electronic device, a working method, a power amplifier and communication equipment, relates to the technical field of communication, and is used for improving efficiency and linearity. The electronic device comprises a first HEMT device, a second HEMT device, a first grid electrode, a second grid electrode, a source electrode and a drain electrode, the first grid electrode is connected with the grid electrode of the first HEMT device and the source electrode of the second HEMT device, the source electrode of the electronic device is connected with the source electrode of the first HEMT device, the drain electrode of the electronic device is connected with the drain electrode of the first HEMT device, and the second grid electrode is connected with the grid electrode of the second HEMT device. The drain of the second HEMT device is electrically floating, and the gate-source capacitance of the first HEMT device can be compensated through the source-gate capacitance of the second HEMT device, so that the sum of the capacitance values of the source-gate capacitance of the second HEMT device and the gate-source capacitance of the first HEMT device is kept unchanged along with the change of the voltage of the first gate, and the efficiency and the linearity are improved.

The invention provides a shield gate MOSFET and a forming method thereof, and the method comprises the steps: providing an epitaxial layer, and forming a shield gate trench in the epitaxial layer; forming an ONO layer on the inner wall of the shield gate trench, wherein the ONO layer comprises a first oxide layer, a nitride layer and a second oxide layer which are sequentially stacked from the inner wall of the shield gate polysilicon; forming shield gate polycrystalline silicon at the lower part of the shield gate groove, wherein the shield gate polycrystalline silicon is separated from the inner wall of the shield gate groove through an ONO layer; forming a dielectric layer on the surface of the shield gate polycrystalline silicon, wherein the dielectric layer fills the upper part of the shield gate groove; removing a part of the nitride layer on the shield gate trench to form second trenches on the two sides of the dielectric layer; and forming second gate polycrystalline silicon in the second groove. According to the invention, the relative area of the isolation layer between the second gate polycrystalline silicon and the shield gate polycrystalline silicon is reduced, so that the gate source capacitance is reduced, and the switching speed is improved.

A process that exhibits: Discharging a gate-source capacitance (C GS ) of a transistor device (1) from a first voltage level (V1) to a second voltage level (V2) when a first resistor (21) is connected in parallel to the gate-source capacitance (C GS ) is switched on, and measuring a first discharge time (T1) in connection with the discharge; Discharge of the gate-source capacitance (C GS ) from the first voltage level (V1) to the second voltage level (V2) when the first resistor (21) and a second resistor (22) are connected in parallel to the gate-source capacitance (C GS ) are switched on, and measuring a second discharge time (T2) in connection with the discharge; Comparing the ratio between the first discharge time (T1) and the second discharge time (T2) with a predefined threshold; and Detecting a fault based on comparison.

This invention discloses a method for establishing and extracting a charge model for HEMT transistors based on GaN technology, comprising: obtaining the gate-channel voltage based on externally input gate voltage, drain potential, and source potential; obtaining the gate charge based on gate charge density, number of gate elements, gate length, and width of a single gate element; obtaining the drain-source potential difference based on the drain potential and source potential; establishing a charge model based on the gate-channel voltage, gate charge, and drain-source potential difference to characterize the correlation between charge value and drain-source voltage after the transistor device is turned on; and differentiating the charge value of the charge model to establish a capacitance model to characterize the correlation between gate-source capacitance, gate-source voltage, and drain-source voltage. This invention supports the charge / capacitance description of HEMT transistors based on GaN technology, especially the description of the relationship between gate-source capacitance, gate-source voltage, and drain-source voltage after the channel is turned on, with high model accuracy.

The application discloses a kind of high drive IO power supply burr processing circuits, by setting multiple IO modules and ESD protection modules on chip base guide, IO module includes first delay drive circuit and second delay drive circuit, level conversion unit receives the digital square wave signal input by digital signal input end, respectively obtains DRP signal and DRN signal by DRP signal processing unit and DRN signal processing unit processing, DRP signal and DRN signal drive multiple MOS in each group of effective delay circuit in turn and obtain square wave signal, digital signal output unit is processed to the square wave signal of surge protection unit and is output to first delay drive circuit, utilize the gate-source capacitance of drive pipe and resistance and form multiple groups of effective delay circuit, ensure that effective delay is formed between each group of effective delay circuit, solve the influence of through current to power supply from IO module inside, solve IO to power supply in combination with chip layout processing, enhance power anti-interference performance.

The invention provides a small signal model of an InP-based HEMT (High Electron Mobility Transistor) device and a parameter extraction method of the small signal model. The model comprises a stray capacitor between gate and drain bonding pads, a stray capacitor between gate and source bonding pads, a stray capacitor between drain and source bonding pads, a gate stray resistor, a gate stray inductor, a drain stray resistor, a drain stray inductor, a capacitor between gate and drain electrodes, a capacitor between gate and source electrodes and a capacitor between drain and source electrodes. An intrinsic gate-source capacitor, an intrinsic gate-drain capacitor, an intrinsic drain-source capacitor, an inter-gate-drain leakage resistor, an inter-gate-source leakage resistor, an output resistor, an intrinsic channel resistor, an intrinsic transconductance and a delay factor are included. Aiming at the working frequency of a device in a millimeter wave band, an improved small signal model is established, distributed model establishment is carried out on parasitic capacitance between bonding pads and parasitic capacitance between tube cores, four auxiliary structures are combined, parameter extraction of parasitic elements such as the parasitic capacitance between the bonding pads and the parasitic capacitance between the tube cores is respectively carried out, and the reliability of the device is improved. Therefore, the precision of the millimeter wave band small signal model is improved.

The invention discloses a display panel and a display device.The display panel comprises a data line, a scanning line, a shared electrode line, a main pixel electrode, a secondary pixel electrode, a first transistor, a second transistor and a third transistor, and a first active part of the first transistor and a second active part of the second transistor are arranged on the same layer and connected into an integrated structure; the overlapping area between the source and drain electrodes of the first transistor and the second transistor and the scanning line can be reduced, so that the difference between the gate-source capacitance of the first transistor and the gate-source capacitance of the third transistor can be reduced, and the difference between the charge transmission efficiency of the first transistor and the charge transmission efficiency of the third transistor is reduced; therefore, the brightness uniformity of the display panel can be improved.

The present invention relates to the technical field of semiconductors, and more specifically, relates to a shielded-gate trench power device and a preparation method therefor. The method comprises: preparing a semiconductor wafer to be processed; depositing gate polysilicon on the upper surface of an epitaxial layer and a trench structure of the semiconductor wafer, such that a recess is formed above the trench structure; etching the gate polysilicon in the recess until an oxide layer above source polysilicon is reached, so as to form two sub-gates, wherein an inter-gate trench is formed between the two sub-gates; planarizing the gate polysilicon until the oxide layer on the surface of the epitaxial layer is exposed; forming an oxide-film dielectric layer, which covers the oxide layer covering the upper surface of the epitaxial layer, and the gate polysilicon; and planarizing the oxide-film dielectric layer, so as to obtain a flat surface of the oxide-film dielectric layer. The shielded-gate trench power device and the preparation method therefor provided by the present invention enable the adjustment of the gate-source overlap area, thereby reducing the gate-source capacitance, and increasing the degree of freedom in device preparation.

The invention discloses a bridge arm crosstalk suppression circuit for reducing reverse conduction loss of a GaN device, and belongs to the technical field of power electronics and electricians. According to the circuit, a negative voltage circuit capable of inhibiting forward crosstalk is connected in series in a driving circuit, an auxiliary MOS tube is connected in series in a reverse direction on the driving positive voltage circuit, and the negative voltage circuit is isolated from the driving circuit by controlling the auxiliary MOS tube to be switched on in dead time, so that the reverse conduction loss is reduced. When forward crosstalk is generated, the auxiliary MOS tube is controlled to be switched off, the negative voltage circuit is connected to the driving circuit, negative voltage is provided for a gate source capacitor of the GaN device, meanwhile, a low-impedance loop is provided for forward crosstalk current, and forward bridge arm crosstalk is restrained. When negative crosstalk is generated, a low-impedance loop is provided for negative crosstalk current, and negative bridge arm crosstalk is suppressed. The reverse conduction loss of the GaN device can be reduced while positive and negative crosstalk is suppressed, and the method is suitable for all bridge arm type circuit topologies.

Provides an easily adjustable protection circuit. [Solution] The protection circuit 10 according to the first aspect includes a switch F1 which is an FET connected between the battery BTT and the load 30, and the protection circuit 10 turns off (shuts off) the switch F1 when an overvoltage is applied from the battery BTT, and comprises a voltage detection unit 11 for detecting the overvoltage, a resistor R5 which is the gate-source resistance of the switch F1, a capacitor C1 which is the gate-source capacitor of the switch F1, and a diode D1 connected between the gate of the switch F1 and ground.

Provided in the present disclosure are a gate drive circuit and an electronic device, which are applied to the technical field of semiconductor process devices. The circuit comprises a first switching circuit, a second switching circuit and a charging circuit, wherein a first input end of the first switching circuit receives a power supply signal, a second input end receives a drive signal, and an output end is connected to an input end of the charging circuit; a first input end of the second switching circuit is grounded, a second input end is used for receiving a drive signal, and an output end is connected to the input end of the charging circuit; an output end of the charging circuit is configured to be connected to a gate of a target switching transistor; the first switching circuit and the second switching circuit are alternately switched on; and the charging circuit is configured to forwardly charge a gate-source capacitor when the first switching circuit is switched on, so as to drive the target switching transistor to switch on, and to reversely charge the gate-source capacitor when the second switching circuit is switched on, so as to drive the target switching transistor to switch off. Therefore, the circuit requires only one power supply to control the conduction state of the target switching transistor, which can effectively reduce the overall cost of the circuit.

The invention belongs to the technical field of semiconductor power devices, and particularly relates to an asymmetric single-channel planar SiC MOSFET device and a preparation method thereof. According to the asymmetric single-channel planar SiC MOSFET device and the preparation method thereof, an island barrier layer does not need to be reserved on the N + layer, a photolithography mask is not needed either, a traditional symmetric double-channel cell is changed into a single-channel cell, the surface current uniformity is improved, and the reliability such as the short-circuit capability is improved. In addition, due to the fact that only a single channel exists, the polycrystalline grid does not need to cover a JFET area, the gate-oxide electric field intensity is reduced, the gate-oxide reliability is improved, meanwhile, the gate-source capacitance and the gate-drain capacitance are reduced, and therefore the dynamic loss of the device is reduced.

The invention discloses a non-volatile computing storage array based on a 1FeFET-1C structure and a parasitic capacitance compensation method, and aims to solve the problems of array output linearity reduction and sensing margin reduction caused by mode dependence on capacitance change in the prior art and realize accurate evaluation and optimization of large-scale CiM array performance. The compensation method comprises the steps that a FeFET device model containing a GAA nanowire channel and fully surrounding a ferroelectric layer is established on a TCAD platform, and equivalent fixed charges are introduced into the interface of a semiconductor and the ferroelectric layer to simulate the polarization state of a low-threshold LVT and the polarization state of a high-threshold HVT respectively; in different polarization states, extracting gate-source capacitance and gate-drain stray capacitance of the FeFET device and interconnection coupling capacitance between a bit line and a word line; the device-level parasitic parameters are integrated into an array simulation model comprising a 1FeFET-1C memory cell to evaluate the influence of parasitic characteristics on the linearity and sensing margin of the array output voltage.

The invention provides a diamond-based gallium nitride device with patterned source and drain electrodes and a preparation method of the diamond-based gallium nitride device, and relates to the technical field of gallium nitride HEMT devices. At least one first ohmic contact region with the area smaller than that of the drain electrode is arranged below the drain electrode; the first ohmic contact regions are distributed in the direction perpendicular to the source-drain connecting lines; in the active region, a non-uniformly distributed current path is formed between the first ohmic contact region with a smaller area and the source electrode ohmic contact region; the internal electric field of the device is adjusted by changing the distribution of the ohmic contact region, and the change of gate-source capacitance is realized, so that the linearity of the device is adjusted, and the flexible adjustment of the linearity of the device is realized. And channel electrons flow from the ohmic contact region of the source electrode to the ohmic contact region of the drain electrode, and channel current is non-uniformly distributed in the active region of the device, so that the temperature distribution of the device is optimized, the channel peak temperature of the device is reduced, and the reliable service life of the device is prolonged.

The application provides a method for reducing gate-source capacitance, which comprises the following steps: epitaxially forming an epitaxial layer on a substrate; forming a gate trench on the top of the epitaxial layer, and forming a first gate dielectric layer and a first polysilicon gate on the first gate dielectric layer at the bottom of the gate trench; forming an isolation layer on the first polysilicon gate and the first gate dielectric layer; forming a second gate dielectric layer on the sidewall of the remaining gate trench and the epitaxial layer; forming a second polysilicon gate to fill the remaining gate trench, and grinding the second polysilicon gate to the second gate dielectric layer; etching back the second polysilicon gate, so that the second trench gate forms a groove with a depth of 1000-2000 angstroms at the gate trench; and judging whether the thickness of the second gate dielectric layer on the step at the top of the gate trench is less than a target value, and if yes, forming an etching protection layer on the epitaxial layer and the groove. The input capacitance value of the wafer level test of the process of the application is about 10% lower than that of the prior art process.

The present application relates to the technical field of communications, and discloses an electronic apparatus, a working method, a power amplifier and a communication device, used for improving efficiency and linearity. The electronic apparatus comprises a first HEMT apparatus, a second HEMT apparatus, a first gate, a second gate, a source, and a drain. The first gate is connected to a gate of the first HEMT apparatus and a source of the second HEMT apparatus; the source of the electronic apparatus is connected to a source of the first HEMT apparatus; the drain of the electronic apparatus is connected to a drain of the first HEMT apparatus; the second gate is connected to a gate of the second HEMT apparatus; and a drain of the second HEMT apparatus is electrically floating. The gate-to-source capacitance of the first HEMT apparatus is compensated by the gate-to-source capacitance of the second HEMT apparatus, such that the sum of the gate-to-source capacitance of the second HEMT apparatus and the gate-to-source capacitance of the first HEMT apparatus remains constant as the voltage of the first gate changes, improving efficiency and linearity.

This invention discloses an on-chip compact dual-core dual-path quality factor enhancement source degradation fully differential low-noise amplifier, comprising four MOS transistors, gate-source capacitors, DC blocking capacitors, bias resistors, and inductors. Four source half-turn inductors form a first transformer, and two gate-end inductors coupled together form a second transformer, which is nested within the first transformer. The first and second transformers constitute a multiplexed four-turn coupled transformer, simultaneously achieving source degradation imaginary and real part matching within the same transformer area. In differential operation, the currents in both signal paths enhance the magnetic flux, improving the effective inductance and quality factor of the inductors. This achieves on-chip integration of gate-end inductors in the Sub-6GHz band, optimizing noise, gain, and area efficiency.

In an example, a circuit includes a high side output transistor having a control terminal coupled to a first capacitor, and includes a low side output transistor having a control terminal coupled to a second capacitor and a balancing capacitor. The circuit includes a first differential input stage configured to receive a differential input and provide a first output current to the control terminal of the high side output transistor. The circuit includes a second differential input stage configured to receive the differential input and provide a second output current to the control terminal of the low side output transistor. The circuit includes a floating battery coupled to the control terminal of the high side output transistor and the control terminal of the low side output transistor. The balancing capacitor balances a gate-to-source capacitance of the low side output transistor with a gate-to-source capacitance of the high side output transistor.

The application provides a shielded gate trench MOSFET and a manufacturing method thereof, which comprises a drain layer, a first epitaxial layer, a second epitaxial layer, a first trench, a second trench, a first dielectric layer, a source conductive layer, a gate trench, a gate dielectric layer, a gate conductive layer, a body region, a source region, a source line layer and a gate line layer. The application connects the source conductive layer, the source region and the body region to the source line layer through a via, connects the gate conductive layer of part of the trench to the gate line layer through a hole, and connects the gate conductive layer of adjacent trenches to the source line layer through a via, so as to reduce the zero temperature coefficient cross point of the device, improve the working capacity of the device in the linear working area, significantly reduce the gate capacitance and the gate-source capacitance of the device, improve the switching frequency of the device, and enable the device to be applied to application occasions requiring higher switching frequency. In addition, the manufacturing method of the application is compatible with the manufacturing process of common structures, and does not increase additional cost.

The invention provides a diamond-based gallium nitride device of an ohmic Schottky electrode and a preparation method of the diamond-based gallium nitride device, and relates to the technical field of gallium nitride HEMT devices. At least one first ohmic contact region with the area smaller than that of the source electrode is arranged below the source electrode; the first ohmic contact regions are distributed in the direction perpendicular to the source-drain connecting lines; each first ohmic contact region and the drain ohmic contact region form a plurality of current paths; on one hand, the Schottky source electrode with the ohmic contact region is added with the Schottky electrode part, a Schottky barrier is introduced, gate leakage is reduced, and therefore the sub-threshold characteristic of the device is improved; and on the other hand, by changing the distribution of the ohmic contact region of the source electrode, the electric field distribution in the device can be adjusted, the gate-source capacitance and the channel current path can be changed, channel electrons flow to the ohmic contact drain electrode from the ohmic contact region of the source electrode, the channel current is non-uniformly distributed in the active region of the device, and the flexible adjustment of the linearity of the device is realized.

The invention discloses an SGT device which is characterized in that a source field plate is formed in a bottom region of a gate trench of a device unit structure, and a field plate dielectric layer is isolated between the source field plate and the inner side surface of the gate trench. A first dielectric layer is formed on the bottom surface of a top trench formed by the gate trenches on the top surface of the source field plate, and a gate dielectric layer and a gate conductive material layer with a side wall structure are formed on the side surface of the top trench. And a first spacer region is arranged between the gate conductive material layers on the side surfaces of the two sides of the gate trench and is filled with a second dielectric layer. The first spacer region is located right above the top surface of the source field plate, and the area covered by the first spacer region is larger than the position area of the top surface of the source field plate. The invention further provides a manufacturing method of the SGT device. According to the invention, the width of the gate conductive material layer can be reduced under the condition that the gate trench has a relatively wide width, so that the process complexity of the gate conductive material layer can be reduced, and the gate-drain capacitance and the gate-source capacitance can be reduced at the same time.

A single-channel, single-poly floating gate (EEPROM-type) memristor including asymmetric source / drain-to-gate coupling and an asymmetric channel doping pattern. Asymmetric source / drain-to-gate coupling is achieved by configuring the drain, source and floating gate such that the gate-to-drain capacitance is greater than the gate-to-source capacitance. The asymmetric channel doping pattern is implemented by forming different drain-side and source-side doping portions (i.e., different N-type or P-type implant configurations and / or positions). The asymmetric channel doping pattern is preferably formed using standard CMOS implants (e.g., NLDD and P-type pocket implants). Multiple N-type and P-type implants may be selectively positioned to achieve a desired balance between program / erase speeds, reverse (read direction) threshold voltage and immunity to read-disturb and over-erase. A drain-side diode may be additionally used to suppress over-erase. A memory circuit including multiple two-terminal memristors disposed in a cross-point array is disclosed, which can be utilized, e.g., in a neuromorphic circuit.

The application discloses a preparation method of a shield gate trench power device, a semiconductor structure for the shield gate trench power device, and the shield gate trench power device. The method comprises the following steps: providing a semiconductor substrate, forming a trench in the semiconductor substrate, and forming a first oxide layer on the surface of the substrate and the sidewall of the trench; filling polycrystalline silicon in the trench, and the surface of the polycrystalline silicon is lower than the upper surface of the first oxide layer on the surface of the substrate; forming a sidewall on the sidewall of the trench above the polycrystalline silicon; taking the sidewall as a hard mask, etching the polycrystalline silicon in the trench to a first depth; etching the first oxide layer of the sidewall of the trench to a second depth, and the second depth is smaller than the first depth; removing the sidewall, and performing thermal oxidation to form an oxide layer on the exposed part in the trench; and filling polycrystalline silicon in the first depth part and the second depth part of the trench. The scheme provided by the application can reduce the gate-source capacitance, thereby improving the opening speed of the device.

The display panel comprises a grid electrode part, a source electrode part and drain electrode parts, the drain electrode parts are located on the two sides of the source electrode part in the column direction, the area of orthographic projection of the drain electrode parts on a substrate is reduced, and therefore the capacitance of the drain electrode parts is reduced. The two ends of the source electrode part clamped between the two drain electrode parts extend to exceed the edge of the gate electrode part in the row direction, even if the source electrode part deviates to a certain degree relative to the gate electrode part in the row direction, the gate-source capacitance value of each driving transistor can still be kept consistent, the gate electrode part does not need to be independently provided with a gate-source capacitance compensation part, and the cost is reduced. Therefore, the capacitance of the gate portion is reduced. In conclusion, the display panel can reduce the capacitance of the grid line and the capacitance of the drain electrode part while ensuring the display image quality, so that the capacitance of the driving transistor is smaller, and the condition that the display image flickers is reduced or eliminated. The invention further provides a display device comprising the display panel.

The invention discloses an on-chip compact dual-core dual-path quality factor enhanced source electrode degeneration fully-differential low noise amplifier, which comprises four MOS (Metal Oxide Semiconductor) tubes, a gate-source capacitor, a blocking capacitor, a bias resistor and an inductor, four source electrode half-circle inductors form a first transformer, two gate end inductors are coupled to form a second transformer, and the two gate end inductors are coupled to form a second transformer. The second transformer is nested in the first transformer, the first transformer and the second transformer form a multiplexing type four-ring coupling transformer, and matching of a source electrode degeneration imaginary part and a source electrode degeneration real part is achieved at the same time in the same transformer area. During differential work, currents of the two signal paths enhance magnetic flux in the same direction, the effective inductance value and the quality factor of the inductor are improved, on-chip integration of the Sub-6GHz frequency band gate end inductor is achieved, and noise, gain and area efficiency are optimized.