Semiconductor device and manufacturing method therefor

Abstract

The invention provides a semiconductor device and a manufacturing method therefor. The device comprises a substrate, a semiconductor layer positioned on the substrate, a source electrode and a drain electrode positioned on the semiconductor layer, and a grid electrode positioned between the source electrode and the drain electrode, and a source field plate positioned on the semiconductor layer, wherein a groove is formed in the semiconductor layer between the grid electrode and the drain electrode; and the source field plate comprises a beginning part electrically connected with the source electrode, a first middle part, a second middle part covering the semiconductor layer between the grid electrode and the drain electrode, and a tail part, wherein air exists between the first middle part and the semiconductor layer, and between the tail part and the semiconductor layer. According to the semiconductor device, the overlay deviation between the groove and the source field plate can be eliminated, so that the production cost can be saved, and parasitic gate source capacitance and parasitic resistance are reduced as well.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof. Background technique [0002] HEMT (High Electron Mobility Transistor, High Electron Mobility Transistor) device working under high drain-source voltage, the electric field lines near the side of the gate near the drain end are very dense, which will form a high electric field peak, and the high electric field in this local area can It causes a very large gate leakage current, even leads to material breakdown, and the device fails, thereby reducing the breakdown voltage of the device, and the higher the electric field peak, the smaller the breakdown voltage that the device can withstand. At the same time, with the increase of time, the high electric field will also cause the degradation and denaturation of the dielectric layer or semiconductor material layer on the surface of the device, which will affect the reliabi...

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Problems solved by technology

[0004] However, in the above-mentioned semiconductor device, the source field plate 111 directly covers the second dielectric layer 110, and the metal of the source field plate 111 with a large area completely overlaps with the gate 108 below it and the two-dimensional electron gas in the channel, resulting in a parasitic gate The source capacitance, the parasitic gate-source capacitance is inversely proportional to the distance between the source field plate 111 and the gate 108, and is proportional to the overlapping area between the source field plate 111 and the gate 108, and the dielectric constant of the dielectric layer is relatively large, Therefore, a large parasitic gate-source capacitance Cgs will be generated during the operation of the device, resulting in the deterioration of the frequency characteristics of the device, and because the source field plate 111 is generally connected to the lowest potential, it will affect the distribution of the two-dimensional electron gas below it, making the two-dimensional electron gas Expanding into the channel layer reduces the concentration of two-dimensional electron gas in the channel, thereby generating parasitic resistance, which makes the on-resistance increase during the working process of the device

And affected by the thickness of the dielectric layer, the source field plate 111 is far away from the strong electric field area, and the modulation effect on the strong electric field is limited. Thinning the thickness of the dielectric layer can improve the electric field modulation effect of the source field plate 111, but the parasitic gate-source capacitance and parasitic resistance It will increase, and thickening the thickness of the dielectric layer can reduce the parasitic gate-source capacitance and parasitic resistance, but it will further weaken the electric field modulation effect. Too thick dielectric layer materials will also increase the difficulty of the process, and the thickness of the dielectric layer is generally passed through Designed and debugged, not easy to change

[0005] One improvement method is to design an air-isolated source-field plate structure. The source-field plate structure uses metal arch support to span the gate, gate-source region and part of the gate-drain region above the dielectric layer. Air is used for isolation in the middle. The field plate spans the gate, the gate-source region and part of the gate-drain region and then covers the dielectric layer of the gate-drain region to modulate the electric field distribution in the gate-drain region. This structure greatly reduces the parasitic gate-source capacitance and parasitic resistance. , but it does not solve the problem that the source field plate is far away from the strong electric field area, and the modulation effect on the strong electric field is limited

[0006] Another improvement method is to carve a groove on the dielectric layer between the gate and drain to form a grooved source field plate, which uses the characteristics of the grooved source field plate to be close to the strong electric field area to strengthen the modulation of the strong electric field, but the groove structure and source The relative position of the field plate structure is formed by two photolithography processes, which will introduce an overlay deviation between the groove structure and the source field plate, which will affect the design result and yield, and also increase the production cost, and the groove source If the field plate is too close to the channel two-dimensional electron gas, the parasitic gate-source capacitance and parasitic resistance will increase

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