Method for improving breakdown voltage of N-groove laterally diffused metal oxide semiconductor (LDMOS)

Abstract

The invention discloses a method for improving breakdown voltage of an N-groove laterally diffused metal oxide semiconductor (LDMOS). The method comprises the following steps of:1, manufacturing a deep N well (DNW), implanting phosphorus into a P-type substrate (P SUB), and performing high-temperature drive-in and forming; 2, performing thermal growth to form field oxide, manufacturing a P well, and implanting boron impurities once or for multiple times; 3, manufacturing a PTOP, implanting boron impurities and forming after well implantation is finished and before gate oxide is grown; 4, manufacturing a polycrystalline silicon gate and a polycrystalline silicon field plate; after gate oxide is grown, depositing a layer of polycrystalline silicon, and defining the positions of the polycrystalline silicon gate and the field plate by etching; and manufacturing a source and a drain, after the polycrystalline silicon gate is formed, implanting phosphorus or arsenic into a device region once or for multiple times by using the polycrystalline silicon gate and the field oxide as hard masks, and implanting boron once or for multiple times to form P+ which is required by the P well. The impact ionization of the thinnest position of the device can be reduced, so that voltage resistance of the device can be improved.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor device. Background technique [0002] The structure of the existing N-channel laterally diffused metal oxide semiconductor NLDMOS is usually as follows figure 1 As shown, this structure usually concentrates the electric field at the beak of the LOCOS near the source, so the focus of optimizing NLDMOS is to use various methods to reduce the electric field intensity here. [0003] As shown in the figure, the usual way to optimize BV is to change the length LA of polysilicon on the deep N-well DNW, the length PF of polysilicon on the selective oxidation of silicon LOCOS, and the distance PA of polysilicon from the boundary of selective oxidation of silicon LOCOS. But just adjusting these dimensions, sometimes the OFF BV and ON BV of the device cannot reach the target value at the same time. Contents of the invention [0004] The technical problem to be solved by the present invention i...

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Problems solved by technology

But just adjusting these dimensions, sometimes the OFF BV and ON BV of the device cannot reach the target value at the same time

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