73results about How to "Improve safe work area" patented technology

The invention discloses a novel large-current silicon on insulator lateral insulated gate bipolar transistor. According to the semiconductor, a buried oxide is arranged on a P-type substrate, an N-type drift region is arranged on the buried oxide, a P-type body region and an N-type buffer region are arranged on the N-type drift region, the N-type buffer region is internally provided with a P-type collector region, a collector metal is connected onto the P-type collector region, a field oxygen layer is arranged above the N-type drift region, the P-type body region is internally provided with a P-type emitter region, an N-type emitter region is arranged around, an emitter metal is connected onto the N-type emitter region and the P-type emitter region, a gate oxide is arranged between the field oxygen layer and the N-type emitter region, a first polysilicon layer is arranged on the surface of the gate oxide, a first gate metal is connected onto the surface of the first polysilicon layer, a longitudinal groove is arranged outside the P-type body region, the longitudinal groove is internally provided with silicon dioxide and a second polysilicon layer coated by other medium, and a second gate metal is connected onto the second polysilicon layer.

The invention provides a crosswise DMOS with cupped source electrode contact and a method for forming the crosswise DMOS. The crosswise DMOS comprises a cupped source electrode contact, wherein the cupped source electrode contact comprises a cupped part which longitudinally extends and penetrates the source area of the crosswise DMOS and contacts the body area,and the cupped part is electrically coupled with the source area and the body area. The crosswise DMOS not only has smaller size, but also is low in production cost.

The invention discloses an insulate gate bipolar transistor (IGBT) with a current carrier storage layer and an additional hole passage, and belongs to the technical field of semiconductor power devices. In the IGBT, an N-type current carrier storage layer (5) and a large P<+> tagma (4) structure are introduced on the basis of a conventional planar non-pouch-through IGBT. The N-type current carrier storage layer (5) improves a conductivity modulation effect close to an emitter and the large P<+> tagma (4) structure plays a role in providing an additional passage for a hole so that the latch-up resistance is improved. Due to the design of the N-type current carrier storage layer (5) and the large P<+> tagma (4), the flow path of a hole current of the conventional IGBT is optimized, so that a safety operation area of a device is enlarged and the sensitivity of latch current density to a temperature is reduced.

The invention provides a high-voltage MOS device, which at least includes a grid, a source and a drift region, wherein, the device further includes at least two field plates which are mutually separated with certain distance and are distributed at the upper surface of the drift region, the field plate which is nearest to the grid is connected with the source, and the other field plate is connected with the grid. The two field plates are both composed of polysilicon layers, and the thickness is the same as the thickness of the polysilicon layers. The lengths of the two filed plates can be same or different. The length of the field plate is decided by the doping level of the drift area, the lower the doping level of the drift area is, the longer the filed plate is, and the length of the filed plate is not more than one third of the length of the drift region. The length of the field plate is more than one sixth and less than one fourth of the length of the drift region. Compared with the prior art, the device of the invention can improve breakdown voltage and reduce on-resistance, the speed of the device is not affected and safe working area is larger.

The invention discloses a fast recovery diode and a manufacturing method of the fast recovery diode. The diode disclosed by the invention comprises an anodic diffusion P-type doped region, an evenly-doped intrinsic region, a cathodic diffusion N-type region, anode and cathode metal layers, wherein the anodic diffusion P-type doped region is a P-type doped region provided with alternated high and low concentrations and formed by locally pouring through a mask plate. Compared with the prior art, the diode disclosed by the invention has the characteristics of low inverse peak current IRRM, short reverse recovery time trr and high reverse recovery softness.

The invention provides a slot simulated gate bipolar transistor, which belongs to the technical field of semiconductor power devices. Based on the prior slot simulated gate bipolar transistor, the invention is additionally provided with a P<+> hole collecting zone (5), to avoid holes entering a P type zone (6) and achieve good action of bypassing the holes, thereby greatly weakening the parasitic thyristor effect, improving the safety operation zone of the device and particularly improving the high-temperature latching resistance of the device. Simultaneously, a metal emitter (8) of the invention is made into a slot metal electrode. Besides the reduction of the contact resistance of the device, the device can dissipate heat more easily and reduces temperature rise, thereby achieving excellent high-temperature operating characteristics. Furthermore, During the injection of the P<+> hole collecting zone(5) and an N<+> source(7) of the slot simulated gate bipolar transistor, an additional masking plate is needed, thereby properly lowering production cost.

An accumulation layer controlled thyristor, which belongs to the technical field of semiconductor power devices, is characterized in that the on/off of the thyristor can be controlled by stopping electron circulation through an electron barrier of an internal electric field formed in a P bypass region and an N depletion region. When a positive voltage is applied on a gate, an accumulation layer is formed at the interface between the N depletion region (33) and a gate oxide layer (6); an electron inversion channel is formed in a P-type base region (8); and electrons pass through an N active region (9), the accumulation layer, an N layer (200), and the electron inversion channel to the an N base region (3), thereby controlling the normal operation of the device. The accumulation layer controlled thyristor as the substitute of the conventional gate controlled thyristors, such as MOS controlled thyristors, has the advantages of lower conduction voltage drop, larger saturation current density, no parasitic effect, and greatly improved safety operation area, and can overcome the disadvantages of the conventional gate-controlled thyristors, such as the deficiency of current saturation characteristic and poor turn-off capability.

The invention provides a high voltage semiconductor device and a manufacture method thereof; the device comprises a first dope type semiconductor substrate, a second dope type epitaxial layer arranged on the semiconductor substrate, a second dope type high voltage well positioned in the epitaxial layer, a second dope type deep well positioned in the high voltage well, a first dope type reduced-field layer positioned on the surface of the epitaxial layer and/or in the epitaxial layer (wherein at least a part of the reduced-field layer is positioned in the deep well), a first dope type first well parallel to the high voltage well and positioned in the epitaxial layer, a second dope type source electrode ohmic contact zone arranged in the first well, a drain electrode ohmic contact zone arranged in the deep well, a grid electrode close to the source electrode ohmic contact zone and at least covering the epitaxial layer between the source electrode ohmic contact zone and the high voltage well. The high voltage semiconductor device and the manufacture method thereof can effectively reduce technical manufacture difficulty, improve device parameter characteristics, and improve device reliability.

This invention relates to the power semiconductor field, providing a trench gate IGBT device with carrier storage which is used for solving the problems of high saturation voltage, small short circuitsafe working area and limited concentration of the existing trench gate IGBT device with carrier storage layer, and put forward a novel trench gate IGBT device with carrier storage layer. The trenchgate IGBT device with carrier storage layer directly integrates a plurality of series diodes on the surface of silicon wafers to clamp the potential of the electric field shielding layer in the P region, thereby breaking the concentration limit of CSL on the basis of trench gate IGBT process, greatly improving the injection efficiency of IGBT emitter and greatly improving the trade-off relation between forward voltage drop and turn-off loss of IGBT. Meanwhile, due to the clamping effect of the diode, the drain near the IGBT nMOS channel is clamped at a lower voltage under high voltage and large current, thereby greatly reducing the saturation current of the novel IGBT and improving the short circuit safe working area of IGBT.

The invention relates to the field of power semiconductors, provides an IGBT device with a carrier storage layer using diode clamping, and solves the problems that the saturation voltage of an existing groove gate IGBT with the carrier storage layer (CSL) is high, a short circuit safe working area is smaller, and the CSL concentration is limited. The IGBT device with the carrier storage layer using diode clamping has the advantages that the IGBT directly integrates one or more series diodes on the surface of a silicon wafer through a groove gate IGBT process for clamping electric potential ofan electric field shielding layer of a P region, on the basis of the groove gate IGBT process, the limitation of the CSL concentration is broken through, the injection efficiency of an IGBT emitting electrode is greatly improved, thereby greatly improving the tradeoff relationship between conduction voltage drop and turn-off loss of the IGBT; due to the clamping action of a diode, a drain electrode near an nMOS channel of the IGBT is clamped at a lower voltage under the high voltage and large current, so that saturation current of the novel IGBT is reduced to a great extent, thereby enlargingthe short circuit safe working area of the IGBT.

The invention belongs to the field of an intelligent power device and a control device, in particular relates to a magnetic balanced harmonic elimination reactive compensation device and a method. According to the device and the method, three-phase unbalanced data of a circuit is acquired by a detector and is also stored and processed, the state of a load diverter switch on a load circuit is controlled so as to control access states of two branches connected with the detector, wherein one branch is provided with a magnetic balanced harmonic elimination device, the detector controls the load diverter switch to have access to the magnetic balanced harmonic elimination device according to power quality on a detection circuit of the detector when an exception occurs, and the original branch is cut off so as to perform magnetic balanced harmonic elimination. The method and the device have the following advantages that: 1, power supply quality is timely and accurately detected to reach economic operation, and operation loss of the original electromagnetic balanced power saver is effectively reduced; 2, switching in and switching out are convenient so as to guarantee power supply; 3, no-load loss can be effectively reduced; and 4, the device and the method are applicable for a place where a load condition is complicated and harmonic wave of a power grid is high, and power supply reliability is increased.

The invention discloses a diode device and a manufacturing method thereof, and belongs to the technical field of power semiconductor devices. A cellular structure of the device comprises a metal negative electrode, an N+ substrate and an N- epitaxial layer; a trench structure is arranged on the two sides of the top layer of the epitaxial layer; the trench structure comprises a P-type semiconductorregion and a heterogeneous semiconductor from the bottom up; the top layer of the N-epitaxial layer is also provided with a P-type body region, an N+ source region and a P+ contact region; the N+ source region, the P-type body region, a part of the N- epitaxial layer and the heterogeneous semiconductor are in contact through a dielectric layer of the side wall of the trench; the surface of the device is covered with a metal positive electrode; and the heterogeneous semiconductor, the dielectric layer, the source region, the body region and the epitaxial layer form an ultra-potential barrier structure. By virtue of the diode device and the manufacturing method thereof, the problems of high forward opening voltage, poor reverse recovery capability and the like existing in the existing PIN diode device can be solved; and in addition, lower electric leakage and a larger safe working region are achieved on the premise that the withstand voltage is not affected, and the reliability of the device is improved.

The invention relates to a novel plastic packaging structure for a power MOS. The novel plastic packaging structure comprises a frame, a chip, and a packaging body. The frame is a copper frame having two parts; one part of the copper frame is used as a piece of slide glass and is connected with a back electrode of a device and a pin is led out to form electrical connection; and the other part of the copper frame is a cooling back panel for realizing a heat radiation function; and the two parts are isolated from each other by a high-thermal-conduction isolation layer, so that the two parts of the copper frame are in physical connection. According to the invention, because the slide glass and the cooling panel are independent parts isolated from each other and the slide glass is used for electrical connection and the cooling panel is used for providing a cooling channel, PCB assembling becomes convenient and the packaging thermal resistance of the power MOS can be reduced, and the security working zone at an application terminal is enhanced; and advantages of high power and low power consumption of the power MOS are fully realized.

The invention provides a novel crimping type IGBT module. The novel crimping type IGBT module comprises a tube shell, and platy metal electrodes coaxially arranged at the upper and lower ends of the tube shell, wherein lug bosses are fixed on the inner side face of the metal electrode at the lower end; power sub modules are crimped between the lug bosses and the metal electrode at the upper end; the lug bosses are arranged by taking the center of the metal electrode at the lower end as the center of a circle; and the lug bosses are distributed on the inner side face of the metal electrode at the lower end circumferentially from the inner layer to the outer layer at an equidistributed manner in sequence. According to the technical scheme of the novel crimping type IGBT module provided by the invention, the problem of overhigh overshoot of partial current when transient state current passes through the lug bosses of the crimping type IGBT module is solved; and the reliability of the crimping type IGBT module is improved, and the safety operation area of the crimping type IGBT module is enlarged.