42 results about "Saturation voltage" patented technology

A light emitting diode (LED) driving system comprises at least one linear current driver configured to regulate current to a plurality of LEDs in a multi-spectral application independently of an electrical load affected by voltage fluctuations across the LEDs; and a programmable input configured to receive a current setpoint signal from a digital-to-analog converter (DAC), which defines a target current through the LEDs. The LED driving system further comprises a programmable voltage regulator configured to output a supply voltage to the least one linear current driver that includes a saturation voltage sufficient for the at least one linear current driver to regulate the current delivered to the plurality of LEDs.

The invention discloses an NPC converter closed-loop feedback data driven IGBT saturation voltage drop monitoring method, and relates to the field of electronic power device state monitoring, and the method comprises the steps: collecting the operation data of an NPC energy storage converter; performing analog-to-digital conversion on the acquired operation data; performing data cleaning on the operation data; deriving a mathematical model of the energy storage converter, and substituting the processed data into the mathematical model; performing curve fitting, calculating an objective function, searching an optimal solution to minimize the objective function, and obtaining an identification voltage drop parameter of the IGBT; according to an IGBT output characteristic curve, extracting parameters in a healthy state, and comparing the parameters with identification parameters to carry out state evaluation; a parameter self-correction or online correction mechanism is introduced; classifying the health states of the IGBTs through normal distribution; and online evolution evaluation and abnormity early warning of the device state are realized. By the adoption of the method, the actual IGBT state and behavior are simulated through the digital model, and therefore predictive maintenance is achieved.

The invention discloses a silicon carbide intelligent power module with voltage and current dual-detection over-current protection, and relates to the technical field of semiconductors. In order to solve the problem that when an existing silicon-based intelligent power module (IPM) is matched with a silicon carbide metal-oxide-semiconductor field effect transistor, due to the fact that the over-current protection response speed is low, interference and false triggering are likely to happen, a dual over-current protection mechanism combining desaturation voltage detection and sub-current detection is adopted. And by mixing and integrating the silicon substrate and the silicon carbide power device, the performance requirements of different application scenes are considered. Three driving control chips, six IGBT chips, six fast recovery diode chips, one SiC MOSFET chip, two silicon carbide Schottky barrier diode chips and one patch sampling resistor are integrated in the module, and all the elements are packaged in the same insulation heat dissipation substrate and lead frame combined structure, so that high integration level, high reliability and fast overcurrent protection are realized; the method can be widely applied to the fields of household appliances, industrial control, new energy and the like.

The application belongs to the technical field of short-circuit protection circuit, and discloses a short-circuit protection circuit and system using a back-saturation logic control, which comprises an upper and lower bridge back-saturation voltage sampling unit, an upper and lower bridge back-saturation voltage comparison unit, an upper and lower bridge back-saturation high and low voltage signal isolation integration unit, an upper and lower bridge back-saturation low voltage signal driving integration unit and a main power unit. The application increases an AND gate circuit at the output end of the back-saturation judgment circuit of each upper and lower bridge of the silicon carbide MOSFET, so that only when the upper and lower bridges both trigger back-saturation, the short-circuit protection is triggered. When only the upper or lower bridge single MOSFET tube triggers back-saturation, the short-circuit protection time still follows the existing protection parameters, that is, false positives caused by the fast opening of the silicon carbide and the interference of system noise are avoided.

The application provides an insulated gate bipolar transistor and a manufacturing method thereof, and relates to the fields of semiconductor power devices and manufacturing. In order to effectively reduce the on-voltage drop, the hole concentration in the N-type charge storage layer will significantly increase, which will cause the field intensity in the N-type charge storage layer to exponentially increase when the insulated gate bipolar transistor is in reverse blocking, and the collector-emitter reverse blocking voltage to decrease. In the embodiment, a part of the conductive channel is replaced by a first P+ region, the introduction of the first P+ region can make the field intensity in the N-type charge storage layer decrease and share the rising field intensity with the N-drift region. However, the introduction of the first P+ region will reduce the conductance modulation effect of the N-type charge storage layer, so the N+ intercepting region, the trench intercepting region and the hole extraction region arranged along the extension direction of the trench in the first P+ region are repeatedly arranged, the extraction rate of the key carrier holes is artificially adjusted, and the balance problem of the saturation voltage drop, the reverse cut-off voltage, the short circuit characteristic and the switching speed can be solved.

The invention discloses a submicron micro-groove IGBT (Insulated Gate Bipolar Translator), which belongs to the technical field of power semiconductor devices and comprises a substrate, a plurality of grooves and a contact assembly, comprising a Gate groove and a virtual groove, the Gate groove and the virtual groove are isolated from a substrate through an oxide layer, the Gate groove adopts a multi-groove parallel connection and non-full-channel structure, the non-full-channel is a single-side channel only arranged beside two outer side Gate grooves in the parallel connection structure, and the two single-side channels are arranged in a bilateral symmetry mode; each contact assembly is composed of a contact hole and heavy doping, the contact assemblies are arranged on the two outer sides of the Gate groove parallel structure, the contact assemblies on the two outer sides are arranged in a bilateral symmetry mode, and the device has the advantages that the parasitic resistance is reduced through multi-Gate parallel connection, the current density is reduced while the current loss is reduced through non-full-channel optimization; the outer side contact assembly reduces contact electrical impedance latch, the virtual groove ensures low saturation voltage drop, the micro-scale structure is compatible, and the technical effects of low loss, high reliability and wide adaptability are achieved.

The invention discloses a desaturation short-circuit protection circuit and method of a power switching device and a new energy vehicle, and relates to the technical field of motor controllers, the desaturation short-circuit protection circuit of the power switching device comprises a driving module, a divider resistor and a diode, the driving module comprises a switching tube and a comparator, and a time delay module is arranged in the switching tube; the driving module is used for controlling the switching tube to be switched off under the condition that the actual conduction duration of the switching tube reaches the target conduction duration; the divider resistor is used for dividing voltage to obtain desaturation voltage of the driving module after the switching tube is switched off; and the driving module is also used for controlling the comparator to turn over under the condition that the desaturation voltage is greater than a preset comparator turn-over voltage threshold value so as to start desaturation short-circuit protection on the power switch device. The circuit provided by the invention can quickly respond to short-circuit protection of the power switch device on the basis of ensuring low power consumption and high robustness.

The invention discloses an IGBT (Insulated Gate Bipolar Translator) driving control method based on secondary side hardware protection and active clamping, which comprises the following specific steps of: establishing an IGBT digital twin model, and updating junction temperature distribution, saturation voltage drop and theoretical boundaries of a dynamic safe working area under different working conditions in real time through model simulation; in the normal switching process of the IGBT, voltage waveforms and current change rate waveforms in the switching-on and switching-off stages of the IGBT are collected in real time, key parameters are identified, and meanwhile self-adaptive correction is carried out; according to the invention, the conversion from passive protection to active prediction can be realized, the accuracy of protection criteria is greatly improved, the voltage stress and loss of a device are remarkably reduced, false triggering and misjudgment are reduced, the self-diagnosis capability and response speed of a system are improved, the time precision and coordination of protection decisions are ensured, and the reliability of the system is improved. Thermal fatigue and breakdown risks caused by overstress are reduced, so that the service life of the device is prolonged, and the overall reliability and operation efficiency of the power module are improved.

Various methods and circuital arrangements for reducing a turn ON time of a cascode amplifier are presented. According to one aspect, a configurable switching arrangement coupled to a cascode transistor of the amplifier shorts a gate of the cascode transistor to a reference ground during an inactive mode of operation of the amplifier. During an active mode of operation of the amplifier, the configurable switching arrangement couples a gate capacitor to the gate of the cascode transistor that is pre-charged to a voltage that is higher than a gate biasing voltage to the cascode transistor, which ensures that cascode transistor turns ON much quicker than the traditional method of grounding the cap, hence provide a final current flow through the cascode amplifier in a shorter time by not limiting the turn ON time of the input transistor. The gate biasing voltage is coupled to the gate capacitor via a resistor. A relationship between the pre-charged voltage, and minimum saturation voltages and threshold voltages of the transistors of the cascode amplifier is also provided.

The present disclosure provides a low noise, low switching loss, and emitter-collector saturation voltage V CE An object of the present invention is to provide a semiconductor device capable of suppressing an increase in (sat). [Solution] A semiconductor device according to the present disclosure comprises a two-stage active dummy trench having a first upper electrode and a first lower electrode, and a two-stage active trench having a second upper electrode and a second lower electrode, the first upper electrode, the second upper electrode, and the second lower electrode being connected to the same gate pad, the two-stage active dummy trench and the two-stage active trench extending horizontally in a plan view, and within the overall horizontal length of the two-stage active dummy trench and the two-stage active trench, the length of the region where the two-stage active dummy trench and the two-stage active trench are adjacent is longer than the length of the region where the two-stage active dummy trench and the two-stage active trench are not adjacent.

The invention discloses a high-conductivity insulated gate bipolar transistor with multiple deep trench insulating columns and a manufacturing process thereof, and relates to the technical field of power semiconductor manufacturing, the high-conductivity insulated gate bipolar transistor comprises an emitter end and a collector end, the emitter end comprises an emitter region, a base region and an insulating layer, and trench gates are arranged on two sides of the base region; the emitter end further comprises a potential floatable P-type region and a plurality of deep trench insulating columns therein; the P-type region is formed by doping P-ions on the side wall and the bottom of the insulating column groove, and the deep groove insulating column is filled with an insulating material; the emitter region comprises two N + emitter regions and a P + region between the N + emitter regions. The processing difficulty of the potential floatable P-type region is reduced by increasing the number of the insulating columns, performing side wall ion implantation and backfilling an insulating material process, and the process reliability is improved; according to the structure, low saturation voltage between the collector electrode and the emitter electrode is realized by changing the flow direction of holes, excessive carriers at the emitter electrode are reduced, the switching time is shortened, the switching loss is reduced, the electric field intensity at the bottom of the grid electrode can be reduced, and the breakdown voltage is improved.

The present disclosure aims to provide a semiconductor device capable of improving gate breakdown voltage and lowering saturation voltage. [Solution] The semiconductor device according to the present disclosure comprises a semiconductor substrate, a base layer of a first conductivity type provided on the surface side of the semiconductor substrate, and a trench provided on the surface side of the semiconductor substrate that penetrates the base layer and has an upper electrode covered with an upper oxide film, a lower electrode covered with a lower oxide film, and a boundary oxide film located between the upper electrode and the lower electrode. The upper electrode has a concave shape on the surface facing the lower electrode and has a pointed portion that constitutes the concave shape, the pointed portion has a shape that extends in the width direction of the trench, the pointed portion and the lower electrode face each other in the width direction of the trench, the thickness of the upper oxide film is constant along the base layer and the layer below the base layer, and the thickness of the boundary oxide film is thicker than the thickness of the upper oxide film.

The present application discloses a transistor and a display panel. The transistor comprises a gate, an active layer, a first electrode, and a second electrode. By forming a Schottky contact between the first electrode of the transistor and a first sub-area within a first overlapping area, a Schottky barrier can be introduced at the contact surface of the first sub-area, and carriers must overcome the Schottky barrier when entering the first sub-area from the first electrode, so that the flow of the carriers within the first sub-area can be controlled, thereby reducing the saturation voltage, and thus reducing the power consumption of a driving circuit or a display panel to which the transistor is applied. In addition, by forming an ohmic contact between the first electrode of the transistor and a second sub-area within the first overlapping area, a low resistance at the contact surface of the second sub-area can be ensured, so that it can be ensured that the carriers can more easily enter the second sub-area from the first electrode, thereby increasing the on-state current of the transistor.

An object of the present disclosure is to provide a semiconductor device which is low in noise and low in switching loss, and which is capable of suppressing an increase in saturation voltage VCE (sat) between an emitter and a collector. This semiconductor device is provided with: a double-layer active dummy trench having a first upper layer electrode and a first lower layer electrode; and a double-layer active trench having a second upper-layer electrode and a second lower-layer electrode, the first upper-layer electrode, the second upper-layer electrode, and the second lower-layer electrode being connected to the same gate pad, the double-layer active dummy trench and the double-layer active trench extending in the horizontal direction in plan view. The length of a region in which the double-layer active dummy trench and the double-layer active trench are adjacent is longer than the length of a region in which the double-layer active dummy trench and the double-layer active trench are not adjacent in the full length of the double-layer active dummy trench and the full length of the double-layer active trench in the horizontal direction.

The present application relates to the technical field of radiation measurement with ionization chamber, and particularly relates to a radiation test method and system for a medical cyclotron. The present application firstly analyzes the change characteristics of the output current curve under the condition of the change of the polarization voltage, evaluates the saturation voltage probability coefficient of the output current curve segment corresponding to the ideal polarization voltage, then combines the ionization interference factors such as the ionization chamber environment and the change of the beam intensity of the particle beam, evaluates the radiation confidence of each output current accurately reflecting the radiation intensity, then screens and corrects the to-be-corrected current, obtains the ideal output current correction curve, and further improves the radiation test accuracy of the medical cyclotron.

This application discloses a method, apparatus, device, and medium for parameter identification of a synchronous motor. The method includes: obtaining the steady-state value of the synchronous motor under a given voltage and the measured value of the bus voltage by varying the carrier frequency; obtaining the stator resistance of the synchronous motor and the saturation voltage error of the inverter using a target converter circuit model of the inverter and the synchronous motor and multiple sets of measured values; injecting a low-frequency sinusoidal current into the synchronous motor, and determining the current corresponding to the minimum ratio of the third harmonic amplitude to the fundamental amplitude of the synchronous motor at the given voltage as the bias current identification result of the inverter; when the direct and quadrature axes of the synchronous motor have saturation characteristics, obtaining the maximum peak point of its response current spike under the second harmonic and the zero-crossing point of the fundamental wave, injecting positive and negative voltage pulses into these two points respectively, and determining the type of synchronous motor and the direct and quadrature axis inductance based on the peak value of the response current. This method can improve the accuracy of synchronous motor parameter identification.

This application provides an open-drain output circuit and chip. The open-drain output circuit includes a driving transistor, a first isolation transistor, a second isolation transistor, a control circuit, and an output port. Both the first and second isolation transistors include a body diode. The first isolation transistor conducts when the voltage at the output port is positive and greater than the forward voltage of the body diode in the first isolation transistor, allowing the pull-down current at the output port to flow to system ground through the first isolation transistor and the driving transistor. The second isolation transistor is controlled to conduct when the voltage at the output port is positive and lower than a preset threshold, allowing the pull-down current at the output port to flow to system ground through the second isolation transistor and the driving transistor. The forward voltage of the body diode in the first isolation transistor is less than the preset threshold. The minimum saturation voltage of the open-drain output circuit provided in this application meets the requirements of automotive-grade chips.

A kind of reducing saturation voltage triode.It is related to the field of semiconductor technology.The utility model discloses a thin base region and thick base region structure design, form the emitting area in thick base region, form base electrode on thin base region, relative traditional structure reduces the thickness of base region on the two sides of emitting area, reduces the recombination of carrier in the base region on the two sides of emitting area, increases unit current density, simultaneously, the innovative structure increases the area of base region and collector region junction below base electrode, the height difference of thin base region and thick base region makes the side of thick base region contact with collector region, increases the area of base region and collector region junction, in turn increases the number of carrier in collector region collected in base region, increases unit area current density, improves power density.

The invention provides a junction temperature prediction model establishment method, a test life prediction method and electronic equipment, and relates to the technical field of power electronics, and the junction temperature prediction model establishment method comprises the steps: obtaining a test data sequence obtained by carrying out an aging test on a power device; preprocessing the test data sequence to obtain inherent frequency time sequence data and saturation voltage drop time sequence data; determining heat conduction pad compression stress time sequence data according to the inherent frequency time sequence data, and determining heat conduction pad thermal resistance time sequence data according to the heat conduction pad compression stress time sequence data and a preset mapping relation; determining junction temperature fluctuation time sequence data according to the heat conduction pad thermal resistance time sequence data; and taking the inherent frequency time series data and the saturation voltage drop time series data as input data, taking the junction temperature fluctuation time series data as labels, constructing a data set, and training a deep learning model by adopting the data set to obtain a junction temperature prediction model. The junction temperature prediction precision is effectively improved, simulation or test resources can be saved, and the test period is shortened.

The invention provides a semiconductor device, a chip and electronic equipment, relates to the technical field of semiconductors, and realizes low saturation voltage and high output impedance by forming a depletion region at an overlapping region of a first channel and a conductive structure. The semiconductor device comprises a substrate and a vertical transistor arranged on the substrate. The vertical transistor comprises a first electrode, a first channel, a second electrode and a first gate structure. The first electrode, the first channel and the second electrode are sequentially stacked in the direction from the substrate to the vertical transistor. The vertical transistor further comprises a conductive structure, the conductive structure is in contact with the surface, facing the first electrode, of the second electrode, and the conductive structure is arranged on the side wall of the first channel. The work function of the conductive structure is greater than the affinity of the first channel. The first gate structure comprises a first gate electrode and a first gate medium used for isolating the first gate electrode from the first channel, and the conductive structure is electrically isolated from the first gate electrode.

A bipolar junction transistor (BJT) comprising a semiconductor region and a plurality of metal contacts, located on a top surface of the semiconductor region, where the plurality of metal contacts comprise one or more first metal contacts that are in contact with one or more emitter regions and one or more second metal contacts that are in contact with an upper surface of a body region of the semiconductor region. One or more insulating structures are located on the top surface of the semiconductor region, where the insulating structures isolate the one or more first metal contacts from the one or more second metal contacts. A metal layer is located over the insulating structures, where the metal layer is in contact with one or more first metal contacts and is isolated from the one or more second metal contacts by the insulating structures.

The application discloses a multiple deep-groove insulating column high-conductivity insulated gate bipolar transistor and a manufacturing method thereof, and relates to the technical field of power semiconductor manufacturing. The application discloses a multiple deep-groove insulating column high-conductivity insulated gate bipolar transistor and a manufacturing method thereof, and relates to the technical field of power semiconductor manufacturing. The emitter end comprises an emitting area, a base area and an insulating layer, and the base area is provided with groove type gates on both sides. The emitter end further comprises a potential floatable P type area and a plurality of deep-groove insulating columns in the P type area. The P type area is formed by doping P ions on the sidewalls and the bottom of the insulating column grooves, and the deep-groove insulating columns are filled with insulating materials. The emitting area comprises two N+ emitter areas and a P+ area between the N+ emitter areas. By increasing the number of insulating columns, performing sidewall ion implantation and backfilling insulating material process, the processing difficulty of the potential floatable P type area is reduced, and the process reliability is improved. The above structure changes the hole flow direction to realize low saturation voltage between the collector and the emitter end, reduces excessive carriers of the emitter end, shortens the switching time, reduces the switching loss, reduces the electric field intensity at the bottom of the gate, and improves the breakdown voltage.

The application discloses an IGBT module aging characteristic decoupling parameter monitoring method based on temperature characteristics, and specifically comprises the following steps: establishing an IGBT-radiator system thermal network model, iteratively calculating the steady-state temperature difference of each loss period starting node and the steady-state temperature difference of the half loss period node, and constructing an aging characteristic parameter; combining the IGBT module thermal resistance, the saturation voltage drop failure standard, deducing an aging factor calculation formula, and establishing a mapping relationship between the aging characteristic parameter and the aging degree; fixing the working condition, measuring the junction temperature curve of the healthy module under the periodic loss, and calculating the aging characteristic parameter value of the healthy state; measuring the junction temperature curve of any module with different aging degrees under the periodic loss, and calculating the aging characteristic parameter value of the module; and finally calculating the heat dissipation path and the bonding wire aging level of the measured module. The aging characteristic decoupling parameter extraction is more simple and convenient, has small invasion and low cost, decouples the failure mode, and is more comprehensive in representation.

The invention relates to a planar gate IGBT (Insulated Gate Bipolar Translator) device with high short-circuit capability and a manufacturing method thereof, which are characterized in that on the basis of the preparation of a conventional planar IGBT, the forming step of a P-type well region is adjusted, that is, after phosphorus injection and junction pushing of an active region are completed, photoetching and boron ion injection of P-type well region injection are carried out, and then the growth of a gate oxide layer is carried out; depositing and etching a polycrystalline silicon grid electrode; and injecting an N + emitter electrode and the like. According to the invention, the P-type well region is formed in front of the polycrystalline silicon gate, so that the length and morphology of the channel can be flexibly controlled, the saturation voltage drop of the device is not influenced, the saturation current of the device can be obviously reduced, and the short-circuit tolerance time of the device is greatly prolonged.

The invention discloses a thermal parameter identification method, system and equipment for a power semiconductor device and a heat dissipation system thereof, and a storage medium. The method comprises the following steps: heating a to-be-tested device to a thermal equilibrium state; the device shell temperature and the radiator temperature of the device to be measured are measured, when other n devices are installed on the same radiator, the device shell temperature and the radiator temperature of other n devices are measured at the same time, the device shell temperature refers to the substrate temperature below the center of the device chip, and the radiator temperature refers to the radiator surface temperature below the center of the device chip; measuring the device saturation voltage drop and the heating current of the to-be-measured device, and multiplying the device saturation voltage drop by the heating current to obtain the device loss; and calculating the thermal resistance from the device shell to the radiator by using a formula according to the device shell temperature, the radiator temperature and the device loss. According to the invention, the thermal parameter identification of the device and the heat dissipation system can be realized without changing the heat dissipation working condition and measuring the junction temperature cooling curve.

The invention provides a high-temperature double-pulse testing method for a power semiconductor device, which relates to the technical field of dynamic testing of the power semiconductor device and comprises the following steps of: performing static sampling processing on the power semiconductor device to be tested under the conditions of room temperature, medium temperature and high temperature to form a junction temperature-saturation voltage drop reference curve; and in the static sampling processing, a saturation voltage drop value is obtained through static parameter testing equipment. And heating and driving the to-be-tested power semiconductor device to form a temperature rise signal sequence. According to the high-temperature double-pulse test method for the power semiconductor device, the junction temperature of the power semiconductor device is accurately controlled, and dynamic test is carried out in a high-temperature environment, so that accurate switch characteristic parameter test in a high-temperature state is realized. The high-temperature double-pulse test method for the power semiconductor device overcomes the problems that a traditional test method is inaccurate in temperature control and low in test precision in a high-temperature environment, and truly and accurately reflects the performance of the device in an actual working condition.

The invention relates to a desaturation voltage signal fault diagnosis method, electronic equipment and a medium. The desaturation voltage signal fault diagnosis method comprises the following steps: acquiring desaturation voltage waveform data of a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving board under different working conditions; processing the data through variational mode decomposition (VMD), and separating out a plurality of mode components; calculating a sample entropy of each modal component, and calculating an entropy difference coefficient and a reduction coefficient between the original voltage and the modal component according to the sample entropy; constructing a modal decomposition evaluation coefficient Cal by using the entropy difference coefficient and the reduction coefficient, and determining an optimal modal component number through the coefficient; a weight vector is analyzed and determined through an entropy weight method, the fitness of modal components is analyzed through a TOPSIS method, and the modal component with the highest fitness is selected as a feature modal component; and taking the frequency as a characteristic frequency, comparing the characteristic frequency with voltage data, identifying abnormal oscillation, and completing voltage state identification. According to the method, the problems of external interference and misjudgment of a traditional method are effectively solved, and the accuracy and efficiency of fault diagnosis are improved.

The application discloses an IGBT drive control method based on secondary side hardware protection and active clamping, and the control scheme has the following specific steps: an IGBT digital twin model is established, and the junction temperature distribution, saturation voltage drop and theoretical boundary of the dynamic safe working area under different working conditions are updated in real time through model simulation; during the normal switching process of the IGBT, the voltage waveform and the current change rate waveform at the turn-on and turn-off stages of the IGBT are collected in real time, key parameters are identified, and adaptive correction is simultaneously performed; the application can realize the transformation from passive protection to active prediction, greatly improve the accuracy of the protection criterion, significantly reduce the voltage stress and loss of the device, reduce the false triggering and misjudgment, improve the self-diagnosis capability and response speed of the system, ensure the time accuracy and coordination of the protection decision, reduce the thermal fatigue and breakdown risk caused by over-stress, thereby prolonging the service life of the device and improving the overall reliability and operation efficiency of the power module.

The utility model relates to the technical field of chargers, in particular to a charging mode control circuit and a charger. In the charging mode control circuit, a voltage detection chip is electrically connected with a power management chip; the voltage detection chip is used for enabling the power management chip to enter a constant-current charging mode when detecting that the charging voltage is lower than the saturation voltage; the voltage detection chip is used for switching the power management chip to a constant-voltage charging mode when the charging voltage is detected to be higher than saturation voltage; the current detection module is electrically connected with the power management chip through the first switch element; the current detection module is used for triggering the first switch element to be switched on when it is detected that the charging current is smaller than a current threshold value, so that the power management chip is switched to a trickle charging mode. The charging mode control circuit and the charger provided by the utility model have the advantages of high charging efficiency and safety, quicker charging and capability of reaching the saturation capacity of the battery.

This invention belongs to the field of power device technology, specifically relating to a power device gate resistor structure, a power device, and a method for fabricating a power module. This invention achieves flexible configuration of the gate resistor by setting several independent resistor units on at least one side of the gate PAD, and connecting both ends of each resistor unit to the resistor PAD while isolating it from the gate PAD. During power module fabrication, the final equivalent gate resistance value required for each chip can be accurately calculated based on individual test data of each chip (such as saturation voltage drop, threshold voltage, switching speed, Rg, etc.) and the parasitic inductance differences of the current paths of parallel chips in the module layout. Then, the corresponding resistor units are connected between the gate PAD and the gate busbar in series or parallel using a bonding process. This design breaks the limitations of traditional fixed gate resistors inside chips, enabling personalized gate resistance adjustment based on the characteristics of each chip and its specific location in the module.