11results about How to "Improve conduction characteristics" patented technology

The invention provides a wide bandgap semiconductor trench gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof. In the structure, an N + current expansion layer is positioned in an upper region of an N-epitaxial layer; the P-well region is located on the N + current expansion layer, and the source N + region is located on the P-well region; the plurality of trench gate electrodes are arranged at intervals along the horizontal direction, and a first source P + region is arranged between every two adjacent trench gate electrodes in the middle region; the trench gate electrode penetrates through the source N + region, the P-well region and the N + current expansion layer in the longitudinal direction and extends into the N-epitaxial layer; a second source P + region is arranged at the bottom of the trench gate electrode; the P-type connection region is connected with the plurality of second source P + regions in the second direction; an interlayer dielectric layer is arranged above the trench gate electrode; the N + contact region is arranged at the first source P + region in an extending mode in the first direction, and the Schottky contact region is located above the N + contact region. The structure can improve the current density of the device, improves the conduction characteristic of the device, can also form a net-shaped P-type region protection gate electrode, and improves the dynamic reliability of the gate electrode of the device.

The invention provides a GaN HEMT (High Electron Mobility Transistor) with strong non-clamping inductive switching capability in an irradiation scene and a preparation method thereof, and belongs to the technical field of semiconductors. Comprising a substrate layer, a gallium nitride layer, a passivation layer, a channel layer, a barrier layer and an electrode structure layer, the electrode structure layer comprises a grid electrode structure, a source electrode structure and a drain electrode structure, the source electrode structure and the drain electrode structure are arranged on the two sides of the grid electrode structure, the grid electrode structure is in a strip shape and arranged above the barrier layer in the first direction, and the source electrode structure and the drain electrode structure are connected with the channel layer; a plurality of rectangular P-type gallium nitride layers arranged in groups are arranged between the grid electrode structure and the drain electrode structure, the plurality of rectangular P-type gallium nitride layers arranged in groups are uniformly arranged at intervals along a first direction and are connected through a metal wire, the top of the metal wire is connected with a negative potential electrode, and an area between the potential barrier layer and the negative potential electrode is filled with a dielectric layer. The technical problems that the normal switching capability of a device is affected and the overvoltage robustness is degraded due to hole accumulation after irradiation of a traditional HEMT can be solved.

The present invention discloses a low dynamic resistance enhanced GaN device. In the conventional enhanced HEMT enhanced device preparation process, an additional P-type doped GaN thin layer (i.e., p-GaN thin layer) is introduced by selectively etching the p-GaN epitaxial layer. The surface trap shielding effect and hole injection effect formed by the p-GaN thin layer in the device structure effectively suppress the ionization of traps in the device, and have a strong inhibitory effect on the current collapse effect. Therefore, the resistance degradation of the GaN device is improved, the dynamic stability of the device is improved, and the conduction characteristics of the device are optimized.

The application discloses a kind of copolymer organic semiconductor devices based on isolation and interconnection and preparation method, including substrate, photoetching blocking layer, insulating isolation layer, N organic field effect transistor and N-1 interconnection line;Photoetching blocking layer includes isolation layer and inorganic dielectric layer;Isolation layer is opened with N longitudinal through isolation groove along length direction;Inorganic dielectric layer includes lower dielectric layer and upper dielectric layer;Lower dielectric layer is located in N isolation, and upper dielectric layer is laid on the top of isolation layer and lower dielectric layer;Each organic field effect transistor includes semiconductor layer, source, drain and gate;Semiconductor layer is laid in the isolation groove at the bottom of corresponding lower dielectric layer section, and its material is organic copolymer.The application effectively utilizes isolation groove and photoetching blocking layer, and the semiconductor layer of different semiconductor materials is wrapped and isolated, so as to realize the integration of different organic field effect transistors on the same substrate, and the organic field effect transistor can realize effective interconnection.

The utility model relates to the technical field of semiconductors, in particular to an insulated gate bipolar transistor, which comprises a transistor module, bare copper is arranged at the center of the transistor module, and a chip A and a chip B are respectively arranged below the bare copper and on the transistor module. A collector lead and a grid lead are sequentially arranged at the bottom of the transistor module, the chip A is connected with the collector lead through a first aluminum wire, and the chip A is connected with the grid lead through a second aluminum wire. The insulated gate bipolar transistor adopts a double-chip structure, and the IGBT with the double-chip structure has smaller switching loss under the condition of the same current and voltage, so that higher power bearing capacity is realized under the condition of the same size, the power density is improved, higher power output is favorably realized in a limited space, and the reliability of the IGBT is improved. Meanwhile, by means of the double-chip structure, when one part of chips are damaged, the other part of chips can still be used, and therefore the overall reliability is improved.

The invention discloses a low-resistance P-type silicon carbide crystal, a silicon carbide substrate and a liquid phase growth method of a semiconductor single crystal, and belongs to the technical field of semiconductor preparation. The liquid phase growth method for a semiconductor single crystal comprises: a step for forming a protective layer on the surface of a seed crystal; a waiting step of placing the protective layer toward the liquid surface in a state away from the liquid surface of the raw material solution heated to the growth temperature; a step for dissolving the protective layer in the raw material solution by bringing the protective layer into contact with the raw material solution; the protective layer is composed of a material having a melting point higher than the growth temperature and a material soluble in the raw material solution at a temperature lower than the growth temperature. According to the growth method, the seed crystal can be protected from being etched by steam liquid drops in the heating stage, meanwhile, components in a raw material solution cannot be changed, the crystal quality of a semiconductor is improved, and formation of defects in the semiconductor is inhibited.

The present invention discloses an adhesive film for circuit connection. The adhesive film for circuit connection comprises: a first adhesive layer containing conductive particles, a cured product of a photocurable resin component and a first thermosetting resin component; and a second adhesive layer disposed on the first adhesive layer and containing a second thermosetting resin component. The minimum melt viscosity of the adhesive film for circuit connection is 450 to 1600 Pa·s.

The invention discloses an activation and surface protection method for ion implantation SiC, and relates to the technical field of semiconductor manufacturing. Comprising the following steps: performing high-temperature ion implantation on a SiC wafer; pVD carbon film plating is carried out on the SiC wafer after high-temperature ion implantation; performing laser activation annealing on the SiC wafer plated with the carbon film; performing plasma physical etching on the annealed SiC wafer; carrying out sacrificial oxide layer treatment on the SiC wafer subjected to plasma physical etching; and carrying out BOE solution wet etching on the SiC wafer after sacrificial oxide layer treatment to obtain the SiC device. According to the method, through high-temperature ion implantation and laser annealing treatment and by adopting a multi-step carbon film removal process, the ion implantation impurity activation efficiency is remarkably improved, meanwhile, the morphology of the device is guaranteed, and the performance of the device is improved. The method has the advantages of simple process, high activation efficiency, good repeatability and the like, and is suitable for manufacturing SiC-based power semiconductor devices.

The utility model relates to the technical field of semiconductors, in particular to a high-voltage metal oxide semiconductor (MOS) diode, which comprises a packaging body, an MOS chip is arranged inside the packaging body, three pins are connected below the packaging body, the three pins are respectively connected with the MOS chip through a first aluminum wire and two second aluminum wires, and the first aluminum wire and the second aluminum wire are respectively connected with the MOS chip. And a source electrode, a grid electrode and a drain electrode are sequentially formed. A plurality of thimbles are arranged on an MOS chip, and a multi-thimble structure is used for carrying out die bonding on the MOS diode, so that the effective width of the MOS chip is increased, the resistance of the MOS diode in a conducting state can be reduced, the conducting characteristic of a device is improved, meanwhile, the multi-thimble structure is adopted, the charge density on the MOS chip can be reduced, the charge voltage drop can be reduced, and the reliability of the device is improved. And the switching speed and the loss characteristic of the device are improved, so that the stress on the MOS chip is dispersed, and the risk of crystal cracking is further reduced.

The present application provides a semiconductor device and a method for preparing the same, comprising a first N-type epitaxial layer located on one side of a substrate; a P-well region and a source N-type contact region located on the side of the first N-type epitaxial layer away from the substrate; a source P-type contact region located on the side of the first N-type epitaxial layer away from the substrate; a gate trench penetrating the P-well region and the source N-type contact region; an N-type channel located on the sidewall of the gate trench and in the P-well region; an N-type current extension region located between the gate trench and the first N-type epitaxial layer; the N-type current extension region and the N-type channel are connected; a gate dielectric layer and a gate located in the gate trench; an interlayer dielectric layer located on the side of the gate away from the substrate; a source located on the side of the interlayer dielectric layer away from the substrate; and a drain located on the side of the substrate away from the source. The longitudinal arrangement of the N-type current extension region is relatively matched with the current path, which can reduce the on-resistance, improve the on-characteristics of the device, and improve the electrical performance of the device.

The utility model relates to a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a double-gate groove, belonging to the technical field of semiconductors. The device comprises an active region and a terminal region. A first gate trench and a second gate trench are arranged in the active region, a P-type base region is arranged below the first gate trench, the side wall and the bottom of the first gate trench are covered with a gate oxide layer, and the first gate trench is filled with a polycrystalline silicon electrode and an interlayer medium; and a P-type protection region is arranged below the second gate trench, and the side wall and the bottom of the P-type protection region are covered with the gate oxide layer and filled with the polycrystalline silicon electrode. An N + type source region and a P + type source region penetrating through the N + type source region are arranged between the first gate trench and the second gate trench, and a source ohmic contact electrode is formed on the surface of the source region. Through the optimization of the double-gate trench structure and the doping design, the high reliability of the gate oxide layer, the uniformity of electric field distribution and the excellent conduction performance are realized, and the semiconductor device is suitable for high-power density occasions.