5results about How to "Improve conduction characteristics" patented technology

The present invention discloses a low dynamic resistance enhanced GaN device. In the conventional enhanced HEMT enhanced device preparation process, an additional P-type doped GaN thin layer (i.e., p-GaN thin layer) is introduced by selectively etching the p-GaN epitaxial layer. The surface trap shielding effect and hole injection effect formed by the p-GaN thin layer in the device structure effectively suppress the ionization of traps in the device, and have a strong inhibitory effect on the current collapse effect. Therefore, the resistance degradation of the GaN device is improved, the dynamic stability of the device is improved, and the conduction characteristics of the device are optimized.

The application discloses a kind of copolymer organic semiconductor devices based on isolation and interconnection and preparation method, including substrate, photoetching blocking layer, insulating isolation layer, N organic field effect transistor and N-1 interconnection line;Photoetching blocking layer includes isolation layer and inorganic dielectric layer;Isolation layer is opened with N longitudinal through isolation groove along length direction;Inorganic dielectric layer includes lower dielectric layer and upper dielectric layer;Lower dielectric layer is located in N isolation, and upper dielectric layer is laid on the top of isolation layer and lower dielectric layer;Each organic field effect transistor includes semiconductor layer, source, drain and gate;Semiconductor layer is laid in the isolation groove at the bottom of corresponding lower dielectric layer section, and its material is organic copolymer.The application effectively utilizes isolation groove and photoetching blocking layer, and the semiconductor layer of different semiconductor materials is wrapped and isolated, so as to realize the integration of different organic field effect transistors on the same substrate, and the organic field effect transistor can realize effective interconnection.

The present invention discloses an adhesive film for circuit connection. The adhesive film for circuit connection comprises: a first adhesive layer containing conductive particles, a cured product of a photocurable resin component and a first thermosetting resin component; and a second adhesive layer disposed on the first adhesive layer and containing a second thermosetting resin component. The minimum melt viscosity of the adhesive film for circuit connection is 450 to 1600 Pa·s.

The invention discloses an activation and surface protection method for ion implantation SiC, and relates to the technical field of semiconductor manufacturing. Comprising the following steps: performing high-temperature ion implantation on a SiC wafer; pVD carbon film plating is carried out on the SiC wafer after high-temperature ion implantation; performing laser activation annealing on the SiC wafer plated with the carbon film; performing plasma physical etching on the annealed SiC wafer; carrying out sacrificial oxide layer treatment on the SiC wafer subjected to plasma physical etching; and carrying out BOE solution wet etching on the SiC wafer after sacrificial oxide layer treatment to obtain the SiC device. According to the method, through high-temperature ion implantation and laser annealing treatment and by adopting a multi-step carbon film removal process, the ion implantation impurity activation efficiency is remarkably improved, meanwhile, the morphology of the device is guaranteed, and the performance of the device is improved. The method has the advantages of simple process, high activation efficiency, good repeatability and the like, and is suitable for manufacturing SiC-based power semiconductor devices.

The utility model relates to a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a double-gate groove, belonging to the technical field of semiconductors. The device comprises an active region and a terminal region. A first gate trench and a second gate trench are arranged in the active region, a P-type base region is arranged below the first gate trench, the side wall and the bottom of the first gate trench are covered with a gate oxide layer, and the first gate trench is filled with a polycrystalline silicon electrode and an interlayer medium; and a P-type protection region is arranged below the second gate trench, and the side wall and the bottom of the P-type protection region are covered with the gate oxide layer and filled with the polycrystalline silicon electrode. An N + type source region and a P + type source region penetrating through the N + type source region are arranged between the first gate trench and the second gate trench, and a source ohmic contact electrode is formed on the surface of the source region. Through the optimization of the double-gate trench structure and the doping design, the high reliability of the gate oxide layer, the uniformity of electric field distribution and the excellent conduction performance are realized, and the semiconductor device is suitable for high-power density occasions.