Strain vertical MOS device manufacturing method

Abstract

Disclosed is a strain vertical MOS device manufacturing method. The method comprises the steps of conducting pattern transfer on a substrate, forming a metal mask, forming a silicon column through etching, reducing the diameter of the silicon column, preparing silicon nanowires and growing a gate oxide layer; conducting polycrystalline silicon deposition, doping and foreign ion activation to form an annular grid electrode; depositing a stress silicon nitride film outside the grid electrode to form a stress liner layer; conducting ion injection to form a drain terminal n- doping area; conducting ion injection on the peripheral annular area of the substrate to form a drain terminal n+ doping area; conducting P+ ion injection on the upper portions of the silicon nanowires to form a Halo doping structure, and conducting n type ion injection to form a source terminal; depositing metal and alloy. According to the method, the grid-control capacity of devices in a nanometer node integrated circuit is improved, the short-channel effect and hot carrier effect are restrained, carrier mobility is improved, current driving capacity is improved, the size of the devices is reduced on the premise that the performance of the devices is not reduced, and then requirements for miniaturization of the devices are met.

Description

technical field [0001] The invention belongs to the field of manufacturing nanometer electronic devices, and relates to a method for forming a strained channel semiconductor device using a stress liner technology, in particular to a method for manufacturing a strained vertical MOS device. Background technique [0002] As the size of semiconductor devices continues to shrink, the method of improving device performance by scaling down the device size is approaching the limit, and the short-channel effect and subthreshold performance degradation also limit the further reduction of the device size. Therefore, many researches are dedicated to new structures and new processes to meet the requirements of chips for device characteristics under the condition of nanometer size. Among all the MOSFET device structures currently proposed, the gate of the surrounding gate MOSFET completely surrounds the channel, which has the strongest short channel effect suppression ability and current ...

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Problems solved by technology

[0005] The purpose of the present invention is to provide a manufacturing method of a strained vertical MOS device, which solves the problem of device performance degradation due to size reduction, effectively improves carrier mobility, thereby improving device performance

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