15 results about "Impurity doping" patented technology

A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.

The application provides a pressure-resistant IGBT device and a channel pushing method and a gate preparation method thereof. When the IGBT device is prepared by using the channel pushing method, after dry etching an N-type doped polycrystal layer, a furnace tube process is used to perform P-well pushing to form a channel. In the process, the distance between the wafers is increased to at least 2 times the distance in the original process by adjusting the distance between each wafer in the furnace tube, and oxygen is provided in the nitrogen protective atmosphere of the furnace process, so that an oxide layer is formed on the front surface of the wafer. By combining the two ways of increasing the distance between the wafers and increasing the oxide layer, the influence of the N-type impurity doping of the adjacent wafers on the P-well pushing is reduced, thereby avoiding the pressure failure of the device, improving the yield of the wafer, better converging the yield stability, and improving the reliability of the device product.

A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.

A repeller may be mounted inside an arc chamber of an ion implantation apparatus for doping impurities into a surface film of a semiconductor wafer. The repeller may include a body including an outer circumferential surface and a surface area enlargement portion on the body. The surface area enlargement portion may include striped grooves continuously formed on the outer circumferential surface of the body at intervals in a longitudinal direction of the body.

Method for forming a semiconductor device (200), comprising: Providing a substrate (208) comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers arranged over the substrate (208), wherein the first and second semiconductor layers (222, 220) have different material compositions and are arranged alternately with each other; Structuring the first semiconductor layers (222) and the second semiconductor layers (220) to form a first fin (212c) and a second fin (212b, 212d); Removing the first semiconductor layers (222) from the first fin (212c) and the second fin (212b), such that a first section of the structured second semiconductor layers (220) becomes first floating nanostructures (220) in the first fin (212c), and a second section of the structured second semiconductor layers (220) becomes second floating nanostructures (220) in the second fin (212b); Doping a threshold-modifying impurity into the first suspended nanostructures (220) in the first fin (212c), wherein the doping of the threshold-modifying impurity includes the application of a plasma-assisted low-temperature doping process; Forming a first gate stack (260c) over the first fin (212c), wherein a section of the first gate stack (260c) envelops the first floating nanostructures (220), thereby forming a first transistor with a first threshold voltage; and Forming a second gate stack (260b) over the second fin (212b), wherein a section of the second gate stack (260b, 260d) envelops the second floating nanostructures (220), thereby forming a second transistor with a second threshold voltage which is higher than the first threshold voltage.

The application discloses a preparation method of a boron aluminum nitride / nitrogen terminal diamond two-dimensional electron gas heterojunction structure which improves lattice mismatch, and comprises the following steps: obtaining a 111 plane monocrystalline silicon substrate; epitaxially growing a monocrystalline boron nitride transition layer on the 111 plane monocrystalline silicon substrate; growing a diamond epitaxial layer on the surface of the monocrystalline boron nitride transition layer; performing nitrogen terminal treatment on the surface of the diamond epitaxial layer to form a nitrogen terminal surface; epitaxially growing monocrystalline boron aluminum nitride with an Al plane polar wurtzite structure and a donor impurity on the nitrogen terminal surface to form a boron aluminum nitride epitaxial layer, so as to form a boron aluminum nitride / nitrogen terminal diamond two-dimensional electron gas heterojunction. The preparation method breaks through the size limitation of a high-quality diamond substrate, effectively alleviates the lattice distortion of boron aluminum nitride on diamond in the epitaxial process, reduces the surface state and the dangling bond at the formed heterojunction interface, and improves the quality of the diamond heterojunction.

A microelectromechanical system (MEMS) resonator includes a substrate having a substantially planar surface and a resonant member having sidewalls disposed in a nominally perpendicular orientation with respect to the planar surface. Impurity dopant is introduced via the sidewalls of the resonant member such that a non-uniform dopant concentration profile is established along axis extending between the sidewalls parallel to the substrate surface and exhibits a relative minimum concentration in a middle region of the axis.

To efficiently manufacture a semiconductor device of high breakdown voltage.SOLUTION: A method for manufacturing a semiconductor device according to one aspect includes a step of preparing a semiconductor substrate of a first conductivity type, a step of doping the semiconductor substrate with impurities of a second conductivity type to form a plurality of impurity regions that are two-dimensionally distributed in a plane perpendicular to a thickness direction of the semiconductor substrate in the semiconductor substrate, and a step of thermally diffusing impurities in the plurality of impurity regions to form a buried layer of the second conductivity type in the semiconductor substrate.SELECTED DRAWING: Figure 2

This application proposes a method for fabricating a MOS device. The method includes: performing impurity doping on the source / drain regions of an initial chip substrate to obtain a first chip substrate; depositing a Ni sacrificial layer on the surface of the first chip substrate to obtain a second chip substrate, wherein a portion of the Ni sacrificial layer deposited into vias diffuses into the impurity-doped source / drain regions, forming a nickel silicide layer on top of the impurity-doped source / drain regions; etching the Ni sacrificial layer of the second chip substrate to obtain a third chip substrate; depositing a contact metal layer on the surface of the third chip substrate to obtain a fourth chip substrate; and heat-treating the fourth chip substrate to react the contact metal layer with the surface layer of the source / drain regions to form a nickel-containing metal silicide, thereby forming a MOS device. The technical solution of this application can improve the performance of MOS devices.

A method of manufacturing an electrode of a semiconductor device includes: preparing a semiconductor substrate including an impurity-doped region; forming a first metal layer on the impurity-doped region; forming a second metal layer on the first metal layer; and heating the semiconductor substrate including the first metal layer and the second metal layer, wherein the impurity-doped region contains silicon, wherein the first metal layer contains tantalum, wherein the second metal layer contains titanium, and wherein, by the heating, a first silicide layer containing titanium, tantalum, and silicon is formed on the impurity-doped region, and a second silicide layer containing titanium and silicon is formed on the first silicide layer.

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which a threshold voltage of a parasitic transistor can be controlled at a desired level by forming a non-doped region without doped impurities or forming a first conductivity type impurity doped region on one side of a longitudinal end portion of a gate electrode.

A method and system for engineering C-Band telecom-wavelength quantum defects centers, such as carbon-boron vacancy (CB-VB) and silicon-boron vacancy (SiB-VB) complex centers, in hexagonal boron nitride (h-BN), the method including growing a h-BN thin epilayer, or a semi-bulk thick layer, using a semiconductor epitaxial growth processing tool, doping one or more of said h-BN thin epilayer, or said semi-bulk thick layer, with carbon or silicon impurities during the growing to create defect complexes comprising (CB-VB) and (SiB-VB), controlling a growth rate and V / III ratio during the growing, and producing h-BN wafers and thin epilayers with the (CB-VB) and (SiB-VB) quantum defect centers as single photon emitters in the conventional band of telecom wavelengths as well as qubits.

A method for fabricating an integrated circuit (IC) includes forming a silicon substrate and doping the silicon substrate with impurities. The method includes sequentially depositing and patterning multiple layers over the silicon substrate, wherein the layers comprise at least a dielectric layer, a metallization layer, an organic polarized layer (OPL), and a photoresist layer. The method includes etching one or more of the layers to create features including vias or trenches. The method includes cooling the IC to a temperature of around 20° C. or lower. The method includes stripping at least the organic planarization layer (OPL) and photoresist residue using ammonia (NH3) plasma to expose the metallization layer and depositing a metal in the vias or trenches.

A method for preparing a MOS device. The method comprises: performing impurity doping treatment on a source / drain region of an initial chip substrate to obtain a first chip substrate; depositing a Ni sacrificial layer on a surface of the first chip substrate to obtain a second chip substrate, wherein a part of the Ni sacrificial layer that is deposited into a through hole diffuses to the source / drain region that has been subjected to impurity doping treatment, and a nickel silicide layer is formed on the top of the source / drain region that has been subjected to impurity doping treatment; performing etching treatment on the Ni sacrificial layer of the second chip substrate to obtain a third chip substrate; depositing a contact metal layer on a surface of the third chip substrate to obtain a fourth chip substrate; and performing thermal treatment on the fourth chip substrate, so that the contact metal layer reacts with a surface layer of the source / drain region to obtain a nickel-containing metal silicide, and thus a MOS device is formed.

A method and system for engineering C-Band telecom-wavelength quantum defects centers, such as carbon-boron vacancy (CB-VB) and silicon-boron vacancy (SiB-VB) complex centers, in hexagonal boron nitride (h-BN), the method including growing a h-BN thin epilayer, or a semi-bulk thick layer, using a semiconductor epitaxial growth processing tool, doping one or more of said h-BN thin epilayer, or said semi-bulk thick layer, with carbon or silicon impurities during the growing to create defect complexes comprising (CB-VB) and (SiB-VB), controlling a growth rate and V / III ratio during the growing, and producing h-BN wafers and thin epilayers with the (CB-VB) and (SiB-VB) quantum defect centers as single photon emitters in the conventional band of telecom wavelengths as well as qubits.