40 results about "Impurity doping" patented technology

A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.

The invention relates to a compensation polarization doped aluminum nitride Schottky diode and a manufacturing method thereof. The compensation polarization doped aluminum nitride Schottky diode comprises a substrate, an unintentionally doped AlN layer, a Si doped AlN layer and a Si compensation doped Al component slowly-decreasing layer from bottom to top. The surface of the Si-doped AlN layer is in Schottky contact with the anode of the diode; the Si compensation doped Al component slowly-decreasing layer is from AlN to Al < x > Ga < 1-x > N from bottom to top, the value range of x is 0-0.3, and ohmic contact is formed between the Si compensation doped Al component slowly-decreasing layer and the cathode of the diode. According to the aluminum nitride Schottky diode, through compensation polarization doping, the metal contact performance is improved, the problems that the material surface is rough and the carrier mobility is low due to impurity doping are solved, and the Schottky diode with the high potential barrier and the low ideal factor is achieved.

The invention provides a crystal pulling method for reducing the head resistivity of a heavily arsenic-doped silicon single crystal, and belongs to the technical field of doped silicon single crystal production. Comprising the following steps: S1, sequentially carrying out a primary doping process, a primary temperature testing process, a primary seeding process, a re-melting process, a supplementary doping process, a secondary temperature testing process, a secondary seeding process, a shouldering process and an equal-diameter process; s2, if NG appears in the guiding and releasing process or the equal-diameter process, re-melting the crystal bar and carrying out supplementary doping, and then sequentially carrying out a temperature testing process, a crystal guiding process, a shouldering process and an equal-diameter process; s3, when the sum of the first doping multiple and the supplementary doping multiple reaches the total doping multiple, supplementary doping is stopped. By controlling the doping interval time and the total doping multiple, the head resistivity can be reduced and controlled within the upper limit of the specification, and impurities can be doped more uniformly, so that the crystallization rate is increased, the drawing and discharging times are reduced, and the quality of the drawn monocrystalline silicon is ensured.

The application provides a pressure-resistant IGBT device and a channel pushing method and a gate preparation method thereof. When the IGBT device is prepared by using the channel pushing method, after dry etching an N-type doped polycrystal layer, a furnace tube process is used to perform P-well pushing to form a channel. In the process, the distance between the wafers is increased to at least 2 times the distance in the original process by adjusting the distance between each wafer in the furnace tube, and oxygen is provided in the nitrogen protective atmosphere of the furnace process, so that an oxide layer is formed on the front surface of the wafer. By combining the two ways of increasing the distance between the wafers and increasing the oxide layer, the influence of the N-type impurity doping of the adjacent wafers on the P-well pushing is reduced, thereby avoiding the pressure failure of the device, improving the yield of the wafer, better converging the yield stability, and improving the reliability of the device product.

The invention relates to a construction method of a high-spin-selectivity photoelectric detector, and the method comprises the steps: setting a scattering region in the middle of a photoelectric detector model constructed by an armchair type Janus WSSe lattice, and enabling the regions at the two ends to serve as a left electrode and a right electrode respectively; the method comprises the following steps: introducing a vacancy defect of a single atomic level into a scattering region of a photoelectric detector, carrying out electronic local state analysis and impurity doping analysis on the scattering region after the defect is introduced, and screening out transition metal elements meeting preset conditions as doping elements; and performing bias voltage regulation and control on the photoelectric detector doped with the elements to construct a cooperative regulation and control strategy so as to complete construction of the photoelectric detector. According to the invention, through atomic scale defect introduction and transition metal doping modes, the photo-generated spinning current intensity, the spinning polarizability and the selective response ability to polarized light are significantly improved.

The invention discloses a production process for improving the conductivity of a conductive aluminum strip. The preparation process comprises the steps of preparation of an efficient refining agent, pretreatment and smelting of metal particles, ingot casting, cold rolling and the like. The synergistic purification effect of cryolite, borax and rare earth is utilized, doping of impurities such as oxygen, hydrogen, iron, silicon and vanadium in molten aluminum is reduced in the refining process, and the molten aluminum is primarily purified; in the refining process, the cold charge ratio is controlled, and an aluminum-boron-titanium refiner is added, so that uniform and large crystal grains grow in the ingot cooling and annealing process, the grain boundary area is reduced, the conductivity and mechanical property of the aluminum alloy are improved, impurities can be further removed through boron, molten aluminum can be further purified, the high conductivity of the aluminum alloy is achieved, and meanwhile the good mechanical property is achieved.

The present invention relates to a single photon avalanche diode (SPAD) structure and a method for manufacturing the same, and more particularly, to a method for forming a guide wall on the side of a first impurity-doped region and a second impurity-doped region so as to induce photo-generated charges to an avalanche region on the side of a PN junction region between the first impurity-doped region and the second impurity-doped region; a) diffusion is carried out, and thus the photon detection efficiency (Photon Detection Efficiency; a single photon avalanche diode (SPAD) structure of a single photon avalanche diode (PED) and a method of manufacturing

The application discloses a back contact cell and a manufacturing method thereof, and relates to the technical field of photovoltaics, which is used for preventing leakage between doped semiconductor layers with opposite conductive types in the back contact cell. The back contact cell comprises a semiconductor substrate, a first doped semiconductor layer, an intrinsic semiconductor layer, a second doped semiconductor layer and an insulating mask layer. The first doped semiconductor layer is divided into a first doped part and a second doped part. The second doped part is smaller than the first doped part in impurity doping concentration. The intrinsic semiconductor layer is formed on the part of the second doped part of the isolation area and is integrally formed with the first doped semiconductor layer. The second doped semiconductor layer covers the second area, at least part of the intrinsic semiconductor layer and at least part of the second doped part. The conductive types of the second doped semiconductor layer and the first doped semiconductor layer are opposite, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped crystalline silicon layer.

The invention relates to the technical field of semiconductor device preparation, and discloses a source-drain contact interface optimization method, a source-drain contact interface and a semiconductor device.The method comprises the steps that firstly, impurity doping is conducted on a source-drain area on a semiconductor substrate, a source-drain doping layer is formed, then an antimony monatomic layer is deposited on the source-drain doping layer, and the source-drain contact interface is formed. And depositing a contact metal layer on the semiconductor structure deposited with the antimony monatomic layer, and finally carrying out heat treatment on the semiconductor structure, so that the source-drain doping layer deposited with the antimony monatomic layer and the contact metal layer are subjected to a silicification reaction to generate silicide. According to the method, by depositing the antimony monatomic layer, the source-drain ratio contact resistivity is reduced, the current transmission efficiency is improved, the interface quality is kept in a high-temperature process, the service life of a semiconductor device is prolonged, and the working stability is improved.

The application provides an antimony impurity doped wafer and a preparation method thereof. A double-temperature-zone method is used to control a temperature field of a source region and a diffusion temperature of a wafer region respectively. The accurate control of the temperature of the source region can ensure the volatilization steam concentration of antimony oxide, and the accurate control of the temperature of the wafer region can ensure the longitudinal depth of impurity diffusion while ensuring the wafer surface quality. Compared with the prior art, the application can significantly improve the impurity doping concentration and diffusion depth of the wafer surface, and has obvious effects on reducing the series resistance of the collector of an NPN transistor. Meanwhile, the high-precision doping of the antimony impurity can be realized through one process step, 200 wafers can be processed per furnace, the production efficiency is greatly improved, and the production and processing cost is reduced.

A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.

A repeller may be mounted inside an arc chamber of an ion implantation apparatus for doping impurities into a surface film of a semiconductor wafer. The repeller may include a body including an outer circumferential surface and a surface area enlargement portion on the body. The surface area enlargement portion may include striped grooves continuously formed on the outer circumferential surface of the body at intervals in a longitudinal direction of the body.

Method for forming a semiconductor device (200), comprising: Providing a substrate (208) comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers arranged over the substrate (208), wherein the first and second semiconductor layers (222, 220) have different material compositions and are arranged alternately with each other; Structuring the first semiconductor layers (222) and the second semiconductor layers (220) to form a first fin (212c) and a second fin (212b, 212d); Removing the first semiconductor layers (222) from the first fin (212c) and the second fin (212b), such that a first section of the structured second semiconductor layers (220) becomes first floating nanostructures (220) in the first fin (212c), and a second section of the structured second semiconductor layers (220) becomes second floating nanostructures (220) in the second fin (212b); Doping a threshold-modifying impurity into the first suspended nanostructures (220) in the first fin (212c), wherein the doping of the threshold-modifying impurity includes the application of a plasma-assisted low-temperature doping process; Forming a first gate stack (260c) over the first fin (212c), wherein a section of the first gate stack (260c) envelops the first floating nanostructures (220), thereby forming a first transistor with a first threshold voltage; and Forming a second gate stack (260b) over the second fin (212b), wherein a section of the second gate stack (260b, 260d) envelops the second floating nanostructures (220), thereby forming a second transistor with a second threshold voltage which is higher than the first threshold voltage.

The application discloses a preparation method of a boron aluminum nitride / nitrogen terminal diamond two-dimensional electron gas heterojunction structure which improves lattice mismatch, and comprises the following steps: obtaining a 111 plane monocrystalline silicon substrate; epitaxially growing a monocrystalline boron nitride transition layer on the 111 plane monocrystalline silicon substrate; growing a diamond epitaxial layer on the surface of the monocrystalline boron nitride transition layer; performing nitrogen terminal treatment on the surface of the diamond epitaxial layer to form a nitrogen terminal surface; epitaxially growing monocrystalline boron aluminum nitride with an Al plane polar wurtzite structure and a donor impurity on the nitrogen terminal surface to form a boron aluminum nitride epitaxial layer, so as to form a boron aluminum nitride / nitrogen terminal diamond two-dimensional electron gas heterojunction. The preparation method breaks through the size limitation of a high-quality diamond substrate, effectively alleviates the lattice distortion of boron aluminum nitride on diamond in the epitaxial process, reduces the surface state and the dangling bond at the formed heterojunction interface, and improves the quality of the diamond heterojunction.

A semiconductor device includes a vertical stacked structure on a substrate that includes an interlayer insulating layer and a gate electrode. A barrier dielectric region is provided on sidewalls of an opening in the stacked structure. A lateral impurity region is provided that extends between the barrier dielectric region and the interlayer insulating layer and between the barrier dielectric region and the gate electrode. A lower impurity region is also provided that extends between the barrier dielectric region and the substrate.

To provide a semiconductor element having a stable electric characteristic.SOLUTION: A semiconductor element according to the present invention includes a channel layer, a barrier layer disposed on the channel layer and containing a substance with an energy band gap different from that of the channel layer, a gate electrode disposed on the barrier layer, a gate semiconductor layer disposed between the barrier layer and the gate electrode, and a source electrode and a drain electrode disposed on both sides of the gate electrode, penetrating at least a part of the barrier layer and the channel layer, and covering a side surface of the barrier layer and a side surface of the channel layer. The side surface of the barrier layer includes a first inclined surface that is inclined from an upper surface of the channel layer and doped with an impurity. The side surface of the channel layer includes a second inclined surface that is inclined from the upper surface of the channel layer. A first angle between a lower surface of the barrier layer and the first inclined surface of the barrier layer is smaller than or equal to a second angle between the upper surface of the channel layer and the second inclined surface of the channel layer.SELECTED DRAWING: Figure 2

Disclosed herein are photoconductive semiconductor switch (PCSS) materials and devices based on simple impurity doped ultra-wide bandgap semiconductors, including AIN and hexagonal BN. A PCSS device includes a substrate layer, a first and second electrode, and the ultra-wide bandgap (UWBG) active semiconductor material layer. The UWBG active material layer is doped with a deep level impurity, such as silicon (Si) in hexagonal BN or zirconium (Zr) in AIN.

A microelectromechanical system (MEMS) resonator includes a substrate having a substantially planar surface and a resonant member having sidewalls disposed in a nominally perpendicular orientation with respect to the planar surface. Impurity dopant is introduced via the sidewalls of the resonant member such that a non-uniform dopant concentration profile is established along axis extending between the sidewalls parallel to the substrate surface and exhibits a relative minimum concentration in a middle region of the axis.

The invention discloses a preparation method for synthesizing a Fe2C iron carbide catalyst with high purity and excellent thermal stability by utilizing a mechanical ball milling method. According to the method, long-time mechanical ball milling is carried out in an inert atmosphere, and single-phase Fe2C is successfully prepared. According to the method disclosed by the invention, the preparation of high-purity Fe2C can be realized under a large-scale production condition, and the problems of impurity doping, thermodynamic instability and the like existing in an iron carbide preparation method (such as gas-phase synthesis and liquid-phase thermal decomposition) in the prior art are solved. In addition, the Fe2C synthesized by the method is at high temperature (gt; the structure is kept stable at the temperature of 400 DEG C, phase change is avoided, and the material is obviously superior to Fe2C materials reported in existing literatures.

To efficiently manufacture a semiconductor device of high breakdown voltage.SOLUTION: A method for manufacturing a semiconductor device according to one aspect includes a step of preparing a semiconductor substrate of a first conductivity type, a step of doping the semiconductor substrate with impurities of a second conductivity type to form a plurality of impurity regions that are two-dimensionally distributed in a plane perpendicular to a thickness direction of the semiconductor substrate in the semiconductor substrate, and a step of thermally diffusing impurities in the plurality of impurity regions to form a buried layer of the second conductivity type in the semiconductor substrate.SELECTED DRAWING: Figure 2

The present invention proposes a high-voltage component and a method for manufacturing the same. The high-voltage component includes: a semiconductor layer, a well region, a base region, a gate, a source, and a drain. The base region has a second conductivity type, and the base region is formed in the semiconductor layer and connected to the well region in the channel direction. The gate is formed on the semiconductor layer, and part of the base region is located directly below the gate and connected to the gate to provide an inversion region for the high-voltage component during conduction operation. The source is located in the base region, the drain is located in a well region away from the base region, and part of the well region is located between the base region and the drain to separate the base region and the drain. The first concentration peak region of the impurity doping distribution of the base region is located directly below the source and contacts the source. The second conductivity type impurity concentration in the first concentration peak region is higher than that in other regions of the base region.

This application proposes a method for fabricating a MOS device. The method includes: performing impurity doping on the source / drain regions of an initial chip substrate to obtain a first chip substrate; depositing a Ni sacrificial layer on the surface of the first chip substrate to obtain a second chip substrate, wherein a portion of the Ni sacrificial layer deposited into vias diffuses into the impurity-doped source / drain regions, forming a nickel silicide layer on top of the impurity-doped source / drain regions; etching the Ni sacrificial layer of the second chip substrate to obtain a third chip substrate; depositing a contact metal layer on the surface of the third chip substrate to obtain a fourth chip substrate; and heat-treating the fourth chip substrate to react the contact metal layer with the surface layer of the source / drain regions to form a nickel-containing metal silicide, thereby forming a MOS device. The technical solution of this application can improve the performance of MOS devices.

A method of manufacturing an electrode of a semiconductor device includes: preparing a semiconductor substrate including an impurity-doped region; forming a first metal layer on the impurity-doped region; forming a second metal layer on the first metal layer; and heating the semiconductor substrate including the first metal layer and the second metal layer, wherein the impurity-doped region contains silicon, wherein the first metal layer contains tantalum, wherein the second metal layer contains titanium, and wherein, by the heating, a first silicide layer containing titanium, tantalum, and silicon is formed on the impurity-doped region, and a second silicide layer containing titanium and silicon is formed on the first silicide layer.

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which a threshold voltage of a parasitic transistor can be controlled at a desired level by forming a non-doped region without doped impurities or forming a first conductivity type impurity doped region on one side of a longitudinal end portion of a gate electrode.

A semiconductor structure includes a substrate, a deep well, a doped region, a field oxide, a gate structure, a source region, and a drain region. The deep well is with a first impurity of a first conductivity type in the substrate. The doped region is with a second impurity of a second conductivity type in the deep well, the second conductivity type being opposite to the first conductivity type. The field oxide partially is embedded in the deep well, wherein the field oxide interfaces with the doped region. The gate structure is over the field oxide and laterally extends across the doped region. The source region and the drain region laterally are separated at least in part by the doped region and the field oxide.

A method and system for engineering C-Band telecom-wavelength quantum defects centers, such as carbon-boron vacancy (CB-VB) and silicon-boron vacancy (SiB-VB) complex centers, in hexagonal boron nitride (h-BN), the method including growing a h-BN thin epilayer, or a semi-bulk thick layer, using a semiconductor epitaxial growth processing tool, doping one or more of said h-BN thin epilayer, or said semi-bulk thick layer, with carbon or silicon impurities during the growing to create defect complexes comprising (CB-VB) and (SiB-VB), controlling a growth rate and V / III ratio during the growing, and producing h-BN wafers and thin epilayers with the (CB-VB) and (SiB-VB) quantum defect centers as single photon emitters in the conventional band of telecom wavelengths as well as qubits.

A microelectromechanical system (MEMS) resonator includes a substrate having a substantially planar surface and a resonant member having sidewalls disposed in a nominally perpendicular orientation with respect to the planar surface. Impurity dopant is introduced via the sidewalls of the resonant member such that a non-uniform dopant concentration profile is established along axis extending between the sidewalls parallel to the substrate surface and exhibits a relative minimum concentration in a middle region of the axis.

The present invention discloses a metal oxide semiconductor field effect transistor (MOSFET), a method for preparing the same, and an electronic device. A trench is dug in both the N+ substrate and the N-type low-doped semiconductor layer to expose the N-type drift layer. A high-concentration N-type impurity-doped N+ drain region is formed on the side of the N-type drift layer near the N+ substrate, and the drain conductive layer fills the trench. This significantly reduces the resistance of the N+ substrate, and the N+ substrate can be maintained relatively thick without thinning the N+ substrate. Compared to existing methods of thinning the N+ substrate, the present invention reduces the risk of fragmentation and maintains the mechanical strength of the wafer. The drain conductive layer of the present invention directly contacts the N-type low-doped semiconductor layer, which facilitates the extraction of holes from the interface between the drain conductive layer and the N-type low-doped semiconductor layer when the body diode of the MOSFET is turned on, reducing the hole density within the N-type drift layer and thus reducing the reverse recovery charge and reverse recovery current of the device.

The application discloses a fast recovery diode structure and a preparation method thereof. An anode region (2) and a resistance region (3) are fixedly arranged on a front surface of an N-type drift region (1), the anode region (2) is located on a left side of the resistance region (3), and multiple resistance regions (3) are distributed at intervals. The anode region (2) and the resistance region (3) are formed by photoetching on the front surface of the N-type drift region (1), and P-type impurities are injected into the anode region (2) and the resistance region (3) for impurity doping. The fast recovery diode structure is prepared by adopting the method, the resistance region is designed as multiple injection strips which are spaced apart, and the injection strips are injected and advanced together with the anode region, so that low resistance is achieved, the process steps and time are reduced, and the problems of multiple process steps and long process time in the prior art are solved.

A semiconductor device includes an active area on a substrate, a gate insulating layer on the active area, and a gate electrode structure on the gate insulating layer. The gate electrode structure includes a first blocking impurity-doped layer in contact with an upper surface of the gate insulating layer and doped with a blocking impurity, a middle layer on the first blocking impurity-doped layer, and a second blocking impurity-doped layer on the middle layer and doped with the blocking impurity. A blocking impurity concentration in the second blocking impurity-doped layer is higher than a blocking impurity concentration in the first blocking impurity-doped layer.