63 results about "Impurity doping" patented technology

A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern sequentially stacked and vertically spaced apart, a source / drain pattern on the active pattern, and a gate electrode on the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern, where the source / drain pattern includes a buffer layer and a main layer on the buffer layer, the main layer includes silicon that is doped with an impurity, an impurity concentration of the main layer is a first atomic fraction at a first level corresponding to the first semiconductor pattern, and the impurity concentration of the main layer is a second atomic fraction at a second level corresponding to the second semiconductor pattern.

A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.

The invention relates to a compensation polarization doped aluminum nitride Schottky diode and a manufacturing method thereof. The compensation polarization doped aluminum nitride Schottky diode comprises a substrate, an unintentionally doped AlN layer, a Si doped AlN layer and a Si compensation doped Al component slowly-decreasing layer from bottom to top. The surface of the Si-doped AlN layer is in Schottky contact with the anode of the diode; the Si compensation doped Al component slowly-decreasing layer is from AlN to Al < x > Ga < 1-x > N from bottom to top, the value range of x is 0-0.3, and ohmic contact is formed between the Si compensation doped Al component slowly-decreasing layer and the cathode of the diode. According to the aluminum nitride Schottky diode, through compensation polarization doping, the metal contact performance is improved, the problems that the material surface is rough and the carrier mobility is low due to impurity doping are solved, and the Schottky diode with the high potential barrier and the low ideal factor is achieved.

The invention provides a crystal pulling method for reducing the head resistivity of a heavily arsenic-doped silicon single crystal, and belongs to the technical field of doped silicon single crystal production. Comprising the following steps: S1, sequentially carrying out a primary doping process, a primary temperature testing process, a primary seeding process, a re-melting process, a supplementary doping process, a secondary temperature testing process, a secondary seeding process, a shouldering process and an equal-diameter process; s2, if NG appears in the guiding and releasing process or the equal-diameter process, re-melting the crystal bar and carrying out supplementary doping, and then sequentially carrying out a temperature testing process, a crystal guiding process, a shouldering process and an equal-diameter process; s3, when the sum of the first doping multiple and the supplementary doping multiple reaches the total doping multiple, supplementary doping is stopped. By controlling the doping interval time and the total doping multiple, the head resistivity can be reduced and controlled within the upper limit of the specification, and impurities can be doped more uniformly, so that the crystallization rate is increased, the drawing and discharging times are reduced, and the quality of the drawn monocrystalline silicon is ensured.

The present invention discloses a silicon carbide power diode with a triple junction terminal extension structure and a preparation method thereof. The main structure of this device is a cylindrical structure, which is composed of an N+ type SiC substrate layer, an N-type SiC drift layer, and a P+ type SiC layer from bottom to top; the three JTE structures of this device extend from the inside to the outside in a concentric circle around the P+ type SiC layer, and are all doped with P-type impurities, but the doping size and uniformity are different; the upper and lower electrodes are respectively drawn from the P+ type SiC layer and the N+ type SiC substrate layer. The gradual impurity doping of the G-JTE2 layer is achieved by introducing graphene as an ion implantation technology for a mask layer and a vertical displacement control technology for the mask layer. The present invention creatively improves the SiC gradual impurity doping process and the device JTE structure, which can reduce the difficulty of designing impurity concentration in the JTE technology and increase the breakdown voltage of the device and the JTE layer doping dose window.

The application provides a pressure-resistant IGBT device and a channel pushing method and a gate preparation method thereof. When the IGBT device is prepared by using the channel pushing method, after dry etching an N-type doped polycrystal layer, a furnace tube process is used to perform P-well pushing to form a channel. In the process, the distance between the wafers is increased to at least 2 times the distance in the original process by adjusting the distance between each wafer in the furnace tube, and oxygen is provided in the nitrogen protective atmosphere of the furnace process, so that an oxide layer is formed on the front surface of the wafer. By combining the two ways of increasing the distance between the wafers and increasing the oxide layer, the influence of the N-type impurity doping of the adjacent wafers on the P-well pushing is reduced, thereby avoiding the pressure failure of the device, improving the yield of the wafer, better converging the yield stability, and improving the reliability of the device product.

The invention relates to a construction method of a high-spin-selectivity photoelectric detector, and the method comprises the steps: setting a scattering region in the middle of a photoelectric detector model constructed by an armchair type Janus WSSe lattice, and enabling the regions at the two ends to serve as a left electrode and a right electrode respectively; the method comprises the following steps: introducing a vacancy defect of a single atomic level into a scattering region of a photoelectric detector, carrying out electronic local state analysis and impurity doping analysis on the scattering region after the defect is introduced, and screening out transition metal elements meeting preset conditions as doping elements; and performing bias voltage regulation and control on the photoelectric detector doped with the elements to construct a cooperative regulation and control strategy so as to complete construction of the photoelectric detector. According to the invention, through atomic scale defect introduction and transition metal doping modes, the photo-generated spinning current intensity, the spinning polarizability and the selective response ability to polarized light are significantly improved.

The invention discloses a production process for improving the conductivity of a conductive aluminum strip. The preparation process comprises the steps of preparation of an efficient refining agent, pretreatment and smelting of metal particles, ingot casting, cold rolling and the like. The synergistic purification effect of cryolite, borax and rare earth is utilized, doping of impurities such as oxygen, hydrogen, iron, silicon and vanadium in molten aluminum is reduced in the refining process, and the molten aluminum is primarily purified; in the refining process, the cold charge ratio is controlled, and an aluminum-boron-titanium refiner is added, so that uniform and large crystal grains grow in the ingot cooling and annealing process, the grain boundary area is reduced, the conductivity and mechanical property of the aluminum alloy are improved, impurities can be further removed through boron, molten aluminum can be further purified, the high conductivity of the aluminum alloy is achieved, and meanwhile the good mechanical property is achieved.

The present invention discloses a method for improving chipping edge of dicing, comprising the following steps: Step 1: Wafer preparation: Select MCZ silicon single crystal wafer, 5-inch crystal orientation <111> , resistivity 5.0‑6.5Ω / cm, thickness 220μm±10%; Step 2: Slice road doping: Phosphorus liquid source deposition is performed under the conditions of furnace temperature 1120°C, oxygen 2L / min, nitrogen 3L / min, and source-carrying nitrogen 1.2L / min; Phosphorus source advancement is performed under the conditions of furnace temperature 1140°C, oxygen 2.5L / min, and nitrogen 4L / min; Four-probe test is used to test the diffusion block resistance of 0.6Ω±10%, and the junction depth is 12μm±10%. In the present invention, a high-concentration impurity doping process is performed on the scribe road area to make the scribe road "loose", thereby reducing the severity of scribe edge collapse and the resulting lattice damage, and improving the scribe quality of the wafer.

The present invention relates to a single photon avalanche diode (SPAD) structure and a method for manufacturing the same, and more particularly, to a method for forming a guide wall on the side of a first impurity-doped region and a second impurity-doped region so as to induce photo-generated charges to an avalanche region on the side of a PN junction region between the first impurity-doped region and the second impurity-doped region; a) diffusion is carried out, and thus the photon detection efficiency (Photon Detection Efficiency; a single photon avalanche diode (SPAD) structure of a single photon avalanche diode (PED) and a method of manufacturing

The application discloses a back contact cell and a manufacturing method thereof, and relates to the technical field of photovoltaics, which is used for preventing leakage between doped semiconductor layers with opposite conductive types in the back contact cell. The back contact cell comprises a semiconductor substrate, a first doped semiconductor layer, an intrinsic semiconductor layer, a second doped semiconductor layer and an insulating mask layer. The first doped semiconductor layer is divided into a first doped part and a second doped part. The second doped part is smaller than the first doped part in impurity doping concentration. The intrinsic semiconductor layer is formed on the part of the second doped part of the isolation area and is integrally formed with the first doped semiconductor layer. The second doped semiconductor layer covers the second area, at least part of the intrinsic semiconductor layer and at least part of the second doped part. The conductive types of the second doped semiconductor layer and the first doped semiconductor layer are opposite, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped crystalline silicon layer.

The invention relates to the technical field of semiconductor device preparation, and discloses a source-drain contact interface optimization method, a source-drain contact interface and a semiconductor device.The method comprises the steps that firstly, impurity doping is conducted on a source-drain area on a semiconductor substrate, a source-drain doping layer is formed, then an antimony monatomic layer is deposited on the source-drain doping layer, and the source-drain contact interface is formed. And depositing a contact metal layer on the semiconductor structure deposited with the antimony monatomic layer, and finally carrying out heat treatment on the semiconductor structure, so that the source-drain doping layer deposited with the antimony monatomic layer and the contact metal layer are subjected to a silicification reaction to generate silicide. According to the method, by depositing the antimony monatomic layer, the source-drain ratio contact resistivity is reduced, the current transmission efficiency is improved, the interface quality is kept in a high-temperature process, the service life of a semiconductor device is prolonged, and the working stability is improved.

The invention relates to a semiconductor device and a method for manufacturing the same. A semiconductor device includes: a semiconductor substrate formed to include a first active region and a second active region; a first dielectric layer disposed over the first active region; a second dielectric layer disposed over the second active region; a first gate electrode disposed over the first dielectric layer; and a second gate electrode disposed over the second dielectric layer. The first active region and the second active region have different impurity doping types from each other, and a fluorine concentration of the first dielectric layer is higher than a fluorine concentration of the second dielectric layer.

According to the metal oxide semiconductor field effect transistor, the preparation method thereof and the electronic equipment disclosed by the embodiment of the invention, the N + substrate and the N-type low-doped semiconductor layer are both provided with the grooves to expose the N-type drift layer, the N + drain region doped with high-concentration N-type impurities is formed on one side, close to the N + substrate, of the N-type drift layer, and the grooves are filled with the drain conducting layer, so that the N-type drift layer is exposed out of the N-type drift layer. The resistance of the N + substrate can be greatly reduced, the N + substrate does not need to be thinned, the thicker N + substrate can still be kept, and compared with a method for thinning the N + substrate in the prior art, the method has the advantages that the fragment risk is reduced, and the mechanical strength of the wafer can be kept. The drain conducting layer is in direct contact with the N-type low-doped semiconductor layer, so that holes can be extracted from the contact surface of the drain conducting layer and the N-type low-doped semiconductor layer when a body diode of the metal oxide semiconductor field effect transistor is conducted, and the hole density in the N-type drift layer is reduced; reverse recovery charge of the device is reduced, and reverse recovery current is reduced.

A semiconductor device includes a gate structure disposed on a substrate and extending along a first direction that is substantially parallel to an upper surface of the substrate, first and second impurity regions disposed on portions of the substrate at opposite sides of the gate structure along a second direction that is substantially parallel to the upper surface of the substrate, the first and second impurity regions being substantially perpendicular to each other, wherein the first and second impurity regions are each doped with n-type impurities, a third impurity region disposed on a portion of the substrate adjacent to the first impurity region along the second direction, wherein the third impurity region is doped with p-type impurities, a fourth impurity region disposed on a portion of the substrate adjacent to the first impurity region along the first direction, wherein the fourth impurity region is connected to the third impurity region and is doped with p-type impurities and a wiring structure disposed on the gate structure, wherein the wiring structure includes wirings that are disposed on a plurality of different levels. The fourth impurity region does not overlap a first one of the wirings along a vertical direction that is substantially perpendicular to the upper surface of the substrate. The first one of the wirings is disposed at an uppermost level among the plurality of different levels.

The application provides an antimony impurity doped wafer and a preparation method thereof. A double-temperature-zone method is used to control a temperature field of a source region and a diffusion temperature of a wafer region respectively. The accurate control of the temperature of the source region can ensure the volatilization steam concentration of antimony oxide, and the accurate control of the temperature of the wafer region can ensure the longitudinal depth of impurity diffusion while ensuring the wafer surface quality. Compared with the prior art, the application can significantly improve the impurity doping concentration and diffusion depth of the wafer surface, and has obvious effects on reducing the series resistance of the collector of an NPN transistor. Meanwhile, the high-precision doping of the antimony impurity can be realized through one process step, 200 wafers can be processed per furnace, the production efficiency is greatly improved, and the production and processing cost is reduced.

A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.

The present invention relates to the field of semiconductor technology, particularly to an epitaxial structure of a light emitting diode and a light emitting diode. The epitaxial structure of the light emitting diode includes a Mg modulation layer between a multiple quantum well light emitting layer and a first hole injection layer, the average impurity doping concentration in the Mg modulation layer is A, the average impurity doping concentration in the first hole injection layer is B, and the average impurity doping concentration in the electron blocking layer is C, where B>A>C, and this setting provides good electron blocking and hole injection effects, improving the light efficiency of the light emitting diode.

A repeller may be mounted inside an arc chamber of an ion implantation apparatus for doping impurities into a surface film of a semiconductor wafer. The repeller may include a body including an outer circumferential surface and a surface area enlargement portion on the body. The surface area enlargement portion may include striped grooves continuously formed on the outer circumferential surface of the body at intervals in a longitudinal direction of the body.

A semiconductor device includes a first substrate doped with an impurity of a first conductivity-type, a first well region formed in the first substrate and doped with an impurity of a second conductivity-type, different from the first conductivity-type, a first guard band that extends in a first direction, parallel to an upper surface of the substrate, is in the first well region, and doped with an impurity of the second conductivity-type, a second guard band facing the first guard band, in the substrate, and doped with an impurity of the first conductivity-type, a first electrode structure electrically connected to the first guard band, a second electrode structure electrically connected to the second guard band, and a first insulating layer on sidewalls of the first electrode structure and the second electrode structure, the first electrode structure, the insulating layer, and the second electrode structure provide a capacitor.

A semiconductor device includes a semiconductor substrate formed to include a first active region and a second active region, first and second dielectric layer disposed over the first and second active regions, first and second gate electrode disposed over the first and second dielectric layers, respectively; and wherein the first and second active region have different impurity doping types from each other, and fluorine concentration of the first dielectric layer is higher than fluorine concentration of the second dielectric layer.

To provide a capacitor, an electrical machinery and apparatus, and a method for manufacturing the capacitor that can contribute to ensuring resistance in harsh environments in a practical size.SOLUTION: A capacitor has a laminate in which an alumina film is laminated on an impurity-doped silicon substrate between a pair of electrodes, the impurity-doped silicon substrate is a p-type silicon substrate, and the rate of change in capacitance when heated to 100°C to 500°C relative to the capacitance at room temperature before heating is less than 20%, and the rate of change in capacitance when irradiated with an accumulated dose of 5 MGy X-rays and heated to 300°C relative to the capacitance before X-ray irradiation is less than 20%.SELECTED DRAWING: Figure 10

Method for forming a semiconductor device (200), comprising: Providing a substrate (208) comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers arranged over the substrate (208), wherein the first and second semiconductor layers (222, 220) have different material compositions and are arranged alternately with each other; Structuring the first semiconductor layers (222) and the second semiconductor layers (220) to form a first fin (212c) and a second fin (212b, 212d); Removing the first semiconductor layers (222) from the first fin (212c) and the second fin (212b), such that a first section of the structured second semiconductor layers (220) becomes first floating nanostructures (220) in the first fin (212c), and a second section of the structured second semiconductor layers (220) becomes second floating nanostructures (220) in the second fin (212b); Doping a threshold-modifying impurity into the first suspended nanostructures (220) in the first fin (212c), wherein the doping of the threshold-modifying impurity includes the application of a plasma-assisted low-temperature doping process; Forming a first gate stack (260c) over the first fin (212c), wherein a section of the first gate stack (260c) envelops the first floating nanostructures (220), thereby forming a first transistor with a first threshold voltage; and Forming a second gate stack (260b) over the second fin (212b), wherein a section of the second gate stack (260b, 260d) envelops the second floating nanostructures (220), thereby forming a second transistor with a second threshold voltage which is higher than the first threshold voltage.

Provided are: a capacitor that, in a practical size, can contribute to ensuring resistance in a severe environment; an electromechanical instrument; and a capacitor manufacturing method. In the capacitor, a laminate in which an alumina film is laminated on an impurity-doped silicon substrate is interposed between a pair of electrodes. The impurity-doped silicon substrate is a p-type silicon substrate. The rate of change in the capacitance in a state in which the temperature has risen to 100-500°C, with respect to the capacitance at room temperature before said temperature rise, is less than 20%. The change rate in the capacitance in a state in which the temperature has risen to 300°C by irradiation with X-rays at a cumulative dose of 5 MGy, with respect to the capacitance before said X-ray irradiation, is less than 20%.

A semiconductor device includes a gate structure disposed on a substrate and extending along a first direction that is substantially parallel to an upper surface of the substrate, first and second impurity regions disposed on portions of the substrate at opposite sides of the gate structure along a second direction that is substantially parallel to the upper surface of the substrate, the first and second impurity regions being substantially perpendicular to each other, wherein the first and second impurity regions are each doped with n-type impurities, a third impurity region disposed on a portion of the substrate adjacent to the first impurity region along the second direction, wherein the third impurity region is doped with p-type impurities, a fourth impurity region disposed on a portion of the substrate adjacent to the first impurity region along the first direction, wherein the fourth impurity region is connected to the third impurity region and is doped with p-type impurities and a wiring structure disposed on the gate structure, wherein the wiring structure includes wirings that are disposed on a plurality of different levels. The fourth impurity region does not overlap a first one of the wirings along a vertical direction that is substantially perpendicular to the upper surface of the substrate. The first one of the wirings is disposed at an uppermost level among the plurality of different levels.

The application discloses a preparation method of a boron aluminum nitride / nitrogen terminal diamond two-dimensional electron gas heterojunction structure which improves lattice mismatch, and comprises the following steps: obtaining a 111 plane monocrystalline silicon substrate; epitaxially growing a monocrystalline boron nitride transition layer on the 111 plane monocrystalline silicon substrate; growing a diamond epitaxial layer on the surface of the monocrystalline boron nitride transition layer; performing nitrogen terminal treatment on the surface of the diamond epitaxial layer to form a nitrogen terminal surface; epitaxially growing monocrystalline boron aluminum nitride with an Al plane polar wurtzite structure and a donor impurity on the nitrogen terminal surface to form a boron aluminum nitride epitaxial layer, so as to form a boron aluminum nitride / nitrogen terminal diamond two-dimensional electron gas heterojunction. The preparation method breaks through the size limitation of a high-quality diamond substrate, effectively alleviates the lattice distortion of boron aluminum nitride on diamond in the epitaxial process, reduces the surface state and the dangling bond at the formed heterojunction interface, and improves the quality of the diamond heterojunction.

A semiconductor device includes a vertical stacked structure on a substrate that includes an interlayer insulating layer and a gate electrode. A barrier dielectric region is provided on sidewalls of an opening in the stacked structure. A lateral impurity region is provided that extends between the barrier dielectric region and the interlayer insulating layer and between the barrier dielectric region and the gate electrode. A lower impurity region is also provided that extends between the barrier dielectric region and the substrate.

To provide a semiconductor element having a stable electric characteristic.SOLUTION: A semiconductor element according to the present invention includes a channel layer, a barrier layer disposed on the channel layer and containing a substance with an energy band gap different from that of the channel layer, a gate electrode disposed on the barrier layer, a gate semiconductor layer disposed between the barrier layer and the gate electrode, and a source electrode and a drain electrode disposed on both sides of the gate electrode, penetrating at least a part of the barrier layer and the channel layer, and covering a side surface of the barrier layer and a side surface of the channel layer. The side surface of the barrier layer includes a first inclined surface that is inclined from an upper surface of the channel layer and doped with an impurity. The side surface of the channel layer includes a second inclined surface that is inclined from the upper surface of the channel layer. A first angle between a lower surface of the barrier layer and the first inclined surface of the barrier layer is smaller than or equal to a second angle between the upper surface of the channel layer and the second inclined surface of the channel layer.SELECTED DRAWING: Figure 2

The invention provides an enhanced nitride semiconductor transistor epitaxial structure, which comprises a substrate, a nucleating layer, a buffer layer, a channel layer, a barrier layer and a cap layer arranged on the barrier layer, and the cap layer comprises a p-type polarization doped AlInGaN structure in which the Al component is gradually reduced along the epitaxial growth direction or the In component is gradually increased along the epitaxial growth direction. P-type doping is achieved through polarization doping instead of Mg atom impurity doping, higher negative ionization charge density and hole concentration are obtained, meanwhile, due to the fact that ionization charges and hole concentration generated by polarization doping are hardly affected by impurity ionization energy, an AlGaN or AlInGaN layer with the forbidden band width larger than that of GaN can be adopted as the cap layer, and therefore the performance of the device is improved. Therefore, the nitride transistor can obtain higher threshold voltage, and the reliability of the device in work is improved.

Disclosed herein are photoconductive semiconductor switch (PCSS) materials and devices based on simple impurity doped ultra-wide bandgap semiconductors, including AIN and hexagonal BN. A PCSS device includes a substrate layer, a first and second electrode, and the ultra-wide bandgap (UWBG) active semiconductor material layer. The UWBG active material layer is doped with a deep level impurity, such as silicon (Si) in hexagonal BN or zirconium (Zr) in AIN.