213 results about "Impurity doping" patented technology

A semiconductor substrate and a method of its manufacture has a semiconductor substrate having a carbon concentration in a range of 6.0×10¹⁵ to 2.0×10¹⁷ atoms/cm³, both inclusively. One principal surface of the substrate is irradiated with protons and then heat-treated to thereby form a broad buffer structure, namely a region in a first semiconductor layer where a net impurity doping concentration is locally maximized. Due to the broad buffer structure, lifetime values are substantially equalized in a region extending from an interface between the first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer to the region where the net impurity doping concentration is locally maximized. In addition, the local minimum of lifetime values of the first semiconductor layer becomes high. It is thus possible to provide a semiconductor device having soft recovery characteristics, in addition to high-speed and low-loss characteristics, while suppressing a kinked leakage current waveform.

Disclosed is a light emitting diode (LED) having an active region of a multiple quantum well structure in which well layers and barrier layers are alternately laminated between a GaN-based N-type compound semiconductor layer and a GaN-based P-type compound semiconductor layer. The LED includes a middle barrier layer having a bandgap relatively wider than the first barrier layer adjacent to the N-type compound semiconductor layer and the n-th barrier layer adjacent to the P-type compound semiconductor layer. The middle barrier layer is positioned between the first and n-th barrier layers. Accordingly, positions at which electrons and holes are combined in the multiple quantum well structure to emit light can be controlled, and luminous efficiency can be enhanced. Furthermore, an LED is provided with enhanced luminous efficiency using a bandgap engineering or impurity doping technique.

A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.

A method for doping impurities into a device layer is provided. The method includes providing a carbonized dopant layer over a device layer, wherein the carbonized dopant layer comprises one or more dopant impurities, and heat treating the carbonized dopant layer to thermally diffuse the dopant impurities into the device layer.

Disclosed here is a method of controlling a dose amount of dopant to be doped into object (1) to be processed in plasma doping. According to the method, the doping control is formed of the following processes: determining the temperature of object (1), the amount of ions having dopant in plasma that collide with object (1), and types of gases in plasma during doping; calculating a dose amount by neutral gas according to the temperature of object (1), and a dose amount by ions from the determined amount of ions containing dopant that collide with object (1); and carrying out doping so that the sum of the dose amount by neutral gas and the dose amount by ions equal to a predetermined dose amount.

The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

A method of forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on at least a portion of a semiconductor substrate of a first conductivity type and forming at least one trench through the epitaxial layer to at least partially expose the substrate. The method further includes doping at least one or more sidewalls of the at least one trench with an impurity of a known concentration level. The at least one trench is then substantially filled with a filler material. In this manner, a low-resistance electrical path is formed between an upper surface of the epitaxial layer and the substrate.

A solid state image pickup device is provided which can reduce crosstalks between range finding photoelectric conversion elements (AF sensor) and photometry photoelectric conversion elements (AE sensor). The solid state image pickup device has an n-type epitaxial semiconductor region, a p-type first well region formed in the semiconductor region, a p-type second well region formed in the semiconductor region and electrically separated from the first well, an n-type first impurity doped region formed in the first well region and an n-type second impurity doped region formed in the second well, wherein a photometry photoelectric conversion element is formed by using the p-type first well region and n-type first impurity doped region, and a range finding photoelectric element is formed by using the p-type second well region and n-type impurity doped region.

The invention relates to a diffusion method for a polycrystalline silicon solar photovoltaic cell silicon chip. The method comprises the following steps of: 1, putting the silicon chip into a furnace; 2, oxidizing; 3, diffusing a phosphorus source for the first time; 4, performing impurity distribution for the first time; 5, diffusing the phosphorus source for the second time; 6, performing impurity distribution for the second time; 7, gettering; and 8, taking the chip out of the furnace. The diffusion method for the polycrystalline silicon solar photovoltaic cell silicon chip has the advantages that: the phosphorus impurity doping concentration distribution is good, the diffusion rate has high controllability, the first pass yield of diffusion of the silicon chip is improved, the minority carrier lifetime of a polycrystalline silicon chip is prolonged, and the utilization rate of the phosphorus source in the diffusion process is high.

A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion maybe controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.

The invention discloses a preparation method of a germanium-base schottky transistor, which belongs to the technical field of a manufacturing process of ultra large scale integrated circuits (ULSI). The method comprises the following steps: manufacturing an MOS transistor structure on a germanium-base substrate; depositing a metal thin film; carrying out heat treatment for the first time for quick heat annealing so as to ensure that the metal thin film layer and the germanium layer below the metal thin film layer react to form metal germanide; removing the unreacted metal thin film layer; doping impurities in the germanide layer generated by the reaction; carrying out heat treatment for the second time for annealing so as to ensure that the doped impurities are activated to drive in; and finally forming contact holes and metal connection wires. The method carries out the impurity doping and the activated drive-in annealing after forming the germanide through the first annealing and can effectively regulate and control a barrier height of the contact of a metal semiconductor and also improve the surface appearance of the germanide.

A thin film transistor substrate is provided including a first thin film transistor and a second thin film transistor. The first thin film transistor comprises a first active layer, a first gate insulating film, and a first gate electrode. The second thin film transistor comprises a second active layer formed, a second gate insulating film, and a second gate electrode. A thickness of the second gate insulating film is larger than a thickness of the first gate insulating film, the second active layer has at least two impurity doping regions which overlap the second gate electrode, the first active layer has at least two impurity doping regions formed in a self-aligning manner with respect to the first gate electrode, and the second gate electrode comprises a semiconductor layer.

A method of manufacturing a semiconductor device having a silicon substrate containing an impurity diffusion layer is disclosed, that comprises the steps of doping impurities to the silicon substrate through a silicon oxide film with a thickness of 2.5 nm or less at an accelerating voltage of 3 keV or less, the silicon oxide film being formed on the silicon substrate and annealing the silicon substrate with the oxide film left.

An isolation structure and method of forming the same. The isolation structure includes a first isolation structure having including an insulation layer formed in a trench in a substrate and a second isolation structure, formed on the first isolation structure. The second isolation structure includes a first impurity region formed in the substrate, the first impurity region having a first impurity doping concentration, and a second impurity region that is formed around the first impurity region, the second impurity region having a second impurity doping concentration that is greater than the first doping concentration.

A semiconductor device includes a resistor element covered by a silicon oxide film. In the semiconductor device, with respective gate electrodes of MIS transistors and impurity doped layers, i.e., non-silicide regions exposed, thermal treatment for activating an impurity and silicidization are performed. Thus, auto-doping of an impurity is suppressed, so that variations in a resistance value of a resistor are suppressed. Also, the gate electrodes of the MIS transistors and the like are exposed when thermal treatment for activating an impurity, and therefore breakdown of respective gate insulation films of the MIS transistors hardly occurs.

A semiconductor device having a recess gate is formed by first forming a recess below the upper surface of the substrate. A spacer is formed at each sidewall of the recess. An impurity doping area is formed in a source area. A first LDD area is formed in a drain area. A gate comprising a gate insulating layer and a gate conductive layer is then formed in the recess. A second LDD area is formed on the upper surface of the semiconductor substrate. A gate spacer is formed at each sidewall of the gate. Then a source/drain area having an asymmetrical structure is formed on each side of the gate.

The invention discloses a method for preparing high-purity low-sulfur expanded graphite, which belongs to the preparation method of expanded graphite. The existing chemical method of the present invention to prepare expanded graphite has the technical problems of low product purity and high production cost. The method of the present invention: 1. high-temperature purification of phosphorus flake graphite; 2. putting it into a polypropylene mesh bag, soaking it in peroxide water, and lifting it to pour water; 3. wrapping the graphite block with a polypropylene mesh bag as an anode, and putting In the graphite electrolytic cell, then inject the electrolyte solution, use graphite as the cathode, and then electrolyze. During the electrolysis process, the polypropylene mesh bag is inflated and stirred; 4. Constant temperature drying and expansion; that is, high-purity low-sulfur expanded graphite is obtained. The method of the invention is simple and easy to operate, and the degree of intercalation can be controlled by adjusting the current intensity and electrolysis time, and the prepared high-purity expanded graphite is low in sulfur, and there is no pollution to the water body during the washing process, and no other impurities are doped in the product. The invention uses a small amount of oxidant to trigger, little or almost no pollution in production, and relatively low production cost.

The invention discloses a semiconductor substrate and a manufacturing method thereof. The semiconductor substrate comprises a support substrate as well as a polycrystalline silicon layer, a first oxide layer and a semiconductor layer which are sequentially located on the support substrate, wherein the support substrate is a heavy doped type silicon substrate; the specific resistance of the support substrate is in 10 <-3> omega.cm by means of the impurity doping concentration of the support substrate; and the polycrystalline silicon layer similarly can adopt conductive or insulated polycrystalline silicon. The semiconductor substrate structure adopts a design thought opposite to SOI (silicon on insulator), the silicon substrate of the support substrate is designed into a heavy doped conductive substrate, and a grounding effect is achieved through the conductive substrate, so that not only are the problems of leakage current and power loss solved, but also more electrode connection schemes and heat dissipation solving schemes of a semiconductor device further can be provided.