421results about "Diffusion/doping" patented technology

A method for preparing a silicon carbide heterojunction normally-off high-electron-mobility transistor includes selecting an unintentionally doped n-type 4H-SiC chip as a substrate; growing a 4H—SiC transition layer on the substrate through isomorphic epitaxial growth, and growing a C face on the 4H—SiC transition layer through epitaxial growth; growing an unintentionally doped 3C—SiC potential well layer on the C face of the 4H—SiC transition layer; growing an n-type doped 4H—SiC barrier layer on the 3C—SiC potential well layer, and growing a Si face on the 4H—SiC barrier layer through epitaxial growth; growing an unintentionally doped 3C—SiC cap layer on the Si face of the 4H—SiC barrier layer; and producing electrodes and protective films, so as to obtain a 3C—SiC / 4H—SiC heterojunction normally-off single-channel high-electron-mobility transistor. The method allows two sides of the SiC heterojunction interface have homogeneous elements during preparation, thereby eliminating diffusive contamination and reducing process complexity.

According to the preparation method of the heterogeneous wafer structure provided by the embodiment of the invention, the first bonding structure is provided; the first bonding structure comprises a first single crystal wafer, a first dielectric layer and a second single crystal wafer which are sequentially stacked, and a defect layer is arranged in the first single crystal wafer; providing a wafer structure; the wafer structure comprises a third single crystal wafer and a second dielectric layer located on the third single crystal wafer; etching the wafer structure from the surface of the second dielectric layer to form a symmetrical groove structure located on the surface of the third single crystal wafer; the depth of the symmetrical groove structure is equal to the thickness of the second dielectric layer; bonding the first bonding structure and the wafer structure to obtain a second bonding structure; the second bonding structure is subjected to annealing treatment, so that the second bonding structure is peeled off along the defect layer, the heterogeneous wafer structure is obtained, the annealing temperature of preparation of the heterogeneous wafer structure is effectively improved through the method, and the bonding strength and the reuse frequency of the heterogeneous wafer structure are increased.

A preparation method for a solar cell includes: providing a silicon wafer substrate having a first surface and a second surface, which is opposite to the first surface; forming a silicon-containing thin film comprising a doped layer on the first surface of the silicon wafer substrate, wherein the forming method for the doped layer comprises: forming a partially doped layer in an atmosphere in which the flow rate of a dopant gas source is 100-1000 sccm and the flow rate of silane is 1000-4000 sccm, and forming a remaining doped layer in an atmosphere in which the flow rate of the dopant gas source is 1500-3000 sccm and the flow rate of the silane remains unchanged; forming a patterned region; and performing a texturing treatment.

The invention discloses a low-resistance N-type gallium oxide crystal and a growth method thereof. The growth method comprises the following steps: pretreatment of raw materials: sintering a doped gallium oxide material block formed by mixing gallium oxide powder and doped raw material powder; crystal growth: heating the iraurita crucible to melt the doped gallium oxide material block, increasing the power of the medium-frequency induction coil to raise the temperature of the gallium oxide melt, keeping the temperature, cooling to the melting point of gallium oxide, keeping the melt state, firstly reducing the power of the medium-frequency induction coil to spontaneously nucleate at the cold core of the upper surface of the melt and realize the transverse growth of the nucleated crystal; reducing the power of the lower medium-frequency induction coil to enable the gallium oxide melt to grow from top to bottom until the gallium oxide melt completely grows into crystals; after crystal growth is finished, the temperature is reduced to 1200-1400 DEG C, heat preservation is conducted, cooling is conducted to the room temperature, and the low-resistance N-type gallium oxide crystals are obtained.The growth method is simple in process, the crystal growth speed is conveniently controlled, the crystal forming rate is increased, and large-scale mass production is achieved.

The invention provides a preparation method of a silicon carbide substrate, the silicon carbide substrate and a semiconductor device. The preparation method comprises the following steps: preprocessing a silicon carbide substrate raw material; performing neutron irradiation treatment on the material; and the material is subjected to annealing treatment. The silicon carbide substrate prepared by the preparation method provided by the invention can have relatively high mechanical property, conductivity, uniformity and stability.

The invention relates to a p-type silicon carbide epitaxial wafer, a preparation method thereof and a semiconductor device. The preparation method of the p-type silicon carbide epitaxial wafer comprises the following steps: placing a substrate in a reaction chamber; introducing source gas and diluent gas into the reaction chamber; applying radio frequency power to generate plasma in the reaction chamber; introducing a p-type doping source and carrier gas into the reaction chamber, wherein the p-type doping source comprises trimethylaluminum and triethyl boron; and growing a p-type silicon carbide epitaxial layer on one side of the substrate to obtain the p-type silicon carbide epitaxial wafer. According to the preparation method of the p-type silicon carbide epitaxial wafer, the trimethylaluminum and the triethyl boron are jointly used as the p-type doping source, the p-type silicon carbide epitaxial wafer is grown through the plasma enhanced chemical vapor deposition (PECVD) technology, and the doping efficiency can be improved.

The invention relates to the technical field of solar cells, and discloses a laser-assisted etching slotting method for preparing high-doping-concentration P + polycrystalline silicon and application. The grooving method comprises the following steps: preparing a tunneling SiOx layer and an i-polysi layer on the back surface of a silicon wafer; performing patterning etching by using green picosecond laser so as to remove the i-polysi layer and the tunneling SiOx layer in a laser region; removing impurities in a laser area through single-side acid pickling; boron diffusion is carried out, P + polycrystalline silicon is formed on the i-polysi layer in the non-laser area, a P + emission layer is generated in the laser area, and a BSG layer is generated on the back faces of the P + polycrystalline silicon and the P + emission layer; performing patterning etching by using green picosecond laser to remove the BSG layer in the laser area; and carrying out alkali wet etching to remove the P + emission layer in the laser area so as to form a notch. According to the grooving method, the notch with the ideal grooving depth is formed, P + polycrystalline silicon with high doping concentration can be formed in the non-laser area to reduce the contact resistivity, and the cost is low.

There is provided a gallium nitride single crystal substrate, which is a gallium nitride single crystal substrate having a diameter of 50 mm or more, with a low-index crystal plane closest to a main surface being (0001), and in which a Mn concentration in the substrate is 5×1017 cm−3 or more; and secondary ion mass spectrometry at a plurality of arbitrary points on the main surface reveals that a variation in the Mn concentration is within ±20% from an average value.

The utility model discloses a boron diffusion reaction intake system and reaction equipment, the boron diffusion reaction intake system comprises a boron source intake assembly and a reaction intake assembly, the boron source intake assembly comprises a first intake pipe, a first intake port is used for introducing a boron source, the first intake port is used for directly communicating with a reaction cavity, and the reaction intake assembly comprises a second intake pipe; the reaction gas inlet assembly comprises at least one second gas inlet pipe, a second gas inlet is used for introducing oxygen or nitrogen, and the second gas inlet pipe is isolated from the first gas inlet pipe; the reaction equipment comprises the boron diffusion reaction gas inlet system. According to the utility model, the first gas inlet pipe and the second gas inlet pipe are isolated from each other, and a boron source and other reaction gases are respectively fed through the first gas inlet pipe and the second gas inlet pipe, so that the boron source gas and oxygen are prevented from being mixed outside the reaction cavity, and the possibility that the boron source gas and the reaction gases react in advance before entering the reaction cavity is reduced; the influence of a gas inlet mode on a gas field in the reaction cavity is reduced, and the uniformity of sheet resistance of the silicon wafer is improved.

The present invention relates to the fields of ferroelectric single crystal technology and acousto-optical device technology, particularly to a silicon-based lead magnesium niobate (PbMn) single crystal piezoelectric wafer structure, preparation method, and application. The structure comprises a silicon substrate on which a silicon dioxide layer and a single crystal piezoelectric thin film layer are sequentially disposed; the single crystal piezoelectric thin film layer is a PbMn-PT single crystal, including a binary PMN-PT single crystal thin film or a ternary PIN-PMN-PT single crystal thin film. This piezoelectric wafer structure on a silicon substrate can be used to fabricate various high-performance piezoelectric MEMS sensors, actuators, and electro-optical modulator devices. The resulting surface acoustic wave (SAW) filters and thin film bulk acoustic wave (BAW) filters exhibit a relative bandwidth increase of over 50%, and the resulting electro-optical modulators exhibit lower half-wave voltage and higher electro-optical modulation efficiency. The device volume can be reduced by 10 times, better meeting the future 6G communication requirements for higher efficiency, higher integration, and miniaturization of MEMS devices. This provides a novel multilayer piezoelectric wafer structure for the miniaturization and integration of piezoelectric MEMS and optoelectronic devices.

The invention relates to a gas phase annealing method of a cadmium zinc telluride crystal. The gas phase annealing method comprises the following steps: S1, detecting the type and the defect concentration of point defects in the cadmium zinc telluride crystal; s2, determining a corresponding gas phase source for annealing regulation and control according to a point defect detection result; s3, preparing a gas phase source film on the quartz plate through physical vapor deposition; s4, confirming the gas phase source gas pressure of annealing; and S5, respectively packaging the tellurium-zinc-cadmium wafer and the quartz plate deposited with the gas-phase source film at two ends of an annealing quartz tube, then placing the annealing quartz tube in an annealing furnace, respectively heating the two ends of the annealing quartz tube, and finally obtaining the CdZnTe crystal modified by gas-phase annealing. Compared with the prior art, the method has the advantages that the variety and content of the gas phase source can be regulated and controlled, and finally the tellurium-zinc-cadmium crystal of which the internal defects are remarkably reduced and the electrical property of the crystal is remarkably improved is obtained.

The invention discloses a multi-element differentiated distribution co-doped single-crystal high-nickel positive electrode material and a preparation method and application thereof.The material is doped with a first doping element and a second doping element, the first doping element is in gradient distribution with the concentration gradually increased from inside to outside in material particles, and the second doping element is in gradient distribution with the concentration gradually increased from inside to outside. The second doping elements are basically and uniformly distributed in the material particles; the first doping element is used for strengthening the surface stability of the material, and the second doping element is used for stabilizing the bulk phase structure of the material. The material is obtained by taking a lithium salt and a ternary positive electrode material precursor as raw materials, introducing a first doping source and a second doping source, mixing, ball-milling and calcining according to a preset stoichiometric ratio.

The invention provides a wafer boat and semiconductor process equipment. The wafer boat comprises a plurality of supporting assemblies which are arranged in the circumferential direction of the wafer boat at intervals, each supporting assembly comprises a plurality of supporting columns which are arranged in the circumferential direction of the wafer boat at intervals, and each supporting column is arranged in the direction parallel to the axial direction of the wafer boat; the plurality of supporting pieces are arranged at intervals in the direction parallel to the axial direction of the wafer boat; each supporting piece comprises at least one supporting part, the orthographic projection of each supporting part on the radial cross section of the wafer boat is in a groove shape with an opening facing the outer side of the wafer boat, and the two ends of each supporting part are connected with the two adjacent supporting columns respectively; the supporting pieces of the multiple supporting assemblies are arranged at the same height in a one-to-one correspondence mode and used for jointly supporting the wafer, and the uniformity of film forming on the surface of the wafer is improved.

An ion source includes a vaporizer, an arc chamber, and a heat shield. The vaporizer includes a crucible containing an aluminum-containing material and a heater that heats the crucible. The crucible has a gas inlet and a vapor outlet. The arc chamber generates a plasma inside of the arc chamber. The vapor outlet outputs vapor into the arc chamber through a wall of the arc chamber, and the heat shield is provided between the vaporizer and the wall of the arc chamber.

A high-uniformity SiC crystal, a crystal bar, a substrate and a semiconductor device are provided. The SiC crystal is obtained by direct growth through a PVT method without subsequent machining, and includes a facet region and a non-facet region. The facet region is located on an outer-circumference end face of the SiC crystal. A doping concentration change rate of the facet region is 1.5 times or above that of the non-facet region; and / or a carrier concentration change rate of the facet region is 5 times or above that of the non-facet region.

The invention provides a preparation method of a diamond NV color center. The preparation method comprises the following steps: preparing one or more slotted nano structures on the surface of diamond; placing the diamond with the slotted nano-structure in a nitrogen source solution without metal elements, and performing pulse laser induced nitrogen injection by aligning laser to the area where the slotted nano-structure is located; and carrying out annealing treatment on the diamond subjected to pulse laser induced nitrogen injection to obtain the diamond with the NV color center. Nitrogen element shallow layer injection and nanoscale positioning in NV color center preparation are achieved at the same time.

The invention discloses semiconductor processing equipment, and belongs to the technical field of semiconductor processing, the semiconductor processing equipment comprises a cavity, a door body, an air inlet pipe and a blocking assembly, the door body can be connected with the cavity in a sealing manner to define a process cavity, the process cavity is used for accommodating a wafer boat, and the air inlet pipe and the blocking assembly are both arranged in the cavity. An opening of the air inlet pipe faces the door body; in the axial direction of the cavity, the blocking assembly is located between the door body and the air inlet pipe and comprises a plurality of blocking plates which are arranged at intervals in the axial direction, and in the plane perpendicular to the axial direction of the cavity, the projection of the outer edge of each blocking plate covers the projection of the wafer boat. The semiconductor process equipment can solve the problems that in the gas feeding process of existing semiconductor process equipment, due to the fact that gas flows to the furnace door, a sealing ring between the furnace door and the furnace body is prone to losing efficacy, sealing of the furnace body loses efficacy, and normal proceeding of the process is affected.

The present disclosure discloses a method for manufacturing a semiconductor epitaxial layer, including: forming a well region. A transition layer is formed by performing cyclic steps, where the cyclic steps includes: performing a first interface repair process to repair a defect exposed on the surface of a previous layer; and performing first epitaxial growth to form an undoped first epitaxial sublayer on the surface of the previous layer. A bulk layer of the semiconductor epitaxial layer is formed, including: performing a second interface repair process to repair a defect exposed on the surface of the transition layer; and performing second epitaxial growth to form the undoped bulk layer on the surface of the transition layer. The rate of the first epitaxial growth is less than the rate of the second epitaxial growth, and the thickness of the bulk layer is greater than the thickness of each first epitaxial sublayer.

This application relates to a P-type gallium oxide and a preparation method thereof. The preparation method of the P-type gallium oxide includes providing a substrate, the material of the substrate includes β-gallium oxide, and a co-doping of shallow-level acceptor impurities and deep-level acceptor impurities is formed on the substrate. Among them, the shallow-level acceptor impurities are elements of the same group as oxygen. When the deep-level acceptor impurities and the shallow-level acceptor impurities are co-doped, the deep-level acceptors of the deep-level acceptor impurities can combine with the acceptor levels of the shallow-level acceptor impurities, further pushing the Fermi level towards the valence band top. This combined effect significantly improves the stability of P-type conductivity of β-gallium oxide.

A film stack is formed a workpiece. The film stack is fabricated by sequentially depositing a carbon-doped silicon germanium stack and a silicon film to form a carbon-doped silicon-germanium and silicon mini-stack disposed on a substrate during a deposition cycle. The deposition cycle comprises exposing a workpiece including the substrate to a first gas including a first precursor to deposit a first silicon-germanium layer and exposing the workpiece to a second gas including the first precursor to deposit a carbon-silicon-germanium layer on the first silicon-germanium layer. Further, the deposition cycle includes exposing the workpiece to a third gas including the first precursor to deposit a second silicon-germanium layer on the carbon-silicon-germanium layer. The deposition cycle further includes exposing the workpiece to a fourth gas including a second precursor to deposit the silicon film on the second silicon-germanium layer. The second precursor differs from the first precursor.

The utility model provides a cadmium telluride series semiconductor crystal annealing device and a cadmium telluride series semiconductor crystal. The annealing device comprises: a crucible having a first zone and a second zone, the first zone being used for accommodating cadmium-containing chloride and / or indium-containing chloride, and the second zone being used for accommodating cadmium telluride series semiconductor crystals; the heating furnace comprises a furnace body and a heating device, the furnace body is used for containing the crucible, and the heating device is used for heating the crucible, so that the chloride containing cadmium and / or the chloride containing indium are / is molten into an annealing agent in a molten state; and the position adjusting device is connected with the heating furnace and is used for adjusting the position of the crucible accommodated in the furnace body, so that the cadmium telluride series semiconductor crystals are soaked in the annealing agent in the molten state, and the annealing agent in the molten state is used for annealing the cadmium telluride series semiconductor crystals. The annealing device can be used for preparing crystals with very good performance.

The invention belongs to the technical field of semiconductors, and particularly relates to a stripping method, a single crystal thin film preparation method applying the stripping method and a single crystal thin film. The stripping method comprises the steps that first ions and second ions are sequentially injected from the first surface of a functional wafer, an ion injection sheet comprising a thin film layer, a separation layer and a residual layer is formed, and the first ions and the second ions are gathered on the separation layer; the first ions are ions with characteristic absorption peaks, and the second ions are gas ions; the emission wavelength of the light source is within the characteristic absorption peak wavelength range of the first ions, and the first ions absorb light energy and convert the light energy into heat energy, so that the separation layer is rapidly heated to a high temperature, and the second ions are gasified into bubbles; and the ion implantation sheet is stripped from the separation layer. The separation layer is selectively heated through the light source to achieve stripping, local temperature rise of the ion implantation sheet and temperature rise are concentrated on the separation layer, when the stripping method is applied to preparation of the single crystal thin film, other areas except the separation layer are almost not heated, complete stripping of the single crystal thin film and reuse of the residual layer can be achieved, and meanwhile the available area and the yield of the thin film are improved.

The utility model provides a heating carrier and processing equipment, relates to the field of semiconductor or photovoltaic material processing, and solves the technical problem of low heating efficiency of a traditional reaction furnace. The heating carrier comprises at least two boat sheets which are arranged at intervals along a first direction and are configured to bear sheet materials; the connecting piece is configured to connect the at least two boat pieces; the at least one heating assembly is arranged on the side, away from the last boat piece, of the first boat piece, and / or the heating assembly is arranged on the side, away from the first boat piece, of the last boat piece, so that the first boat piece and / or the last boat piece form a heating boat piece; the heating assembly is configured to transfer heat to the sheet material by heating the boat sheet. As the heating assembly is arranged on one side or two sides of the at least two boat pieces, the distance between the heating assembly and the sheet-shaped material is small, and the heating efficiency and the heating uniformity are improved.

The invention discloses a method for preparing a blue diamond based on an MPCVD method, and aims to solve the problems that in the diamond growth process, boron-doped coloring growth has gray tone, and an electron irradiation method needs to be adjusted according to the growth batch of diamonds. The method for preparing the blue diamond comprises the following steps: S1, pretreating an HPHT diamond seed wafer, and ultrasonically cleaning a silicon wafer and a germanium wafer; s2, placing a cleaned silicon wafer and a cleaned germanium wafer around the pretreated seed crystal, and then performing etching treatment; s3, methane and hydrogen are introduced for microwave plasma chemical vapor deposition growth; s4, the diamond blank is taken out; s5, polycrystals on the surface of the diamond blank are cut off; and S6, high-temperature and high-pressure treatment. According to the method, Si and Ge elements are doped in the crystal growth process, SiV and GeV color centers are formed in a diamond blank, the diamond is blue through absorption of the SiV and GeV color centers in a near-infrared region, gray tone caused by doping of boron elements is avoided, and the method is suitable for batch production of blue diamonds.

The utility model relates to the technical field of photovoltaic cell production, in particular to an auxiliary heating mechanism and a diffusion furnace, the auxiliary heating mechanism comprises a silicon carbide paddle and a plurality of heating pieces wound on the surface of the silicon carbide paddle, the surface of each heating piece is provided with a heat conduction coating, and the heat conduction coatings are arranged on the surface of the silicon carbide paddle. The heating piece comprises a heating wire and a heat dissipation structure wrapping the surface of the heating wire. According to the utility model, the wound heating wire is additionally arranged on the silicon carbide paddle in the furnace body shell to assist in heating, so that non-uniform temperature distribution caused by the fact that the silicon carbide paddle is made of opaque materials and hinders heat radiation is compensated, and non-uniform sheet resistance of a silicon wafer in an area shielded by the silicon carbide paddle structure is reduced.

The invention provides an antimony-based chalcogenide film with (hk1) dominant orientation and a preparation method and application thereof, and belongs to the technical field of semiconductor photovoltaic materials. According to the method, the crystal orientation of the antimony-based chalcogenide film is regulated and controlled by doping PbI2 in situ under the simple solution method (water bath or hydrothermal) deposition condition, and research results show that the solution method is adopted to introduce PbI2, so that the antimony-based chalcogenide film can be remarkably induced to preferentially grow along the (hk1) direction, grain boundary scattering and inter-chain potential barriers are effectively weakened, and the crystal orientation of the antimony-based chalcogenide film is improved. The carrier longitudinal migration and collection efficiency is improved, so that the VOC loss is reduced, and the final battery performance is improved; the method provided by the invention not only provides a new thought for preparing the high-orientation antimony-based chalcogenide film, but also lays a technical foundation for design and optimization of a bottom battery material in a future laminated battery.

The utility model discloses a TOPCon battery piece production diffusion furnace with an air outlet circulation structure, the diffusion furnace comprises a furnace body and a preheating box, the furnace body is internally provided with multiple layers of heating cavities and air supply pipes penetrating through the heating cavities from top to bottom, one side of the top of the furnace body is provided with a first air outlet, and the other side of the top of the furnace body is provided with a second air outlet; the top of the first air outlet is connected with a second air inlet of the preheating box through a circulation pipeline, a heat exchange mechanism is arranged in the preheating box and comprises a plurality of heat exchange branch pipes, a moving plate, a rotating plate and a rotating motor, and the tops of the heat exchange branch pipes are fixed to the bottom of the rotating plate. According to the utility model, reaction gas can be uniformly fed into each heating cavity, so that the reaction gas can be in full contact with a silicon wafer, high-temperature tail gas discharged by the diffusion furnace is fed into the preheating box, and heat of the high-temperature tail gas can be recycled to heat the reaction gas, so that the temperature difference between the reaction gas and the interior of the diffusion furnace is reduced, and adverse effects on reaction are avoided.

The invention provides a TOPCon battery and a preparation method thereof, and boron diffusion equipment, and the preparation method of the TOPCon battery comprises the steps: providing a silicon substrate, placing the silicon substrate in a boron diffusion furnace, introducing nitrogen into a furnace mouth region of the boron diffusion furnace, introducing oxygen and boron trichloride into the boron diffusion furnace, introducing nitrogen gas into the furnace mouth region of the boron diffusion furnace, introducing nitrogen gas into the furnace mouth region of the boron diffusion furnace, introducing nitrogen gas into the furnace mouth region of the boron diffusion furnace, and introducing nitrogen gas into the furnace mouth region of the boron diffusion furnace, the ratio of the flow of the oxygen to the flow of the boron trichloride is alpha, and alpha is more than or equal to 3.5 and less than or equal to 4.5. The nitrogen can quickly purge reaction byproducts in a low-temperature area of the furnace mouth, and sufficient oxygen is provided to completely oxidize boron trichloride into a gaseous boron oxide precursor before the boron trichloride enters a high-temperature reaction area, so that the generation of viscous low-temperature boron oxide due to insufficient oxidation is avoided; and the generation and deposition of boron oxide crystals at the furnace mouth are inhibited from two dimensions of mass transfer process and chemical reaction completeness, and the yield and average photoelectric conversion efficiency of the TOPCon battery can be remarkably improved.

According to one embodiment, a method for manufacturing a semiconductor body (10) includes the steps of providing a first semiconductor layer (1) of SiC, introducing carbon into the first semiconductor layer to make at least a portion of the first semiconductor layer a C-rich region (11), and growing a second semiconductor layer (2) of SiC on the first semiconductor layer including at least a C-rich region.