657results about "Diffusion/doping" patented technology

According to the deformation detection integrated micro-nano sensor, a substrate is an SOI silicon wafer and comprises bottom layer silicon (1), a buried oxide layer (2) and top layer silicon (3) which are sequentially stacked and attached from bottom to top, a detection unit is arranged on the top layer silicon (3) and comprises a deformation detection unit (4), a temperature detection unit (5) and a vibration detection unit (6); the final detection value of the deformation takes a deformation parameter detected by the deformation detection unit (4) as basic data, and meanwhile, a temperature parameter detected by the temperature detection unit (5) and a vibration parameter detected by the vibration detection unit (6) are used for providing compensation for the deformation parameter detected by the deformation detection unit (4); the invention further provides a manufacturing method and a detection method. The piezoresistive effect of the semiconductor is used for detecting the strain, and the measurement sensitivity is remarkably improved.

A method for preparing a silicon carbide heterojunction normally-off high-electron-mobility transistor includes selecting an unintentionally doped n-type 4H-SiC chip as a substrate; growing a 4H—SiC transition layer on the substrate through isomorphic epitaxial growth, and growing a C face on the 4H—SiC transition layer through epitaxial growth; growing an unintentionally doped 3C—SiC potential well layer on the C face of the 4H—SiC transition layer; growing an n-type doped 4H—SiC barrier layer on the 3C—SiC potential well layer, and growing a Si face on the 4H—SiC barrier layer through epitaxial growth; growing an unintentionally doped 3C—SiC cap layer on the Si face of the 4H—SiC barrier layer; and producing electrodes and protective films, so as to obtain a 3C—SiC / 4H—SiC heterojunction normally-off single-channel high-electron-mobility transistor. The method allows two sides of the SiC heterojunction interface have homogeneous elements during preparation, thereby eliminating diffusive contamination and reducing process complexity.

A seed substrate for epitaxial growth has a support substrate, a planarizing layer of 0.5 to 3 μm provided on the top surface of the support substrate, and a seed crystal layer provided on the top surface of the planarizing layer. The support substrate includes a core of group III nitride polycrystalline ceramics and a 0.05 to 1.5 μm encapsulating layer that encapsulates the core having surface voids filled and flattened by Al or Si oxide, nitride, oxynitride, or a mixture thereof. The seed crystal layer is provided by thin-film transfer of 0.1 to 1.5 μm of the surface layer of Si <111> single crystal with oxidation-induced stacking faults (OSF) of less than 10 defects / cm2.

The invention provides a heterogeneous composite substrate and a manufacturing method thereof, and the manufacturing method comprises the steps: (1) carrying out the O ion implantation of a Si substrate, forming an O implantation layer, carrying out the C ion implantation, forming a C implantation layer on the O implantation layer, and obtaining a composite substrate precursor; (2) annealing and repairing the composite substrate precursor to convert the O injection layer into a SiO2 layer and convert the C injection layer into a SiC layer at the same time, and then performing post-processing to obtain a composite substrate; the composite substrate comprises a Si layer, a SiO2 layer and a SiC layer which are stacked in sequence; and (3) bonding the surface of one side, far away from the SiO2 layer, of the SiC layer in the composite substrate with the to-be-bonded surface of the SiC substrate to obtain the heterogeneous composite substrate. By adopting the method provided by the invention, the bonding strength of the heterogeneous composite substrate can be improved, and the quality of the heterogeneous composite substrate can be improved.

According to the preparation method of the heterogeneous wafer structure provided by the embodiment of the invention, the first bonding structure is provided; the first bonding structure comprises a first single crystal wafer, a first dielectric layer and a second single crystal wafer which are sequentially stacked, and a defect layer is arranged in the first single crystal wafer; providing a wafer structure; the wafer structure comprises a third single crystal wafer and a second dielectric layer located on the third single crystal wafer; etching the wafer structure from the surface of the second dielectric layer to form a symmetrical groove structure located on the surface of the third single crystal wafer; the depth of the symmetrical groove structure is equal to the thickness of the second dielectric layer; bonding the first bonding structure and the wafer structure to obtain a second bonding structure; the second bonding structure is subjected to annealing treatment, so that the second bonding structure is peeled off along the defect layer, the heterogeneous wafer structure is obtained, the annealing temperature of preparation of the heterogeneous wafer structure is effectively improved through the method, and the bonding strength and the reuse frequency of the heterogeneous wafer structure are increased.

A preparation method for a solar cell includes: providing a silicon wafer substrate having a first surface and a second surface, which is opposite to the first surface; forming a silicon-containing thin film comprising a doped layer on the first surface of the silicon wafer substrate, wherein the forming method for the doped layer comprises: forming a partially doped layer in an atmosphere in which the flow rate of a dopant gas source is 100-1000 sccm and the flow rate of silane is 1000-4000 sccm, and forming a remaining doped layer in an atmosphere in which the flow rate of the dopant gas source is 1500-3000 sccm and the flow rate of the silane remains unchanged; forming a patterned region; and performing a texturing treatment.

The invention belongs to the technical field of new energy materials, and discloses a fused salt auxiliary valence gradient doped modified single crystal positive electrode material and a preparation method and application thereof. The preparation method comprises the following steps: mixing a transition metal source, a lithium source, a manganese source and a molten salt auxiliary agent, sequentially carrying out first sintering and second sintering, and removing the molten salt auxiliary agent to obtain a doped modified single crystal positive electrode material precursor; and tempering the doped modified single-crystal positive electrode material precursor to obtain the fused salt auxiliary valence gradient doped modified single-crystal positive electrode material, the doped modified single crystal positive electrode material prepared by the invention can effectively avoid the capacity loss of the material, significantly reduce lattice mismatch in the lithium intercalation / deintercalation process, and relieve the volumetric strain in the charge-discharge process. Meanwhile, the formed M-O bond can enhance the structural stability of the material and inhibit the formation of microcracks of the material. The preparation method of the positive electrode material is convenient for industrial application, and provides a thought for commercial modification of the positive electrode material.

The invention discloses a low-resistance N-type gallium oxide crystal and a growth method thereof. The growth method comprises the following steps: pretreatment of raw materials: sintering a doped gallium oxide material block formed by mixing gallium oxide powder and doped raw material powder; crystal growth: heating the iraurita crucible to melt the doped gallium oxide material block, increasing the power of the medium-frequency induction coil to raise the temperature of the gallium oxide melt, keeping the temperature, cooling to the melting point of gallium oxide, keeping the melt state, firstly reducing the power of the medium-frequency induction coil to spontaneously nucleate at the cold core of the upper surface of the melt and realize the transverse growth of the nucleated crystal; reducing the power of the lower medium-frequency induction coil to enable the gallium oxide melt to grow from top to bottom until the gallium oxide melt completely grows into crystals; after crystal growth is finished, the temperature is reduced to 1200-1400 DEG C, heat preservation is conducted, cooling is conducted to the room temperature, and the low-resistance N-type gallium oxide crystals are obtained.The growth method is simple in process, the crystal growth speed is conveniently controlled, the crystal forming rate is increased, and large-scale mass production is achieved.

The invention provides a preparation method of a silicon carbide substrate, the silicon carbide substrate and a semiconductor device. The preparation method comprises the following steps: preprocessing a silicon carbide substrate raw material; performing neutron irradiation treatment on the material; and the material is subjected to annealing treatment. The silicon carbide substrate prepared by the preparation method provided by the invention can have relatively high mechanical property, conductivity, uniformity and stability.

The invention relates to a p-type silicon carbide epitaxial wafer, a preparation method thereof and a semiconductor device. The preparation method of the p-type silicon carbide epitaxial wafer comprises the following steps: placing a substrate in a reaction chamber; introducing source gas and diluent gas into the reaction chamber; applying radio frequency power to generate plasma in the reaction chamber; introducing a p-type doping source and carrier gas into the reaction chamber, wherein the p-type doping source comprises trimethylaluminum and triethyl boron; and growing a p-type silicon carbide epitaxial layer on one side of the substrate to obtain the p-type silicon carbide epitaxial wafer. According to the preparation method of the p-type silicon carbide epitaxial wafer, the trimethylaluminum and the triethyl boron are jointly used as the p-type doping source, the p-type silicon carbide epitaxial wafer is grown through the plasma enhanced chemical vapor deposition (PECVD) technology, and the doping efficiency can be improved.

The invention relates to the technical field of solar cells, and discloses a laser-assisted etching slotting method for preparing high-doping-concentration P + polycrystalline silicon and application. The grooving method comprises the following steps: preparing a tunneling SiOx layer and an i-polysi layer on the back surface of a silicon wafer; performing patterning etching by using green picosecond laser so as to remove the i-polysi layer and the tunneling SiOx layer in a laser region; removing impurities in a laser area through single-side acid pickling; boron diffusion is carried out, P + polycrystalline silicon is formed on the i-polysi layer in the non-laser area, a P + emission layer is generated in the laser area, and a BSG layer is generated on the back faces of the P + polycrystalline silicon and the P + emission layer; performing patterning etching by using green picosecond laser to remove the BSG layer in the laser area; and carrying out alkali wet etching to remove the P + emission layer in the laser area so as to form a notch. According to the grooving method, the notch with the ideal grooving depth is formed, P + polycrystalline silicon with high doping concentration can be formed in the non-laser area to reduce the contact resistivity, and the cost is low.

There is provided a gallium nitride single crystal substrate, which is a gallium nitride single crystal substrate having a diameter of 50 mm or more, with a low-index crystal plane closest to a main surface being (0001), and in which a Mn concentration in the substrate is 5×1017 cm−3 or more; and secondary ion mass spectrometry at a plurality of arbitrary points on the main surface reveals that a variation in the Mn concentration is within ±20% from an average value.

The invention discloses a conveying system and a diffusion furnace, and belongs to the technical field of semiconductor processing. In the conveying system, an air inlet assembly extends in the axial direction of a process chamber of the diffusion furnace and communicates with the process chamber. In the air inlet assembly, the first air inlet pipe is sleeved with the second air inlet pipe, and a conveying gap is formed between the second air inlet pipe and the first air inlet pipe. The gas outlet end of the first gas inlet pipe and the gas outlet end of the second gas inlet pipe are close to a furnace door of the diffusion furnace; one end of the first input pipeline is communicated with a process gas source, and the other end is communicated with the gas inlet end of the first gas inlet pipe; one end of the second input pipeline is communicated with the water source, and the other end of the second input pipeline is connected to the air inlet end of the second air inlet pipe. According to the conveying system, the problems that in the working process of an existing diffusion furnace, the air inlet pipeline is extremely prone to being blocked by boric acid, so that the air inlet pipeline needs to be frequently cleaned, the process efficiency is seriously affected, and the manpower and spare part cost is increased can be solved.

The utility model discloses a boron diffusion reaction intake system and reaction equipment, the boron diffusion reaction intake system comprises a boron source intake assembly and a reaction intake assembly, the boron source intake assembly comprises a first intake pipe, a first intake port is used for introducing a boron source, the first intake port is used for directly communicating with a reaction cavity, and the reaction intake assembly comprises a second intake pipe; the reaction gas inlet assembly comprises at least one second gas inlet pipe, a second gas inlet is used for introducing oxygen or nitrogen, and the second gas inlet pipe is isolated from the first gas inlet pipe; the reaction equipment comprises the boron diffusion reaction gas inlet system. According to the utility model, the first gas inlet pipe and the second gas inlet pipe are isolated from each other, and a boron source and other reaction gases are respectively fed through the first gas inlet pipe and the second gas inlet pipe, so that the boron source gas and oxygen are prevented from being mixed outside the reaction cavity, and the possibility that the boron source gas and the reaction gases react in advance before entering the reaction cavity is reduced; the influence of a gas inlet mode on a gas field in the reaction cavity is reduced, and the uniformity of sheet resistance of the silicon wafer is improved.

The spliced diffusion furnace pipe comprises a long-barrel-shaped furnace pipe outer wall and a furnace pipe body which is arranged in the furnace pipe outer wall and formed by splicing a plurality of heating pipes in the length direction of the furnace pipe outer wall, and the furnace pipe body comprises at least one first heating pipe and a second heating pipe which is located at the head end and / or the tail end and is adjacent to a furnace door. The first heating tube comprises a metal heating wire used for heating an inner cavity of the heating tube, the second heating tube comprises at least one group of electrode rod windings used for heating the inner cavity of the heating tube, and the electrode rod windings are silicon carbide rods or silicon molybdenum rods. According to the technical scheme, the spliced furnace pipe structure is designed, the silicon carbide rod or the silicon molybdenum rod is adopted at the opening for heating, the silicon carbide rod and the silicon molybdenum rod are ceramic heating bodies, the surface load can be designed to be very high and is about 10w / cm < 2 >, and a formed oxidation film is easier to resist stripping, so that the service life is greatly prolonged when the silicon carbide rod or the silicon molybdenum rod is used at the opening of the furnace pipe.

The present invention relates to the fields of ferroelectric single crystal technology and acousto-optical device technology, particularly to a silicon-based lead magnesium niobate (PbMn) single crystal piezoelectric wafer structure, preparation method, and application. The structure comprises a silicon substrate on which a silicon dioxide layer and a single crystal piezoelectric thin film layer are sequentially disposed; the single crystal piezoelectric thin film layer is a PbMn-PT single crystal, including a binary PMN-PT single crystal thin film or a ternary PIN-PMN-PT single crystal thin film. This piezoelectric wafer structure on a silicon substrate can be used to fabricate various high-performance piezoelectric MEMS sensors, actuators, and electro-optical modulator devices. The resulting surface acoustic wave (SAW) filters and thin film bulk acoustic wave (BAW) filters exhibit a relative bandwidth increase of over 50%, and the resulting electro-optical modulators exhibit lower half-wave voltage and higher electro-optical modulation efficiency. The device volume can be reduced by 10 times, better meeting the future 6G communication requirements for higher efficiency, higher integration, and miniaturization of MEMS devices. This provides a novel multilayer piezoelectric wafer structure for the miniaturization and integration of piezoelectric MEMS and optoelectronic devices.

The invention provides an air inlet device and semiconductor equipment. The gas inlet device comprises a flow uniformizing structure and a gas distribution structure. The flow uniformizing structure comprises a plurality of annular flow uniformizing cavities and a plurality of air inlet pipelines correspondingly communicating with the annular flow uniformizing cavities. A plurality of first air outlet holes which are uniformly distributed are formed in the radial outer ring side surface of each annular uniform flow cavity; the gas distribution structure comprises a plurality of annular gas distribution cavities which are coaxially arranged with the annular flow uniformizing cavity; and the plurality of second air outlet holes are non-uniformly distributed on the outer peripheral surface of the corresponding annular air distribution cavity. The gas distribution structure can move between a first position and a second position; at the first position, the gas distribution structure surrounds the periphery of the flow uniformizing structure, and the gas inlet end of each annular gas distribution cavity is in sealed communication with the first gas outlet hole, so that gas is discharged non-uniformly through the second gas outlet hole; and at the second position, the gas distribution structure is staggered from the peripheral surface of the flow uniformizing structure, so that the first gas outlet hole is exposed in the semiconductor process chamber, and uniform gas outlet is realized.

The invention relates to a gas phase annealing method of a cadmium zinc telluride crystal. The gas phase annealing method comprises the following steps: S1, detecting the type and the defect concentration of point defects in the cadmium zinc telluride crystal; s2, determining a corresponding gas phase source for annealing regulation and control according to a point defect detection result; s3, preparing a gas phase source film on the quartz plate through physical vapor deposition; s4, confirming the gas phase source gas pressure of annealing; and S5, respectively packaging the tellurium-zinc-cadmium wafer and the quartz plate deposited with the gas-phase source film at two ends of an annealing quartz tube, then placing the annealing quartz tube in an annealing furnace, respectively heating the two ends of the annealing quartz tube, and finally obtaining the CdZnTe crystal modified by gas-phase annealing. Compared with the prior art, the method has the advantages that the variety and content of the gas phase source can be regulated and controlled, and finally the tellurium-zinc-cadmium crystal of which the internal defects are remarkably reduced and the electrical property of the crystal is remarkably improved is obtained.

The invention discloses a multi-element differentiated distribution co-doped single-crystal high-nickel positive electrode material and a preparation method and application thereof.The material is doped with a first doping element and a second doping element, the first doping element is in gradient distribution with the concentration gradually increased from inside to outside in material particles, and the second doping element is in gradient distribution with the concentration gradually increased from inside to outside. The second doping elements are basically and uniformly distributed in the material particles; the first doping element is used for strengthening the surface stability of the material, and the second doping element is used for stabilizing the bulk phase structure of the material. The material is obtained by taking a lithium salt and a ternary positive electrode material precursor as raw materials, introducing a first doping source and a second doping source, mixing, ball-milling and calcining according to a preset stoichiometric ratio.

The invention provides a wafer boat and semiconductor process equipment. The wafer boat comprises a plurality of supporting assemblies which are arranged in the circumferential direction of the wafer boat at intervals, each supporting assembly comprises a plurality of supporting columns which are arranged in the circumferential direction of the wafer boat at intervals, and each supporting column is arranged in the direction parallel to the axial direction of the wafer boat; the plurality of supporting pieces are arranged at intervals in the direction parallel to the axial direction of the wafer boat; each supporting piece comprises at least one supporting part, the orthographic projection of each supporting part on the radial cross section of the wafer boat is in a groove shape with an opening facing the outer side of the wafer boat, and the two ends of each supporting part are connected with the two adjacent supporting columns respectively; the supporting pieces of the multiple supporting assemblies are arranged at the same height in a one-to-one correspondence mode and used for jointly supporting the wafer, and the uniformity of film forming on the surface of the wafer is improved.

An ion source includes a vaporizer, an arc chamber, and a heat shield. The vaporizer includes a crucible containing an aluminum-containing material and a heater that heats the crucible. The crucible has a gas inlet and a vapor outlet. The arc chamber generates a plasma inside of the arc chamber. The vapor outlet outputs vapor into the arc chamber through a wall of the arc chamber, and the heat shield is provided between the vaporizer and the wall of the arc chamber.

A high-uniformity SiC crystal, a crystal bar, a substrate and a semiconductor device are provided. The SiC crystal is obtained by direct growth through a PVT method without subsequent machining, and includes a facet region and a non-facet region. The facet region is located on an outer-circumference end face of the SiC crystal. A doping concentration change rate of the facet region is 1.5 times or above that of the non-facet region; and / or a carrier concentration change rate of the facet region is 5 times or above that of the non-facet region.

The invention provides a preparation method of a diamond NV color center. The preparation method comprises the following steps: preparing one or more slotted nano structures on the surface of diamond; placing the diamond with the slotted nano-structure in a nitrogen source solution without metal elements, and performing pulse laser induced nitrogen injection by aligning laser to the area where the slotted nano-structure is located; and carrying out annealing treatment on the diamond subjected to pulse laser induced nitrogen injection to obtain the diamond with the NV color center. Nitrogen element shallow layer injection and nanoscale positioning in NV color center preparation are achieved at the same time.

The invention discloses semiconductor processing equipment, and belongs to the technical field of semiconductor processing, the semiconductor processing equipment comprises a cavity, a door body, an air inlet pipe and a blocking assembly, the door body can be connected with the cavity in a sealing manner to define a process cavity, the process cavity is used for accommodating a wafer boat, and the air inlet pipe and the blocking assembly are both arranged in the cavity. An opening of the air inlet pipe faces the door body; in the axial direction of the cavity, the blocking assembly is located between the door body and the air inlet pipe and comprises a plurality of blocking plates which are arranged at intervals in the axial direction, and in the plane perpendicular to the axial direction of the cavity, the projection of the outer edge of each blocking plate covers the projection of the wafer boat. The semiconductor process equipment can solve the problems that in the gas feeding process of existing semiconductor process equipment, due to the fact that gas flows to the furnace door, a sealing ring between the furnace door and the furnace body is prone to losing efficacy, sealing of the furnace body loses efficacy, and normal proceeding of the process is affected.

The present disclosure discloses a method for manufacturing a semiconductor epitaxial layer, including: forming a well region. A transition layer is formed by performing cyclic steps, where the cyclic steps includes: performing a first interface repair process to repair a defect exposed on the surface of a previous layer; and performing first epitaxial growth to form an undoped first epitaxial sublayer on the surface of the previous layer. A bulk layer of the semiconductor epitaxial layer is formed, including: performing a second interface repair process to repair a defect exposed on the surface of the transition layer; and performing second epitaxial growth to form the undoped bulk layer on the surface of the transition layer. The rate of the first epitaxial growth is less than the rate of the second epitaxial growth, and the thickness of the bulk layer is greater than the thickness of each first epitaxial sublayer.

This application relates to a P-type gallium oxide and a preparation method thereof. The preparation method of the P-type gallium oxide includes providing a substrate, the material of the substrate includes β-gallium oxide, and a co-doping of shallow-level acceptor impurities and deep-level acceptor impurities is formed on the substrate. Among them, the shallow-level acceptor impurities are elements of the same group as oxygen. When the deep-level acceptor impurities and the shallow-level acceptor impurities are co-doped, the deep-level acceptors of the deep-level acceptor impurities can combine with the acceptor levels of the shallow-level acceptor impurities, further pushing the Fermi level towards the valence band top. This combined effect significantly improves the stability of P-type conductivity of β-gallium oxide.

The invention relates to a boron diffusion method, a TOPCon battery and a preparation method thereof, and the boron diffusion method comprises the following steps: placing a pretreated N-type silicon wafer in a diffusion furnace, and carrying out the pre-oxidation at a first temperature; performing constant source deposition at the first temperature; raising the temperature in the diffusion furnace from the first temperature to a second temperature, and performing limited source knot pushing at the second temperature; increasing the temperature in the diffusion furnace from the second temperature and then reducing the temperature, and carrying out gradient cooling oxidation. In the boron diffusion process, the oxide layer is prepared through gradient cooling oxidation, oxide layer phase change of different doping concentrations can be formed, the boron diffusion rate is regulated and controlled, the problem of surface boron depletion is solved, longitudinal P- / P + high-low junctions are further improved, surface energy band bending is reduced, and therefore the capacity of migration of carriers to an N-type region is improved.

A film stack is formed a workpiece. The film stack is fabricated by sequentially depositing a carbon-doped silicon germanium stack and a silicon film to form a carbon-doped silicon-germanium and silicon mini-stack disposed on a substrate during a deposition cycle. The deposition cycle comprises exposing a workpiece including the substrate to a first gas including a first precursor to deposit a first silicon-germanium layer and exposing the workpiece to a second gas including the first precursor to deposit a carbon-silicon-germanium layer on the first silicon-germanium layer. Further, the deposition cycle includes exposing the workpiece to a third gas including the first precursor to deposit a second silicon-germanium layer on the carbon-silicon-germanium layer. The deposition cycle further includes exposing the workpiece to a fourth gas including a second precursor to deposit the silicon film on the second silicon-germanium layer. The second precursor differs from the first precursor.

A furnace door structure for a diffusion furnace, and a diffusion furnace. The furnace door structure comprises a metal furnace door, a hanging assembly, and a heat radiation blocking piece, and the metal furnace door is movably connected to the heat radiation blocking piece by means of the hanging assembly. The heat radiation blocking piece in the present invention is hung on the metal furnace door to form a combined furnace door structure, thereby simultaneously avoiding the fragility of a furnace door made of a quartz material and the contamination of a furnace door made of a metal material to a diffusion process. Due to the use of hanging installation, installation and disassembly of the heat radiation blocking piece and the metal furnace door are easier, and adjustment is more convenient.

A digallium trioxide single crystal substrate having a circular main surface, wherein the diameter of the digallium trioxide single crystal substrate is 100 mm or more, the thickness of the digallium trioxide single crystal substrate is 600 μm or more, the digallium trioxide single crystal substrate comprises boron, and the concentration of boron is 4-200 mass ppm in glow discharge mass spectrometry.