223 results about "Electric stress" patented technology

A stress cone for reducing electrical stresses is disclosed for use on terminated ends of tubing encapsulated power cable used in surface applications in a subsurface well power system employing electric submersible pumps (ESPs). The stress cone comprises an annular section about a longitudinal axis for receiving a terminated end of the TEPC in its first end and for abutting the terminated metal TEPC end against a metal shoulder at its second end therein, and an insulation chamber axially aligned with and connected to the annular section. The chamber comprises a metal interior surface symmetrical about the axis. The insulated TEPC core (without outer metal sheath) passes through the insulation chamber along the axis and then exits. The ID of the TEPC metal sheath and the inside metal surface of the chamber form a smooth ground plane transition surface. Insulation material surrounds the TEPC insulation layer within the insulation chamber.

A nonvolatile semiconductor memory device includes a memory array in which a plurality of memory cells are arranged in a row direction and a column direction, each of the memory cells being formed by connecting one end of a variable resistive element for storing information according to a change in electric resistance caused by an electric stress and a drain of a selection transistor to each other on a semiconductor substrate, a voltage switch circuit for switching among a program voltage, an erase voltage and a read voltage to be applied to the source line and the bit line connected to the memory cell, and a pulse voltage applying circuit. In the state where the program voltage or erase voltage corresponding to the bit line and the source line is applied to the bit line and the source line connected to a memory cell to be programmed or erased in the memory array via the voltage switch circuit, the pulse voltage applying circuit applies a voltage pulse for programming or erasing to the word line connected to the gate electrode of the selection transistor connected to the memory cell.

Provided are a coplanar structure thin film transistor that allows a threshold voltage to change only a little under electric stress, and a method of manufacturing the same. The thin film transistor includes on a substrate at least: a gate electrode; a gate insulating layer; an oxide semiconductor layer including a source electrode, a drain electrode, and a channel region; a channel protection layer; and an interlayer insulating layer. The channel protection layer includes one or more layers, the layer in contact with the oxide semiconductor layer among the one or more layers being made of an insulating material containing oxygen, ends of the channel protection layer are thinner than a central part of the channel protection layer, the interlayer insulating layer contains hydrogen, and regions of the oxide semiconductor layer that are in direct contact with the interlayer insulating layer form the source electrode and the drain electrode.

A light-emitting display device which suppresses influence of characteristic variations of a driving transistor and characteristic shift caused by electrical stress. The device includes multiple pixels including an organic EL element (OLED) which emits light at a luminance determined based on supplied current and a drive circuit for supplying current to OLED based on a control voltage from a data line. The drive circuit includes a driving transistor (D-TFT) for OLED, a capacitor element, and multiple switch elements. D-TFT has a source terminal connected with an anode terminal of OLED. The capacitor and switch elements operate so that, when current is supplied from the drive circuit to OLED, a voltage difference between gate and source terminals of D-TFT is a sum of threshold voltage of the driving transistor and voltage determined from voltage of a drain terminal of the driving transistor and the control voltage during current setting period.

The invention provides a data writing method for writing data sequentially in a cross-point memory cell array having a variable resistive element whose electric resistance is changed by application of an electric stress. When data is sequentially written in memory cells in the same row or column, the writing order of the memory cells to be written is determined according to the length from an electric connection point to a selected memory cell to be written and the increase/decrease direction of the electric resistance of each selected memory cell changed by data writing, the electric connection point being between a write voltage applying circuit, which applies a data writing voltage to a same wiring of the selected word line or bit line connected to the selected memory cell, and the same wiring, and the data writing is executed based on the determined writing order.

The invention discloses a gas-protective submerged-arc welding digitalized power supply system for dual ARM (Automated Route Management) control and a control method thereof. The system comprises a case and a built-in circuit, wherein the built-in circuit comprises a main circuit unit and a main control unit; the main circuit unit is a full-bridge inverting main circuit of a limited bipolar soft switch; and an ARM9S3C2440 controller is used in the main control unit. In the control method, a corresponding welding mode is selected through the controller, the welding process is monitored by the main control unit and three-phase power frequency alternating current is converted by the main circuit unit to obtain the required smooth direct current with heavy flow and low voltage. The invention can provide two different welding processes of submerged-arc welding and gas-protective welding for one welding machine, realize the soft switch in all range, greatly reduce the switch loss and the electric stress, effectively reduce the electromagnetic interference of an inverting welding machine while improving the efficiency and saving energy and improve the electromagnetic compatibility and the reliability of the inverting welding machine.

The invention discloses a combined environment test method for an integrated circuit, which comprises the following steps of: S1) acquiring the highest test temperature, the lowest test temperature, the highest test temperature change rate delta TE, a test power density spectrum, a test humidity and a test electric stress according to the basic product information of the integrated circuit and the used environment information, S2) according to the test data, performing a temperature cycling test, a random vibration test and a humid test while respectively exerting a rated operational voltage, the maximum operating voltage and the minimum operating voltage on the integrated circuit, and S3) after finishing the tests, performing a functional test on the integrated circuit, confirming the integrated circuit invalid if the integrated circuit loses the function or any property parameter value exceeds a designed scope, otherwise, confirming the integrated circuit being in good condition. The invention can really simulate the actual using environment of the integrated circuit, quickly and completely arouse the faults of the products and provide a reference to improve the design and the manufacturing shortcomings of the integrated circuit.

The invention discloses a multi-stress limit determination method for an intelligent ammeter. The method comprises the following steps: determining the sensitive stress of the intelligent ammeter through FMEA (Failure Mode and Effects Analysis); respectively setting the stepping reinforcement stress tests of both temperature and electric stress; testing the output characteristics of the intelligent ammeter; processing the test result; and determining the mechanism consistency condition. The method provided by the invention is specially for determining the mechanism consistency of the intelligent ammeter and makes up the blank that a matched method specially researched and developed for the intelligent ammeter is unavailable in the present market. The conventional reinforcement test data of the intelligent ammeter is less, and can not be analyzed more accurately by adopting a traditional data processing method. The grey theory method provided by the invention can be used under the small-sample poor-information condition, thereby compensating defects when the reinforcement testing data is processed by the traditional method.

The invention discloses an electric stress relief adhesive for connecting thermal shrinkage cable accessories. The electric stress relief adhesive comprises ingredients of, by weight, 20-50 parts of elastomer, 20-50 parts of adhesion agent, 15-50 parts of conductive filling material, 0.5-5 parts of anti-oxidant, 2-5 parts of fire retardant and 0.5-1 part of lubricant. The electric stress relief adhesive for connecting thermal shrinkage cable accessories of the invention has good bonding intensity on aluminium, lead, copper and oil isolating pipe, has excellent bonding sealing, airtight, weatherability and aging resistance in an insulating cable joint, and has proper dielectric constant and volume resistivity, large tensile strength and good effect on mitigating and dispersing electric stress.

The invention provides a high dielectric constant silastic used for electric stress control and a preparation method and an application thereof. The silastic is prepared by the following components according to parts by weight: 40-70 parts of organopolysiloxane, 1-6 parts of organic hydrogenated polysiloxane, 0.8-3.0 parts of fluorine silicon multipolymer, 10-80 parts of base rubber, catalyst with routine type and routine dosage and inhibitor; the base rubber comprises the following components according to parts by weight: 30-45 parts of fumed silica treated by hydrophobization with organosilicon compound adopted, 25-40 parts of acetylene black and 10-20 parts of BaTiO3. The invention also provides a preparation method of the above silastic, comprising the following steps: each component and one or more of appropriate platinum catalyst, palladium catalyst or rhodium catalyst and/or butynol inhibitor are subjected to blending, refining, filtering and remilling to prepare the silastic. The invention also provides an application of the silastic, namely, the prepared gross rubber is sliced, extruded and formed by vulcanization to prepare the high dielectric constant silicone rubber tube.

The invention discloses electrical stress control hot melting composition which comprises components by weight as follows: 100 parts of matrix resin, 5-20 parts of tackifying resin, 40-120 parts of filler with high dielectric constant, 1-30 pats of conductive filler and 1-3 parts of an antioxidant. The invention further discloses an electrical stress control element provided with a hot melting interface. An electrical stress control tube is formed when the hot melting composition is composited with the inner wall of a heat shrink tubing, an electrical stress control tape is formed when the hot melting composition is composited with a base band, and the thickness of the hot melting composition interface layer is in a range from 5 mu m to 5 mm.

The invention discloses a quick evaluation method for ultimate stress strength of an integrated circuit for spaceflight. The quick evaluation method includes temperature stepping stress test, quick temperature change stress test, vibration stepping stress test, and temperature and vibration comprehensive stress test. The whole process of each test tests the functions of a sample to be evaluated and records fault phenomenons. The other special stress can be exerted to the sample to be evaluated when exerting temperature or vibration stress, such as electric stress. According to the quick evaluation method for the ultimate stress strength of the integrated circuit for the spaceflight, through exerting a series of combined tests, the failure time of the product is reduced, and the evaluation test finishing time is reduced to one week from the original six months to one year; through the heat, power and electric stress combined test, a superimposed or coordination effect is formed, and the evaluation test completeness and precision are greatly improved. Multiple verification results prove that the product fault mode coverage rate discovered in the test evaluation can arrive at more than 98%.

The invention provides a discharge lamp lighting device, a power supply device and an illuminator, which can prevent an overlarge electric stress on a circuit element or the discharge clamp after lighting the lamp. The device is provided with a direct current power supply part, a resonance part formed a resonance circuit together with the discharge lamp. A switch part for switching the DC power supply part and the resonance part, and a driving part for driving the switch part to output an alternated current to the discharge lamp from the resonance part through the voltage frequencies on two ends of a controlling capacitor. After the driving part is started and still cannot work in a preset stopping time T1, the driving part starts to work after stopping for the stopping time T1. The voltages on two ends of the capacitor can be stabled in the stopping time T1, so the overlarge electric stress on the circuit element or the discharge clamp can be avoided after starting, even if starting again after stopping for a short period of time.

The invention discloses an in-wafer reliability screening method for a GaN HEMT (High Electron Mobility Transistor) device. The in-wafer reliability screening method is characterized by comprising the following steps that: firstly, in-wafer electroluminescence spectrum testing platform is established, a GaN heterojunction HEMT device wafer is placed on a probe platform in a darkroom, and then probes are respectively pressed on a grid electrode, a source electrode and a leakage electrode; and then, the source electrode is grounded, certain forward bias is applied to the leakage electrode, backward bias Vgs, which changes from pinch-off voltage Vp to 0V, is applied to the grid electrode, a change relationship between the luminous intensity of a GaN heterojunction HEMT device and grid voltage is tested by virtue of a spectrum testing system, the luminescence spectrum of the device is tested under the adopted bias point Vgsm with the largest luminous intensity, and then the spectrum is analyzed to evaluate the reliability of the device. The in-wafer reliability screening method has the advantages that in-wafer screening can be realized; a series of reliability screening preparation procedures, such as scribing and packaging, is eliminated without long-time electric stress; and the reliability screening time is shortened, costs are saved, and work efficiency is improved.

The invention relates to a method for processing the reducing sealing element. It comprises: first, processing the sealing element; then compressing the sealing element radial; adding the sealing element into reducing mould; processing uniform reducing deform force on the sealing element, while rotating and compressing it at the same time, to make the deformation of reducing neck to 0.8-0.92%. The invention has the advantages that: said sealing element can be used in the electric connection and sealing between the inner and outer parts of support container, especially used in the safe frame of atomic reactor or research reactor, to effectively prevent electric stress power, high temperature, high pressure, temperature change, accumulated radiation, chemical corrosion, and vibrations. It can confirm the sealing and electric properties of support container.

The invention relates to a BGA (ball grid array) welding point acceleration service life prediction method, which comprises the following steps that (a) n BGA welding point samples are randomly selected, wherein the n is greater than or equal to 5, and the BGA welding point samples are subjected to environment stress screening processing; (b) the samples processed in the step (a) are subjected to integral stress processing, and the integral stress processing comprises second temperature circulation processing, random vibration processing and electric stress processing on the samples processed in the step (a), and in addition, the sample failure time is recorded; (c) the samples processed in the step (b) are subjected to third temperature circulation processing; (d) a model shown in a formula (III) is used for calculating an acceleration factor, and finally, a formula (IV) is used for calculating the use average failure before time MTTR<use> for predicting the service life of the BGA welding point. The invention also provides application of the method to the preparation of electronic products and mechanical equipment.

A novel electronic product failure rate prediction correcting method includes three steps: step 1, analyzing components of a prediction unit, obtaining composition of composed components of the prediction unit, and obtaining basic information of each composed component, step 2, obtaining an electrical stress value of each composed component of the prediction unit under the normal working state through the method of electrical stress automatic emulation, substituting an electrical stress parametric model which is provided by a handbook to obtain electrical stress parameters of each component of the prediction unit, and step 3, expanding failure rate prediction. A simple method and predicted results which are accurate can be obtained through the novel electronic product failure rate prediction correcting method, and method support can be provided for accuracy of the electronic products and convenience prediction. The novel electronic product failure rate prediction correcting method has preferable practical values and wide application prospects in the technical field of electronic product reliability prediction.

The invention relates to a flat panel television reliability test method. The method comprises the following steps: (a) carrying out stepping decrease on a temperature to 40 DEG C below zero, and testing a core plate at each temperature point; (b) carrying out stepping increase on the temperature to 80 DEG C, and testing the core plate at each temperature point; (c) testing the core plate in a cycle of 30 DEG C below zero and 80 DEG C; (d) carrying out 4 Grms to 40 Grms vibration stepping increase, and testing the core plate at each vibration point; (e) testing the core plate in the cycle of 30 DEG C below zero and 80 DEG C, and carrying out 6 Grms to 28 Grms vibration stepping increase test on the core plate simultaneously; (f) testing a whole machine at 40 DEG C to 65 DEG C; (g) testing the whole machine at 0 DEG C to 32 DEG C; (h) testing the whole machine at 0.1 Grms to 0.5 Grms; wherein in steps of (a) to (h), alternating current electric stress of 100V/47Hz and 240V/63 Hz are applied to a test product alternatively. According to the method, problems of low efficiency and high cost in a traditional reliability test can be effectively solved, and a reliability level of the product can be raised obviously and greatly.