Quick evaluation method for ultimate stress strength of integrated circuit for spaceflight

Abstract

The invention discloses a quick evaluation method for ultimate stress strength of an integrated circuit for spaceflight. The quick evaluation method includes temperature stepping stress test, quick temperature change stress test, vibration stepping stress test, and temperature and vibration comprehensive stress test. The whole process of each test tests the functions of a sample to be evaluated and records fault phenomenons. The other special stress can be exerted to the sample to be evaluated when exerting temperature or vibration stress, such as electric stress. According to the quick evaluation method for the ultimate stress strength of the integrated circuit for the spaceflight, through exerting a series of combined tests, the failure time of the product is reduced, and the evaluation test finishing time is reduced to one week from the original six months to one year; through the heat, power and electric stress combined test, a superimposed or coordination effect is formed, and the evaluation test completeness and precision are greatly improved. Multiple verification results prove that the product fault mode coverage rate discovered in the test evaluation can arrive at more than 98%.

Description

technical field [0001] The invention relates to the field of reliability evaluation of integrated circuits, in particular to a rapid evaluation method for the ultimate stress intensity of integrated circuits used in aerospace. Background technique [0002] The ultimate stress strength evaluation is an experimental method to subject the tested object to different stresses, and then discover the design limit and potential weakness. Through the aerospace environment limit stress intensity evaluation test, the working limit and damage limit value of aerospace integrated circuit products can be obtained, and the reliability design margin of products in aerospace applications can be fully understood, thereby improving product design. [0003] At present, the most widely used method is the highly accelerated life test method. This method is a method of applying step stress to the product, discovering product defects, operating design margins and structural strength limits at an ea...

AI Technical Summary

Problems solved by technology

[0004] The main disadvantages of the existing technology are: first, the lack of test function monitoring requirements and methods; second, the lack of comprehensive stress evaluation methods; third, the working limit and damage limit of the product are not distinguished

[0005] The above shortcomings have led to the inability of the existing technology to fully evaluate the reliability of integrated circuits under aerospace comprehensive stress conditions, and the evaluation results have large deviations

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