94results about How to "Reduce dislocation defects" patented technology

A method for melting a silicon starting material can suppress silica (SiO2) from melting out from a quartz crucible wherein the silicon starting material is melted and can provide a high-quality silicon single crystal in a high yield. The growth method comprises melting the silicon starting material charged in the crucible while applying thereto a static magnetic field, contacting a seed crystal to a surface of the silicon melt, and pulling the seed crystal upwardly to solidify the contacted melt. The silicon starting material charged in the crucible, which is under melting, is applied with a static magnetic field such as a Cusp magnetic field, a horizontal magnetic field and/or a vertical magnetic field. The application can control heat convection occurring in the crucible during the course of the melting of the starting material, thereby obtaining a silicon single crystal having a reduced number of dislocation defects.

The invention provides a GaN-based LED chip extending and growing method for reducing dislocation defects, comprising the following steps of: (1) firstly, growing a low-temperature GaN buffer layer or AlxGal-xN buffer layer on a substrate, and then growing a high-temperature undoped GaN layer on the buffer layer; (2) regulating the growing temperature in a reaction chamber to 600DEG C to 1100 DEG C ,and then independently introducing CP2Mg and NH3 into the reaction chamber, reacting the CP2Mg with the NH3 to form MgN on the high-temperature undoped GaN layer made in step (1), wherein the sizes and density of the holes are controlled through the time for introducing the CP2Mg; (3) continuously growing other extending materials of a GaN-based LED chip according to the normal method. The invention adopts the MgN to make a nano masking figure in situ to reduce the dislocation defects in a GaN-based material. Compared with SiN masking, the invention has no corrosion on the GaN material when making the MgN masking, and therefore, the GaN having no a masking position can not introduce more defects, and the GaN material with higher quality can be acquired.

This invention is about a window interface layer in a light-emitting diode which comprises an n-type GaAs substrate with an n-type ohmic electrode at the bottom side thereof; an n-type AlGaInP cladding layer formed atop the substrate; an undoped AlGaInP active layer formed atop the n-type cladding layer; a p-AlGaInP cladding layer formed atop the active layer; a p-type window layer made of GaP; a p-type ohmic electrode formed atop the p-type window layer; and a highly doped p-type interface layer made of Ga_xIn_1-xP (0.6≦x≦0.9) and interposed between the p-type cladding layer and p-type window layer wherein the highly doped p-GaInP interface layer possesses a band gap which is higher than that of the active layer and, however, smaller than that of the p-type cladding layer, and wherein the lattice constant lies between GaAs and GaP. In this way, the p-GaInP interface layer is interposed between a p-GaP window layer and a p-AlGaInP cladding layer for enhancing the film quality and the luminous efficiency as well as improving the electric property.

The invention relates to an improved falling crucible method growth method for compound semiconductor arsenide gallium monocrystal. The growth method comprises the following steps: a multi-position falling crucible furnace is used for the growth of compound semiconductor GaAs monocrystal; the furnace is designed with a plurality of positions, and can be used for the growth of a plurality of crystals; a raw material for high-purity arsenic-enriched multicrystal GaAs is synthesized first, and generally, the arsenic-enriched quantity is not more than 1mol percent; the raw material is fed into a PBN crucible with the bottom provided with crystal seed and seed crystal, and the PBN crucible is placed inside the static stable falling crucible furnace; the falling crucible furnace is designed with three temperature zones, namely a high-temperature zone T1, a gradient zone T2 and a low-temperature zone T3 which respectively plays a role in material smelting, growth and heat preservation; moreover, the furnace temperature is controlled to between 1,250 and 1,290 DEG C, and the position of the crucible is adjusted so as to ensure that the top of the seed crystal is molten; then the temperature is reduced at the speed between 0.2 and 3 millimeters/hour so as to start crystal growth; and when crystal growth is finished, in situ annealing of the crystal is carried out through adjusting the position of the crucible and controlling the furnace temperature. The improved falling crucible growth method has the advantages that the growth method combines the advantages of the prior VB method and VGF method, and adopts a plurality of crucibles so as to increase crystal yield; moreover, an in situ annealing method is adopted to overcome the disadvantage of dislocation caused by thermal stress.

The invention discloses a light-emitting diode with a composite polar face electron blocking layer. The light-emitting diode comprises a substrate (101), a metal polar face n-type nitride layer (102), a metal polar face multiple quantum well layer (103), a metal polar face p-type nitride layer (104), a composite polar face p-type electron blocking layer (105) composed of a metal polar face p-type electron blocking layer (1051) and a nitrogen polar face p-type electron blocking layer (1052), a nitrogen polar face p-type nitride layer (106), an n electrode (7) arranged on the metal polar face n-type nitride layer and a p electrode (8) arranged on the nitrogen polar face p-type nitride layer, and the layers and the electrodes are arranged sequentially from bottom to top. A high electronic barrier is formed on a conduction band by the composite polar face electron blocking layer and blocks electrons from crossing a multiple quantum well active region to enter a p-type region, leakage currents can be reduced, and the probability of radiative recombination of the electrons and holes is improved.

A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source/drain regions. Source/drain regions are implanted or grown by a selective epitaxial growth.

The invention relates to a rectangular patterned Si substrate AlN template for a GaN semiconductor material epitaxy. The rectangular patterned Si substrate AlN template comprises a Si substrate and an AlN template layer epitaxially growing on the Si substrate with a crystal plane (111) as a crystal orientation, a plurality of mutually perpendicular strip-shaped grooves are etched on the AlN template layer to form a plurality of rectangular platforms which are independent with each other. The invention also relates to a method for preparing the patterned Si substrate AlN template. The method comprises the following steps of cleaning the substrate, growing the AlN layer and etching the rectangular platform. According to the rectangular patterned Si substrate AlN template for the GaN semiconductor material epitaxy, the yield is high and the cost is low, the prepared products have good uniformity and high quality.

The invention relates to a preparation method of a polycrystalline silicon ingot. The method comprises the following steps: (1) a binding agent, a dispersing agent, and silicon particles of which the purity is above 99.9 percent and the diameter is between 1 [mu]m and 5,000 [mu]m, are added into deionized water, a pulp is obtained after uniform mixing, and the mass percentage of the silicon particles in the pulp is not less than 50 percent; (2) in a quartz crucible with a silicon nitride coating on the inner surface, the pulp is applied on the surface of the silicon nitride coating through spray coating, roller coating or brush coating, so as to form a pulp layer with a thickness between 1 mm and 10 mm; the crucible with a silicon coating is obtained after drying; (3) the crucible with the silicon coating is sent into a polycrystalline silicon ingot furnace after being loaded with silicon materials, the silicon materials are heated after vacuum pumping, a silicon material melt is cooled for polycrystalline silicon growth after the silicon materials are completely molten, and the polycrystalline silicon ingot is obtained through annealing cooling after the polycrystalline silicon growth is completed. The polycrystalline silicon ingot obtained through the method can be used for the manufacturing of a solar battery, so that the average battery efficiency of a silicon wafer exceeds 18 percent.

The invention discloses a preparation method of polycrystalline silicon. According to the method, the twin crystal growth control technology is adopted, the ordinary polycrystalline process is optimized, a heat insulation cage is quickly opened, and the opening of the heat insulation cage is adjusted to be 6-8cm; at the initial stage of growth of the crystal, the temperature of a heater is adjusted to be 1425-1440 DEG C, the heat insulation cage is slowly lifted, a layer of uniform dendritic crystal grows vertically on a nucleation source layer along the bottom of a crucible, then dendritic crystal is taken as the seed crystal, and vertically upward directionally grows to form the polycrystalline silicon. The polycrystalline silicon prepared by the invention contains a great quantity of twin crystals, as the twin crystals have the advantages that the interfacial energy of the twin crystals is low, the twin crystals are relatively more stable, and the like, and the polycrystalline silicon prepared by the method has the advantage of few dislocation defects, the battery efficiency of the polycrystalline silicon is higher than that of the ordinary polycrystalline silicon for 0.2-0.4%, the average battery efficiency of a whole silicon wafer reaches 17.5%, and the highest efficiency reaches 18.0%.

The invention relates to a seed crystal jointing structure for oriented solidification of cast ingots. The seed crystal jointing structure comprises jointed seed crystal blocks, wherein jointing surface betweens two seed crystal blocks are planes which are vertical to the bottom of a crucible; a transverse columnar hole vertical to the jointing planes is formed in each seed crystal block; after adjacent seed crystal blocks are jointed, the transverse columnar holes are jointed to form a bar-shaped columnar cavity; a silicon rod inserts the columnar cavity. The transverse columnar holes are formed in the seed crystal blocks; two ends of the silicon rod insert the columnar holes of adjacent seed crystal blocks, thus jointing of the seed crystal blocks is realized; the jointing manner has a mortise-and-tenon jointing structure, thus lamination of the seed crystal jointing surfaces is improved. During heating, seed crystal at the edges is expanded by heating and the mortise-and-tenon jointing structure becomes relatively tight, thus expanding of seams caused by wrapped edges of the seed crystal blocks is prevented. The silicon rod and the columnar holes can be processed at one time through a drilling machine and are easily realized in industries; the jointing (inserting) method is simple, is easy to be mastered by operators and has relatively high practical value.

The invention discloses an ultraviolet LED with a polarized doped composite polar surface electron blocking layer. The device comprises a substrate arranged in sequence from bottom to top, the devicecomprises a low-temperature AIN nucleating layer, a high-temperature AlN intermediate layer, a non-doped AlGaN buffer layer, an n-type AlGaN layer, an Alx1Ga (1-x) 1N/Alx2Ga (1-x) 2N multi-quantum well active region, a polarization doped composite polar surface electron blocking layer and a p-type Alx5Ga (1-x) 5N layer, an n-type ohmic electrode is arranged on the n-type AlGaN layer; wherein a p-type ohmic electrode is arranged on the p-type Alx5Ga1-x5N layer, and the polarization doped composite polar surface electron barrier layer comprises a nitrogen polar surface p-type Alx3Ga1-x3N electron barrier layer and a metal polar surface p-type Alx4Ga1-x4N electron barrier layer which are arranged from bottom to top. The polarized doped composite polar surface electron barrier layer has higherelectron barrier layer hole concentration, and hole injection of the p-type Alx5Ga1-x5N layer is facilitated; lattice mismatch between the active region and the electron blocking layer is reduced, and the crystal quality of the epitaxial layer is improved; the radiation recombination efficiency of electron holes in an active region is improved, and the light-emitting efficiency of the ultravioletlight-emitting diode is improved.

The invention discloses a light emitting diode epitaxial wafer and a preparation method thereof, which belong to the field of light emitting diode manufacturing. The AlGaN sub-layers and the first GaNsub-layers which are alternately stacked can release certain stress in the growth process, and dislocation defects accumulated in the first composite layer are few. The buffer layer further comprisesa second composite layer stacked on the first composite layer, and the structure of the second composite layer can be a second GaN sub-layer and a MgN sub-layer which are alternately stacked, and a second GaN sub-layer and a BN sub-layer which are alternately stacked. The Mg atoms and B atoms in the BN sub-layer are small in particle size, vacancies generated by defects and dislocations in crystals can be filled in the growth process, so that the formation of the dislocations and the defects is reduced, the crystal quality of the buffer layer is improved, and the luminous efficiency of the finally obtained light-emitting diode epitaxial wafer is also improved.

To provide semiconductor films for enabling semiconductor light emitting devices particularly having excellent luminous efficiency as compared with conventional devices to be manufactured with high yields, and semiconductor light emitting devices using the films, the present invention provides an optical substrate with a concavo-convex structure (20) formed on a part or the whole of a main surface, where the concavo-convex structure has regular toothless portions. The concavo-convex structure is comprised of convex portions (21), inter-convex portion bottom portions (flat portions) (22), and a concave portion (23) (toothless portion) having a flat plane in a position lower than a main surface formed of the inter-convex bottom portions. Further, it is preferable that the convex portions are arranged with an average pitch P0, the toothless portions are disposed on vertexes of a regular polygon, or disposed on a side of the regular polygon connecting between the vertexes, and that a length of the side of the regular polygon is longer than the average pitch P0.