12465results about "Single crystal growth details" patented technology

In a process for producing an oriented inorganic crystalline film, a non-monocrystalline film containing inorganic crystalline particles is formed on a substrate by a liquid phase technique using a raw-material solution which contains a raw material and an organic solvent, where the inorganic crystalline particles have a layered crystal structure and are contained in the raw material. Then, the non-monocrystalline film is crystallized by heating the non-monocrystalline film to a temperature equal to or higher than the crystallization temperature of the non-monocrystalline film so that part of the inorganic crystalline particles act as crystal nuclei.

A laminated structure comprises a first layer comprising a crystal with six-fold symmetry, and a second layer comprising a metal oxynitride crystal formed on the first layer, wherein the second layer comprises at least one element selected from the group consisting of In, Ga, Si, Ge and Al, N, O and Zn, as main elements, and wherein the second layer has in-plane orientation.

PCT No. PCT/JP98/01640 Sec. 371 Date Dec. 9, 1998 Sec. 102(e) Date Dec. 9, 1998 PCT Filed Apr. 9, 1998 PCT Pub. No. WO98/47170 PCT Pub. Date Oct. 22, 1998A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.

A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires which may be embedded in a matrix. The conductive layer is optically transparent and flexible. It can be coated or laminated onto a variety of substrates, including flexible and rigid substrates.

A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and my have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be a single crystal and may be free-standing. Such a semiconductor may be either lightly n-doped, heavily n-doped, lightly p-doped or heavily p-doped. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor. Two or more of such a semiconductors, including an array of such semiconductors, may be combined to form devices, for example, to form a crossed p-n junction of a device. Such devices at certain sizes may exhibit quantum confinement and other quantum phenomena, and the wavelength of light emitted from one or more of such semiconductors may be controlled by selecting a width of such semiconductors. Such semiconductors and device made therefrom may be used for a variety of applications.

Embodiments of the invention generally provide a method for depositing films or layers using a UV source during a photoexcitation process. The films are deposited on a substrate and usually contain a material, such as silicon (e.g., epitaxy, crystalline, microcrystalline, polysilicon, or amorphous), silicon oxide, silicon nitride, silicon oxynitride, or other silicon-containing materials. The photoexcitation process may expose the substrate and/or gases to an energy beam or flux prior to, during, or subsequent a deposition process. Therefore, the photoexcitation process may be used to pre-treat or post-treat the substrate or material, to deposit the silicon-containing material, and to enhance chamber cleaning processes. Attributes of the method that are enhanced by the UV photoexcitation process include removing native oxides prior to deposition, removing volatiles from deposited films, increasing surface energy of the deposited films, increasing the excitation energy of precursors, reducing deposition time, and reducing deposition temperature.

One or more highly-oriented, multi-walled carbon nanotubes are grown on an outer surface of a substrate initially disposed with a catalyst film or catalyst nano-dot by plasma enhanced hot filament chemical vapor deposition of a carbon source gas and a catalyst gas at temperatures between 300° C. and 3000° C. The carbon nanotubes range from 4 to 500 nm in diameter and 0.1 to 50 μm in length depending on growth conditions. Carbon nanotube density can exceed 10⁴ nanotubes/mm². Acetylene is used as the carbon source gas, and ammonia is used as the catalyst gas. Plasma intensity, carbon source gas to catalyst gas ratio and their flow rates, catalyst film thickness, and temperature of chemical vapor deposition affect the lengths, diameters, density, and uniformity of the carbon nanotubes. The carbon nanotubes of the present invention are useful in electrochemical applications as well as in electron emission, structural composite, material storage, and microelectrode applications.

A process for depositing polycrystalline silicon on substrates, including foreign substrates, occurs in a chamber at about atmospheric pressure, wherein a temperature gradient is formed, and both the atmospheric pressure and the temperature gradient are maintained throughout the process. Formation of a vapor barrier within the chamber that precludes exit of the constituent chemicals, which include silicon, iodine, silicon diiodide, and silicon tetraiodide. The deposition occurs beneath the vapor barrier. One embodiment of the process also includes the use of a blanketing gas that precludes the entrance of oxygen or other impurities. The process is capable of repetition without the need to reset the deposition zone conditions.

Improved apparatus and method for SMFD ALD include a method designed to enhance chemical utilization as well as an apparatus that implements lower conductance out of SMFD-ALD process chamber while maintaining full compatibility with standard wafer transport. Improved SMFD source apparatuses (700, 700′, 700″) and methods from volatile and non-volatile liquid and solid precursors are disclosed, e.g., a method for substantially controlling the vapor pressure of a chemical source (722) within a source space comprising: sensing the accumulation of the chemical on a sensing surface (711); and controlling the temperature of the chemical source depending on said sensed accumulation.

Embodiments of the invention generally relate to methods for forming silicon-germanium-tin alloy epitaxial layers, germanium-tin alloy epitaxial layers, and germanium epitaxial layers that may be doped with boron, phosphorus, arsenic, or other n-type or p-type dopants. The methods generally include positioning a substrate in a processing chamber. A germanium precursor gas is then introduced into the chamber concurrently with a stressor precursor gas, such as a tin precursor gas, to form an epitaxial layer. The flow of the germanium gas is then halted, and an etchant gas is introduced into the chamber. An etch back is then performed while in the presence of the stressor precursor gas used in the formation of the epitaxial film. The flow of the etchant gas is then stopped, and the cycle may then be repeated. In addition to or as an alternative to the etch back process, an annealing processing may be performed.

The present invention is an apparatus for deliverying high purity gallium trichloride in the vapor phase to a gallium nitride reactor, comprising; a source of carrier gas at an elevated pressure; a purifier to remove moisture from the carrier gas; a heater capable of heating the carrier gas to at least 80° C.; a container having a supply of gallium trichloride, a valve controlled inlet for the carrier gas having a dip tube with an outlet below the level of the gallium trichloride, a valve controlled outlet for removing the carrier gas and entrained gallium trichloride; a heater capable of heating sufficient to melt the gallium trichloride; a delivery line connected to the valve controlled outlet for carrying the entrained gallium trichloride to a reaction zone for gallium nitride. A process is also described for the apparatus.

A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 500 microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.

A method for growth and fabrication of semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga, Al, In, B)N template or nucleation layer on the substrate, and growing the semipolar (Ga, Al, In, B)N thin films, heterostructures or devices on the planar semipolar (Ga, Al, In, B)N template or nucleation layer. The method results in a large area of the semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices being parallel to the substrate surface.

Scanning Laser Epitaxy (SLE) is a layer-by-layer additive manufacturing process that allows for the fabrication of three-dimensional objects with specified microstructure through the controlled melting and re-solidification of a metal powders placed atop a base substrate. SLE can be used to repair single crystal (SX) turbine airfoils, for example, as well as the manufacture functionally graded turbine components. The SLE process is capable of creating equiaxed, directionally solidified, and SX structures. Real-time feedback control schemes based upon an offline model can be used both to create specified defect free microstructures and to improve the repeatability of the process. Control schemes can be used based upon temperature data feedback provided at high frame rate by a thermal imaging camera as well as a melt-pool viewing video microscope. A real-time control scheme can deliver the capability of creating engine ready net shape turbine components from raw powder material.

Non-polar or semi-polar (Al, Ga, In)N substrates are fabricated by re-growth of (Al, Ga, In)N crystal on (Al, Ga, In)N seed crystals, wherein the size of the seed crystal expands or is increased in the lateral and vertical directions, resulting in larger sizes of non-polar and semi-polar substrates useful for optoelectronic and microelectronic devices. One or more non-polar or semi-polar substrates may be sliced from the re-grown crystal. The lateral growth rate may be greater than the vertical growth rate. The seed crystal may be a non-polar seed crystal. The seed crystal may have crystalline edges of equivalent crystallographic orientation

A method for the production of a robust, chemically stable, crystalline, passivated nanoparticle and composition containing the same, that emit light with high efficiencies and size-tunable and excitation energy tunable color. The methods include the thermal degradation of a precursor molecule in the presence of a capping agent at high temperature and elevated pressure. A particular composition prepared by the methods is a passivated silicon nanoparticle composition displaying discrete optical transitions.

This invention relates to processes for the assembly of three-dimensional structures having periodicities on the scale of optical wavelengths, and at both smaller and larger dimensions, as well as compositions and applications therefore. Invention embodiments involve the self assembly of three-dimensionally periodic arrays of spherical particles, the processing of these arrays so that both infiltration and extraction processes can occur, one or more infiltration steps for these periodic arrays, and, in some instances, extraction steps. The product articles are three-dimensionally periodic on a scale where conventional processing methods cannot be used. Articles and materials made by these processes are useful as thermoelectrics and thermionics, electrochromic display elements, low dielectric constant electronic substrate materials, electron emitters (particularly for displays), piezoelectric sensors and actuators, electrostrictive actuators, piezochromic rubbers, gas storage materials, chromatographic separation materials, catalyst support materials, photonic bandgap materials for optical circuitry, and opalescent colorants for the ultraviolet, visible, and infrared regions.

A method for producing a nitride semiconductor, comprising controlling temperature and pressure in a autoclave containing a seed having a hexagonal crystal structure, a nitrogen element-containing solvent, a raw material substance containing a metal element of Group 13 of the Periodic Table, and a mineralizer so as to put said solvent into a supercritical state and/or a subcritical state and thereby ammonothermally grow a nitride semiconductor crystal on the surface of said seed, wherein the crystal growth rate in the m-axis direction on said seed is 1.5 times or more the crystal growth rate in the c-axis direction on said seed. By the method, a nitride semiconductor having a large-diameter C plane or a nitride semiconductor thick in the m-axis direction can be efficiently and simply produced.

A multi-junction solar cell includes a silicon solar subcell, a GaInP solar subcell, and a GaAs solar subcell located between the silicon solar subcell and the GaInP solar subcell. The GaAs solar subcell is bonded to the silicon solar subcell such that a bonded interface exists between these subcells.

A method of fabricating an elastomeric structure, comprising: forming a first elastomeric layer on top of a first micromachined mold, the first micromachined mold having a first raised protrusion which forms a first recess extending along a bottom surface of the first elastomeric layer; forming a second elastomeric layer on top of a second micromachined mold, the second micromachined mold having a second raised protrusion which forms a second recess extending along a bottom surface of the second elastomeric layer; bonding the bottom surface of the second elastomeric layer onto a top surface of the first elastomeric layer such that a control channel forms in the second recess between the first and second elastomeric layers; and positioning the first elastomeric layer on top of a planar substrate such that a flow channel forms in the first recess between the first elastomeric layer and the planar substrate.

A freestanding GaN single crystal substrate is made by the steps of preparing a (111) GaAs single crystal substrate, forming a mask having periodically arranged windows on the (111) GaAs substrate, making thin GaN buffer layers on the GaAs substrate in the windows of the mask, growing a GaN epitaxial layer on the buffer layers and the mask by an HVPE or an MOC, eliminating the GaAs substrate and the mask away and obtaining a freestanding GaN single crystal substrate. The GaN single crystal has a diameter larger than 20 mm and a thickness more than 0.07 mm, being freestanding and substantially distortion-free.

A method is for making at least one semiconductor device including providing a sacrificial growth substrate of Lithium Aluminate (LiAlO₂); forming at least one semiconductor layer including a Group III nitride adjacent the sacrificial growth substrate; attaching a mounting substrate adjacent the at least one semiconductor layer opposite the sacrificial growth substrate; and removing the sacrificial growth substrate. The method may further include adding at least one contact onto a surface of the at least one semiconductor layer opposite the mounting substrate, and dividing the mounting substrate and at least one semiconductor layer into a plurality of individual semiconductor devices. To make the final devices, the method may further include bonding the mounting substrate of each individual semiconductor device to a heat sink. The step of removing the sacrificial substrate may include wet etching the sacrificial growth substrate.

A method for large-scale manufacturing of gallium nitride boules. Large-area single crystal seed plates are suspended in a rack, placed in a large diameter autoclave or internally-heated high pressure apparatus along with ammonia and a mineralizer, and grown ammonothermally. The seed orientation and mounting geometry are chosen to provide efficient utilization of the seed plates and of the volume inside the autoclave or high pressure apparatus. The method is scalable up to very large volumes and is cost effective.

Methods for forming compositions comprising a single-phase rare-earth dielectric disposed on a substrate are disclosed. In some embodiments, the method forms a semiconductor-on-insulator structure. Compositions and structures that are formed via the method provide the basis for forming high-performance devices and circuits.

There is disclosed a silicon focus ring consisting of silicon single crystal used as a silicon focus ring in a plasma apparatus, wherein concentration of interstitial oxygen contained in the silicon focus ring is not less than 5x10<17 >atoms/cm<3 >and not more than 1.5x10<18 >atoms/cm<3>, and a producing method for a silicon focus ring used for a plasma apparatus, wherein a single crystal silicon wherein concentration of interstitial oxygen contained in the silicon focus ring is not less than 5x10<17 >atoms/cm<3 >and not more than 1.5x10<18 >atoms/cm<3 >is grown by a Czochralski method, the single crystal silicon is processed in a circle, and a silicon focus ring is produced. There can be provided a silicon focus ring, which can prevent disadvantage due to impurities such as heavy metal.

The present invention provides microfluidic technology enabling rapid and economical manipulation of reactions on the femtoliter to microliter scale.

The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves only a sub-monolayer of oxygen (typically 1×10¹³-1×10¹⁵/cm² of oxygen) at the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process in a chlorine containing environment which heats the silicon germanium, strained silicon, or thin silicon-on-insulator surface sufficiently to remove the remaining oxygen from the surface. By introducing a small amount of chlorine containing gases, the heating processes avoid changing the roughness of the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. Then the process of epitaxially growing the epitaxial silicon-containing layer on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface is performed.

A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 μm/cm², wherein nTTV is total thickness variation normalized for surface area of the generally planar surface, the substrate having a diameter not less than about 9.0 cm.

A substrate including a host and a seed layer bonded to the host is provided, then a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region is grown on the seed layer. In some embodiments, a bonding layer bonds the host to the seed layer. The seed layer may be thinner than a critical thickness for relaxation of strain in the semiconductor structure, such that strain in the semiconductor structure is relieved by dislocations formed in the seed layer, or by gliding between the seed layer and the bonding layer an interface between the two layers. In some embodiments, the host may be separated from the semiconductor structure and seed layer by etching away the bonding layer.

Disclosed is a natural-superlattice homologous single-crystal thin film, which comprises a complex oxide which is epitaxially grown on either one of a ZnO epitaxial thin film formed on a single-crystal substrate, the single-crystal substrate after disappearance of the ZnO epitaxial thin film and a ZnO single crystal. The complex oxide is expressed by the a formula: M¹M²O₃ (ZnO)_m, wherein M¹ is at least one selected from the group consisting of Ga, Fe, Sc, In, Lu, Yb, Tm, Er, Ho and Y, M² is at least one selected from the group consisting of Mn, Fe, Ga, In and Al, and m is a natural number of 1 or more. A natural-superlattice homologous single-crystal thin film formed by depositing the complex oxide and subjecting the obtained layered film to a thermal anneal treatment can be used in optimal devices, electronic devices and X-ray optical devices.