Heterojunction field effect transistor for groove insulated gate type multiple source field plate

A heterojunction field effect, insulated gate type technology, applied in the field of microelectronics, can solve the problems of reducing the yield of the device, complicated manufacturing process, tedious process debugging, etc., to reduce leakage current, reduce electric field lines, and reduce electric field. Effect

Inactive Publication Date: 2009-04-22
XIDIAN UNIV
View PDF0 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the manufacturing process of the heterojunction field effect transistor using the stacked field plate structure is relatively complicated. Each additional layer of field plate requires additional process steps such as photolithography, metal deposition, insulating dielectric material deposition, stripping, and cleaning. To make the insulating dielectric material deposited under the field plates of each layer have an appropriate thickness, cumbersome process debugging must be carried out, which greatly increases the difficulty of device manufacturing and reduces the yield of devices.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Heterojunction field effect transistor for groove insulated gate type multiple source field plate
  • Heterojunction field effect transistor for groove insulated gate type multiple source field plate
  • Heterojunction field effect transistor for groove insulated gate type multiple source field plate

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0060] The production substrate is sapphire, and the insulating dielectric layer is SiO 2 , the passivation layer is SiN, the protective layer is SiN, the source field plate and each floating field plate is a heterojunction field effect transistor with a composite source field plate composed of Ti / Au metal, and the process is:

[0061] 1. Using metal organic chemical vapor deposition technology to epitaxially undoped transition layer 2 with a thickness of 1 μm on the sapphire substrate 1, the transition layer is composed of AlN material with a thickness of 26 nm and GaN material with a thickness of 0.974 μm from bottom to top constitute. The process conditions used for the epitaxial lower layer AlN material are: temperature 575°C, pressure 82 Torr, hydrogen gas flow rate 4400 sccm, ammonia gas flow rate 4400 sccm, aluminum source flow rate 26 μmol / min; the process conditions for the epitaxial upper layer GaN material are: temperature 1000°C, the pressure is 82 Torr, the flow ...

Embodiment 2

[0071] The production substrate is silicon carbide, the insulating dielectric layer is SiN, and the passivation layer is SiO 2 , the protective layer is SiO 2 , the source field plate and each floating field plate is a heterojunction field effect transistor with a composite source field plate of Ni / Au metal combination, and the process is:

[0072] 1. An undoped transition layer 2 with a thickness of 2.6 μm is epitaxially formed on a silicon carbide substrate 1 by metal-organic chemical vapor deposition technology. Made of GaN material. The process conditions used for the epitaxial lower layer AlN material are: temperature 1040°C, pressure 85 Torr, hydrogen gas flow rate 5000 sccm, ammonia gas flow rate 5000 sccm, aluminum source flow rate 16 μmol / min; the process conditions for the epitaxial upper layer GaN material are: temperature 1040°C, the pressure is 85 Torr, the flow rate of hydrogen gas is 5000 sccm, the flow rate of ammonia gas is 5000 sccm, and the flow rate of ga...

Embodiment 3

[0082] The production substrate is silicon, and the insulating dielectric layer is Al 2 o 3 , the passivation layer is SiN, the protective layer is SiN, the source field plate and each floating field plate is a heterojunction field effect transistor with a composite source field plate composed of Pt / Au metal, and the process is:

[0083] 1. Using metal organic chemical vapor deposition technology to epitaxially undoped transition layer 2 with a thickness of 5 μm on the silicon substrate 1, the transition layer is composed of AlN material with a thickness of 135 nm and GaN material with a thickness of 4.865 μm from bottom to top constitute. The process conditions used for the epitaxial lower layer AlN material are: temperature 880°C, pressure 90 Torr, hydrogen gas flow rate 5100 sccm, ammonia gas flow rate 5100 sccm, aluminum source flow rate 41 μmol / min; the process conditions for the epitaxial upper layer GaN material are: temperature 1070°C, pressure 90 Torr, hydrogen gas ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a heterojunction field effect transistor of a groove-insulated gate type composite source field plate. The transistor comprises a substrate, a transition layer, a barrier layer, a source electrode, a drain electrode, an insulation medium layer, an insulated groove gate, a passivation layer, a source field plate and a protection layer from bottom to top; a groove is opened on the barrier layer, the insulated groove gate is arranged on the insulation medium layer at the upper part of the groove, the source field plate is arranged on the passivation layer, and the source electrode is electrically connected with the source field plate, wherein, n floating field plates are deposited on the passivation layer arranged between the source field plate and the drain field plate. The floating field plates have the same size and are mutually independent, and the spacing between two adjacent floating field plates increases based on the number of the floating field plates arranged along the direction from the source field plate to the drain electrode. The n floating field plates are in floating state and completed together with the source field plate on the passivation layer by one-time process. The heterojunction field effect transistor has the advantages of simple process, good reliability, strong stability, good frequency characteristic and high output power, and can be used for fabricating microwave power devices based on III-V group compound semiconductor heterojunction structure.

Description

technical field [0001] The invention belongs to the field of microelectronics technology, and relates to semiconductor devices, in particular to a heterojunction field effect transistor based on a grooved insulating gate type composite source field plate based on a III-V compound semiconductor material heterojunction, which can be used as a microwave and millimeter wave communication device. system and the basic components of the radar system. technical background [0002] As is well known in the industry, semiconductor materials composed of group III elements and group V elements, that is, group III-V compound semiconductor materials, such as gallium nitride (GaN)-based, gallium arsenide (GaAs)-based, indium phosphide (InP)-based And other semiconductor materials, their bandgap widths are often quite different, so people usually use these III-V compound semiconductor materials to form various heterojunction structures. Due to the large difference in the band gap of III-V c...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
Inventor 毛维杨翠郝跃过润秋
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products