37 results about "Channel density" patented technology

The invention relates to the technical field of bushing detection, and discloses a bushing insulation state detection method based on multi-parameter real-time monitoring. The method comprises the following steps: acquiring multi-dimensional monitoring data such as a partial discharge pulse sequence, dielectric loss angle tangent value fluctuation data and surface leakage current density distribution in a bushing operation environment in real time; carrying out insulation defect feature extraction on the data set, and generating an insulation defect distribution map containing a creeping discharge track, an internal air gap position mark and a carbonization channel density index; high-risk and potential defect areas are divided by adopting a dynamic threshold segmentation algorithm, boundary coordinates are determined, and an insulation state evaluation vector containing parameters such as a surface discharge intensity index and the like is constructed according to the boundary coordinates; and inputting the vector into a pre-trained insulation aging prediction model, and outputting a bushing residual insulation life estimated value and a defect development priority sequence. According to the method, all-around accurate monitoring and pre-judgment of the insulation state of the sleeve are achieved, and scientific support is provided for operation and maintenance decision making of the sleeve.

The invention discloses an insulated gate bipolar transistor device and a preparation process thereof, and the device comprises a substrate, a drain electrode which is formed below the substrate, a dielectric layer which is formed above the substrate, a source electrode which is formed above the dielectric layer, and a plurality of grooves which are formed in the substrate in a downward etching and sinking manner and are independently arranged, independent trench gates are deposited in the trenches, the cross section of the plurality of trenches is of a circular or annular or polygonal closed structure, and the trench gates are insulated and isolated from the side walls of the trenches and the source electrodes through dielectric layers. The novel groove type IGBT structure is achieved through the groove gates arranged in a circular layout mode, the structure has the advantages of being high in channel density, large in current density, simple in process and the like, and the chip area and the cost can be reduced while the current capacity is kept; or the current density and the power density of the device are improved while the chip area is maintained, and the on-state loss is reduced.

The present invention discloses a three-dimensional strip-shaped cell structure, comprising: a first-conductivity-type epitaxial region, a second-conductivity-type well region located within the first-conductivity-type epitaxial region, a meandering first-conductivity-type source region located within the second-conductivity-type well region, and a second-conductivity-type body region located within the meandering first-conductivity-type source region. In the horizontal direction, the first-conductivity-type epitaxial region, the second-conductivity-type well region, the meandering first-conductivity-type source region, and the second-conductivity-type body region are each provided with a plurality of protrusions or grooves of the same height and width, thereby forming a plurality of straight-line mesa structures or a plurality of straight-line groove structures on the strip-shaped cell structure. This structure enables the device to have not only parallel channels parallel to the cell surface but also vertical channels perpendicular to the cell surface, thereby increasing the channel density, reducing the on-resistance of the channel, and thereby improving the current flow capacity of the device.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The application relates to a power device and a preparation method thereof and electronic equipment. The device comprises a substrate, a first surface of the substrate comprising an epitaxial layer; the epitaxial layer comprising source regions, base regions and shielding regions arranged along a first direction towards the substrate via a top surface; a plurality of gates spaced along a second direction parallel to the first surface and penetrating the source regions and the base regions along the first direction and partially embedded in the shielding regions; the gate comprising a gate conductive layer and a gate oxide layer arranged along the first direction; an interlayer dielectric layer located on the top surface of the epitaxial layer and comprising an extension penetrating the gate conductive layer along the first direction and in contact with the gate oxide layer; and a metal layer located on the top surface of the interlayer dielectric layer and comprising a first source electrode extending into the gate via the top surface of the extension; the width and depth of the first source electrode being related to the gate-source capacitance of the power device. The channel density can be ensured while improving the reliability of the gate oxide layer.

The embodiment of the invention discloses a micro-fluidic chip and application thereof in nucleic acid detection.The micro-fluidic chip comprises a chip part, the chip part comprises a substrate, and the substrate comprises a top layer, a middle layer and a bottom layer; the substrate is provided with a microfluidic channel; three-dimensional patterns are arranged on the upper surface and the lower surface of the middle layer, and the pattern on the upper surface of the middle layer and the top layer define an upper-layer microfluidic channel in the microfluidic channel; the pattern on the lower surface of the middle layer and the bottom layer define a lower-layer microfluidic channel in the microfluidic channel; the extending directions of the upper-layer microfluidic channel and the lower-layer microfluidic channel are parallel to the plane of the substrate; the middle layer comprises a through hole used for forming a vertical microfluidic channel, the extension direction of the vertical microfluidic channel is perpendicular to the plane where the substrate is located, and at least part of the vertical microfluidic channel is used for communicating the upper-layer microfluidic channel with the lower-layer microfluidic channel. According to the embodiment of the invention, an overpass type microfluidic channel can be formed, the channel density can be improved, and a flexible communication relation can be constructed to meet complex reaction requirements.

This application discloses a MOSFET and its fabrication method, relating to the field of semiconductor technology. The MOSFET includes a substrate and an epitaxial layer and a current spreading layer sequentially disposed on the substrate. A P-type well region is formed on the current spreading layer, extending along a first direction. An N-type doped region and a source contact are formed within the P-type well region. The N-type doped region surrounds the outer periphery of the source contact, and the sidewall of the source contact contacts the sidewall of the N-type doped region. This MOSFET and its fabrication method can reduce the cell size and increase the channel density without changing the process boundaries.

The invention relates to the technical field of semiconductor power devices, in particular to a discrete device and a manufacturing method thereof, and the method comprises the steps: providing an N + substrate and growing an N epitaxial layer; depositing and patterning a masking layer to etch to form a deep groove; growing a thin oxide layer and depositing a thick oxide layer; depositing and etching polycrystalline silicon to form a shield gate; removing part of the oxide layer, depositing a new oxide layer, and grinding; depositing an oxide layer as a masking layer, and forming a multidirectional shallow slot pattern through photoetching and etching; adjusting the thickness of the oxide layer through wet etching, growing gate oxide and forming gate polycrystalline silicon; completing the steps of P well and N + source region injection, dielectric layer deposition, contact hole etching and metallization to form a device; the layout design of multidirectional cellular layout is introduced, the process limitation of traditional one-way pitch miniaturization is broken through, on the premise of not depending on a higher-level manufacturing process, the channel density of a unit area is remarkably improved, the on-resistance of the device is effectively reduced, and good process compatibility and reliability are achieved.

The utility model provides an injection structure and a silicon carbide gate-controlled device structure. The injection structure comprises cells arranged in an array and at least one P-doped region. Each cell comprises a pbase doped region, an N + doped region and a P + doped region; a groove is formed in one end face of the pbase doped region, the P + doped region is located at the center of the groove and is in contact connection with a source electrode, and the N + doped region is located between the side face of the P + doped region and the side wall of the groove; the gate dielectric region is provided with a first gap which corresponds to the cell and is plugged by the source contact, and the gate contact is provided with a second gap corresponding to the P doped region and a third gap corresponding to the first gap; the pbase doped region is connected with the gate dielectric region; and one end surface of the P-doped region is connected with the gate dielectric region. The injection structure and the silicon carbide gate-controlled device structure provided by the utility model can improve the channel density, reduce the gate-oxide electric field intensity, block the leakage current of the silicon carbide device, reduce the reverse transmission capacitance, and reduce the switching loss of the device.

The invention relates to a power device and a preparation method thereof, and electronic equipment, and the device comprises the components of a substrate which comprises an epitaxial layer on a first surface; the epitaxial layer internally comprises a source region, a base region and a shielding region which are arranged along a first direction towards the substrate through the top surface; the grid electrodes are distributed at intervals along a second direction parallel to the first surface, penetrate through the source region and the base region along the first direction, and are partially embedded into the shielding region; the gate electrode comprises a gate conductive layer and a gate oxide layer which are arranged along a first direction; the interlayer dielectric layer is located on the top surface of the epitaxial layer and comprises an extension part which penetrates through the gate conductive layer in the first direction and is in contact with the gate oxide layer; the metal layer is positioned on the top surface of the interlayer dielectric layer and comprises a first source electrode which extends into the grid electrode through the top surface of the extension part; the width and depth of the first source are associated with the gate-source capacitance of the power device. The reliability of the gate oxide layer can be improved while the channel density is ensured.

According to the trench gate MOSFET structure provided by the invention, the first shielding region and the second shielding region can reduce the maximum electric field in the gate oxide at the bottom of the gate trench structure and improve the reliability of a device, meanwhile, at least one side wall of the first gate trench structure is provided with a channel for conducting current, at least one side wall of the second gate trench structure is provided with a channel for conducting current, and the reliability of the device is improved. The channel density of the device is increased, so that the conduction capability of the device is improved, and the conduction resistance of the device is reduced; besides, a third gate trench structure is arranged between the first gate trench structure and the second gate trench structure, and channels are formed in two side walls of the third gate trench structure and can conduct current, so that the channel density of the device is further increased, and the conduction capability of the device is improved.

The application discloses a MOSFET device and a preparation method thereof, and relates to the technical field of SiC power device design and manufacturing. The MOSFET device comprises a plurality of strip cells, and the strip cells are sequentially stacked from bottom to top with a metal drain, a SiC substrate of a first doping type, a SiC buffer layer of the first doping type and a SiC epitaxial layer of the first doping type, and a plurality of stepped grooves of a symmetrical structure are formed in the SiC epitaxial layer. The MOSFET device utilizes a longitudinal space region to form a multi-directional current channel, under the premise of ensuring the reliability of a gate oxide and the reverse breakdown performance, the multi-directional current channel can effectively improve the channel density and the current density per unit area, the SiC epitaxial layer surface and the metal source electrode above the ohmic contact area of the source groove guarantee the concentrated export of the source current, and the whole realizes the synergistic optimization of low specific on-resistance, high gate oxide reliability and high integration, and the device manufacturing cost is reduced.

The application discloses a high short-circuit resistance current carrier storage trench gate IGBT device, which is configured to comprise a plurality of interval trenches (1), and a P+ area (2) for improving short-circuit resistance of the IGBT is formed between adjacent trenches (1). The IGBT device provided by the application forms the P+ area periodically between the trenches, so that the trench sidewall of the P+ area cannot form a conductive channel, thereby reducing the overall channel density, reducing the saturation current of the device, and greatly improving the short-circuit resistance of the device.

The present invention discloses a silicon carbide trench gate MOSFET device and a method for preparing the same. The device is composed of two alternating cell structures, wherein structure one is a conventional silicon carbide trench gate MOSFET structure with a P-type shielding layer below the gate, while structure two utilizes selective tilted ion implantation to form a P-type connection region below the gate trench side that connects the P-type base region on the side of the gate and the P-type shielding layer below the gate, thereby achieving effective grounding of the P-type shielding layer and improving the shielding effect of the P-type shielding layer. Furthermore, an additional N-type connection region for connecting the channel is added inside the P-type connection region, so that electrons in the source region can flow to the JFET region through the N-type connection region along the alternating arrangement direction of the two structures after passing through the base region channel, thereby increasing the effective channel density and reducing the on-resistance of the device.

The invention provides a trench gate MOS device and a preparation method thereof, the trench gate MOS device comprises a semiconductor structure, a shielding layer, a body region, a source region, a contact region, a trench structure, an injection region and a source / drain / gate, the semiconductor structure comprises a substrate, a drift region and a current transmission layer; the shielding layers arranged at intervals are located in the current transmission layer; the body region is positioned on the upper surface layers of the shielding layer and the current transmission layer; two ends of the source region are respectively positioned on the shielding layer and the current transmission layer; the contact regions are located between the adjacent source regions; the trench structure comprises a trench, a gate dielectric layer and a gate conductive layer, wherein the trench penetrates through the source region and the body region, and two side walls of the trench are positioned in the current transmission layer and the shielding layer; the upper surface of the injection region is flush with the bottom surface of the body region; and the source / drain / grid electrode is electrically connected with the corresponding region respectively. Through the combination of the shielding layer and the injection region, the channel density of the device is improved, the on-resistance of the device is reduced, and the ratio of Cgd / Cgs is reduced at the same time.

The invention provides a trench gate device and a preparation method thereof, the trench gate device comprises a semiconductor layer, a trench gate structure, a first shielding layer, a second shielding layer, a source electrode, a gate electrode and a drain electrode, the semiconductor layer comprises a drift region, a body region located on the upper surface layer of the drift region and a plurality of source regions arranged at intervals and located on the upper surface layer of the body region; the trench gate structure penetrates through the source region and the body region, and the bottom of the trench gate structure extends into the drift region; the first shielding layer is located in the drift region under the trench gate structure and is adjacent to the bottom of the trench gate structure; the second shielding layer is located in the semiconductor layer on the same side of each trench gate structure, the top of the second shielding layer is adjacent to the source region, and the bottom of the second shielding layer is adjacent to the first shielding layer; the source electrode, the grid electrode and the drain electrode are electrically connected with the corresponding areas respectively. The first shielding layer is arranged at the bottom of the groove, and the second shielding layer is arranged in the semiconductor layer on the same side of each groove, so that the channel density and reliability of the device are improved, and the on resistance of the device is reduced.

The present invention discloses a three-dimensional square cell structure, comprising: a first-conductivity-type epitaxial region, a second-conductivity-type well region located within the first-conductivity-type epitaxial region, a meandering first-conductivity-type source region located within the second-conductivity-type well region, and a second-conductivity-type body region located within the meandering first-conductivity-type source region; wherein the second-conductivity-type body region is convex; along the horizontal and vertical directions, the first-conductivity-type epitaxial region, the second-conductivity-type well region, and the meandering first-conductivity-type source region are each provided with a plurality of protrusions of the same width and height, thereby forming a plurality of protruding mesas in the horizontal and vertical directions, respectively, and simultaneously forming a cross-shaped mesa structure intersecting with the second-conductivity-type body region on the square cell structure. This structure enables the device to have both parallel and perpendicular channels to the cell surface, thereby increasing the channel density, reducing the on-resistance of the channel, and improving the current flow capacity of the device.

In a trench MOSFET with a longitudinal channel fin structure, even when the trench spacing is reduced to increase the channel density, the decrease and deviation of the threshold voltage are suppressed. The semiconductor device (1) has: a plurality of trenches (2) which have a length direction in a first direction and a short side direction in a second direction when viewed from above, and are arranged in a plurality of trenches in the second direction; a source region (3) of a first conductivity type, which includes a fin structure divided by the plurality of trenches (2); a channel region (5) of a second conductivity type of fin structure, which is divided by the plurality of trenches (2); and a body region (9) of a second conductivity type, the channel region (5) being connected to the body region (9), and a channel current flowing longitudinally in the channel region (5), the channel region (5) having a first channel region (5A) connected to the lower surface of the source region (3) and a second channel region (5B) disposed below the first channel region (5A), the impurity concentration of the second conductivity type in the first channel region (5A) being higher than that in the second channel region (5B).

The application belongs to the technical field of power devices, and provides a trench gate silicon carbide power device and a preparation method and a chip thereof. A cross-shaped trench gate is arranged, a double-layer structure of a P-type deep well and a P-type heavily doped region is arranged at a cross intersection area of the trench gate, N-type heavily doped regions are arranged on both sides of a first direction trench gate, and the first direction trench gate and the P-type heavily doped region are arranged periodically and alternately. In this way, the current density of the device is greatly improved through a higher channel density. The novel structure can further arrange a deep well as a shielding area at a trench corner, so as to migrate an electric field peak from the trench corner to the bottom of the deep well, so that the depletion region of the device can be closed, the IDSS of the device is reduced, the BVDSS of the device is improved, the reliability of the device is effectively improved, the gate-source coupling is increased by the deep well region, zero-voltage turn-off is beneficial to be realized, and the complexity of a driving system is reduced.

This invention discloses a trench-gate dual-controller 4H-SiC composite transistor structure and its fabrication method. The structure consists of an active region formed by parallel multi-cell structures and a trench-junction termination extension composite terminal region. The n+ source region and p+ region are separated and introduced into dual controllers to control the turn-on and turn-off of the parallel VUMOS and BJT respectively, thereby reducing the on-resistance and loss of the DCT, while reducing the channel density to increase the short-circuit withstand time, improve the short-circuit resistance, and eliminate the influence of the body diode on the device characteristics. A p-floating region with a side arc shape is formed at the bottom of the trench in the active region, and its edge wraps around the trench corner to reduce the electric field intensity in the gate oxide layer at that location, solving the problem of easy breakdown of the gate oxide layer. The trench-junction termination extension composite terminal is used to reduce the terminal size and obtain high breakdown voltage efficiency, which can meet the requirements of power MOSFET characteristics and reliability in practical applications and has low cost.

The invention discloses a multi-channel multi-mode active electrode integrated nerve probe chip for an implantable brain-computer interface, which comprises a non-implantable circuit part and an implantable electrode part, wherein the non-implanted circuit part integrates a multi-channel electroneurographic signal detection front end, a chemical signal detection front end, a multi-bit adjustable stimulation circuit, a reconfigurable switch array and digital control logic; the implantable electrode part is of a silicon needle structure, electrical electrodes and chemical electrodes are longitudinally distributed on the surface of the implantable electrode part, and dynamic gating and closed-loop regulation and control are supported. Through the electrode-circuit integrated design, the multi-mode function of synchronous high-precision detection and electrical stimulation output of the electroneurographic signals and the chemical signals is achieved, the problems that in the prior art, the mode is single, and the integration degree is low are solved, and the device has the advantages of being high in channel density and low in noise; 5 [mu] Vrms) and a fast closed-loop response (lt; the method is suitable for acute and long-term brain science research and nerve disease treatment.

The application discloses a three-dimensional hexagonal cell structure, which comprises a first conductive type epitaxial region, a second conductive type well region in the first conductive type epitaxial region, a first conductive type source region in the second conductive type well region and a second conductive type body region in the first conductive type source region; wherein the second conductive type body region is in a convex shape; and a plurality of convexes with the same width and height are arranged on the first conductive type epitaxial region, the second conductive type well region and the first conductive type source region in the vertical direction of the six sides of the hexagonal cell structure, so as to form a plurality of convex mesa surfaces in each direction and a hexagonal mesa structure intersecting the second conductive type body region on the hexagonal cell structure. The structure makes the device have two channels parallel to the cell surface and perpendicular to the cell surface, thereby improving the channel density, reducing the on-resistance of the channel and improving the current-carrying capacity of the device.

The invention belongs to the technical field of power devices, and provides a trench gate silicon carbide power device, a preparation method thereof and a chip, a cross-shaped trench gate is arranged, a double-layer structure of a P-type deep well and a P-type heavily doped region is arranged in a cross region of the trench gate, and N-type heavily doped regions are arranged on two sides of the trench gate in the first direction, so that the trench gate silicon carbide power device is formed. The first-direction trench gates and the P-type heavily doped regions are periodically and alternately arranged, so that the current density of the device is greatly improved through relatively high channel density, a deep trap can be arranged at a trench corner of the novel structure to serve as a shielding region, and an electric field peak value is migrated to the bottom of the deep trap from the trench corner, so that a depletion region of the device can be closed; iDSS of the device is reduced, BVDSS of the device is improved, reliability of the device is effectively improved, meanwhile, gate-source coupling is added in the deep well region, zero-voltage turn-off is achieved, and complexity of a driving system is reduced.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The invention discloses a semiconductor device and a preparation method, and belongs to the technical field of semiconductors. Comprising a substrate, an N-type drift layer, an N-type source region, a current expansion layer, a P-type shielding layer, a P-type base region, a heavily doped P-type region, a source electrode, a grid electrode, a drain electrode, a grid electrode oxide layer and a source electrode, schottky diodes or channel diodes are integrated on the two sides of the source electrode of the double-groove MOSFET. On the premise that the primitive cell area is not increased and the channel density is not sacrificed, the reverse recovery capability can be obviously improved only by optimizing the existing structure. The core mechanism is that an internally integrated Schottky diode (or channel diode) can bypass a parasitic diode during follow current of an inductive load, so that the reverse recovery capability is directly improved.

This application discloses a MOSFET and its fabrication method, relating to the field of semiconductor technology. The MOSFET includes a substrate and an epitaxial layer and a current spreading layer sequentially disposed on the substrate. A P-type well region is formed on the current spreading layer, extending along a first direction. An N+ doped region and a P+ doped region are formed within the P-type well region, wherein the N+ doped region surrounds the outer periphery of the P+ doped region. A conductive channel is formed between the P-type well region and the epitaxial layer. A source contact is disposed on the P+ doped region. This MOSFET and its fabrication method can reduce cell size and increase channel density without changing the process boundaries.

The present invention provides a multi-step multi-channel trench MOSFET device and a preparation method thereof, wherein the design of the n-step trench can increase the channel path of the unit trench cell and improve the channel density on the basis of ensuring gate oxide reliability and reverse breakdown; adjacent P+ injections are not at the same horizontal position, that is, the first doping region, the second doping region and the third doping region are not at the same horizontal position, which effectively reduces the JFET effect of adjacent P+ regions, reduces the JFET resistance, effectively reduces the specific on-resistance of the MOSFET transistor and improves the current density per unit area; the low JFET effect reduces the on-resistance change under small current and large current; on the other hand, a Schottky diode is connected in anti-parallel near the source electrode, which can significantly reduce the diode voltage drop of the MOSFET transistor without affecting the cell size, improve the integration of the chip, and reduce the production cost of the MOSFET device with integrated Schottky diode.

The invention discloses an ultrahigh-resolution integrated calculation spectrometer based on a single waveguide and an implementation method, and belongs to the field of spectral measurement. The spectrometer comprises a cladding, an input end face coupler, a multi-stage reflection measurement waveguide, a phase modulator, an output end face coupler, a photoelectric detector and a microcontroller. The multi-stage reflection measurement waveguide comprises multiple stages of microstructure reflection units which are sequentially connected through waveguides in the propagation direction. The invention solves the problems of low resolution and insufficient bandwidth and expandability, has high resolution and large bandwidth performance, and realizes 0.9 pm-level double-peak distinguishable and 800nm effective bandwidth in the near-infrared band; due to the simple structure of the single straight waveguide, high independent channel density can be obtained without a long-chain cascade device; the waveguide loss can be maintained within 5 dB by limiting the reflectivity and the segment number of the micro-structure reflection units, and a good detection effect can also be achieved for low-intensity light to be detected; the method is applied to high-precision measurement of various complex spectrums.

The invention relates to a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductor manufacturing, in the semiconductor device, the top surface of a first conductive type first source region is flush with the top surface of a substrate, and the outer surface is located in the substrate; the second conductive type first well ring covers the outer surface of the first source region and is embedded into the substrate through the top surface of the substrate; the second conductive type semiconductor column penetrates through the first source region and the first well ring along the direction towards the substrate through the top surface of the substrate; the first gate structure and the second gate structure are arranged at intervals, cover the top surface of the first well ring, and the top surface of the first source region, the first gate structure, the semiconductor column and the second gate structure are sequentially distributed along a first direction parallel to the top surface of the substrate. At least the MOS channel density can be improved, the impedance and power loss during forward conduction of the MOS device can be reduced, and the anti-surge capability can be improved.

The present disclosure relates to a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductor manufacturing. In the semiconductor device, a top surface of a first source region of a first conductive type is flush with a top surface of a substrate and an outer surface is located in the substrate; a first well ring of a second conductive type covers the outer surface of the first source region and is embedded in the substrate via the top surface of the substrate; a semiconductor column of the second conductive type penetrates the first source region and the first well ring in a direction towards the substrate via the top surface of the substrate; and spaced first gate structures and second gate structures cover top surfaces of the first well ring and the first source region, and the first gate structures, the semiconductor column and the second gate structures are sequentially distributed in a first direction parallel to the top surface of the substrate. At least the MOS channel density can be improved, the impedance and power loss during forward conduction of the MOS device can be reduced, and the surge resistance can be improved.