22 results about "Channel density" patented technology

The invention relates to the technical field of bushing detection, and discloses a bushing insulation state detection method based on multi-parameter real-time monitoring. The method comprises the following steps: acquiring multi-dimensional monitoring data such as a partial discharge pulse sequence, dielectric loss angle tangent value fluctuation data and surface leakage current density distribution in a bushing operation environment in real time; carrying out insulation defect feature extraction on the data set, and generating an insulation defect distribution map containing a creeping discharge track, an internal air gap position mark and a carbonization channel density index; high-risk and potential defect areas are divided by adopting a dynamic threshold segmentation algorithm, boundary coordinates are determined, and an insulation state evaluation vector containing parameters such as a surface discharge intensity index and the like is constructed according to the boundary coordinates; and inputting the vector into a pre-trained insulation aging prediction model, and outputting a bushing residual insulation life estimated value and a defect development priority sequence. According to the method, all-around accurate monitoring and pre-judgment of the insulation state of the sleeve are achieved, and scientific support is provided for operation and maintenance decision making of the sleeve.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The application relates to a power device and a preparation method thereof and electronic equipment. The device comprises a substrate, a first surface of the substrate comprising an epitaxial layer; the epitaxial layer comprising source regions, base regions and shielding regions arranged along a first direction towards the substrate via a top surface; a plurality of gates spaced along a second direction parallel to the first surface and penetrating the source regions and the base regions along the first direction and partially embedded in the shielding regions; the gate comprising a gate conductive layer and a gate oxide layer arranged along the first direction; an interlayer dielectric layer located on the top surface of the epitaxial layer and comprising an extension penetrating the gate conductive layer along the first direction and in contact with the gate oxide layer; and a metal layer located on the top surface of the interlayer dielectric layer and comprising a first source electrode extending into the gate via the top surface of the extension; the width and depth of the first source electrode being related to the gate-source capacitance of the power device. The channel density can be ensured while improving the reliability of the gate oxide layer.

The embodiment of the invention discloses a micro-fluidic chip and application thereof in nucleic acid detection.The micro-fluidic chip comprises a chip part, the chip part comprises a substrate, and the substrate comprises a top layer, a middle layer and a bottom layer; the substrate is provided with a microfluidic channel; three-dimensional patterns are arranged on the upper surface and the lower surface of the middle layer, and the pattern on the upper surface of the middle layer and the top layer define an upper-layer microfluidic channel in the microfluidic channel; the pattern on the lower surface of the middle layer and the bottom layer define a lower-layer microfluidic channel in the microfluidic channel; the extending directions of the upper-layer microfluidic channel and the lower-layer microfluidic channel are parallel to the plane of the substrate; the middle layer comprises a through hole used for forming a vertical microfluidic channel, the extension direction of the vertical microfluidic channel is perpendicular to the plane where the substrate is located, and at least part of the vertical microfluidic channel is used for communicating the upper-layer microfluidic channel with the lower-layer microfluidic channel. According to the embodiment of the invention, an overpass type microfluidic channel can be formed, the channel density can be improved, and a flexible communication relation can be constructed to meet complex reaction requirements.

This application discloses a MOSFET and its fabrication method, relating to the field of semiconductor technology. The MOSFET includes a substrate and an epitaxial layer and a current spreading layer sequentially disposed on the substrate. A P-type well region is formed on the current spreading layer, extending along a first direction. An N-type doped region and a source contact are formed within the P-type well region. The N-type doped region surrounds the outer periphery of the source contact, and the sidewall of the source contact contacts the sidewall of the N-type doped region. This MOSFET and its fabrication method can reduce the cell size and increase the channel density without changing the process boundaries.

The invention relates to the technical field of semiconductor power devices, in particular to a discrete device and a manufacturing method thereof, and the method comprises the steps: providing an N + substrate and growing an N epitaxial layer; depositing and patterning a masking layer to etch to form a deep groove; growing a thin oxide layer and depositing a thick oxide layer; depositing and etching polycrystalline silicon to form a shield gate; removing part of the oxide layer, depositing a new oxide layer, and grinding; depositing an oxide layer as a masking layer, and forming a multidirectional shallow slot pattern through photoetching and etching; adjusting the thickness of the oxide layer through wet etching, growing gate oxide and forming gate polycrystalline silicon; completing the steps of P well and N + source region injection, dielectric layer deposition, contact hole etching and metallization to form a device; the layout design of multidirectional cellular layout is introduced, the process limitation of traditional one-way pitch miniaturization is broken through, on the premise of not depending on a higher-level manufacturing process, the channel density of a unit area is remarkably improved, the on-resistance of the device is effectively reduced, and good process compatibility and reliability are achieved.

The application discloses a MOSFET device and a preparation method thereof, and relates to the technical field of SiC power device design and manufacturing. The MOSFET device comprises a plurality of strip cells, and the strip cells are sequentially stacked from bottom to top with a metal drain, a SiC substrate of a first doping type, a SiC buffer layer of the first doping type and a SiC epitaxial layer of the first doping type, and a plurality of stepped grooves of a symmetrical structure are formed in the SiC epitaxial layer. The MOSFET device utilizes a longitudinal space region to form a multi-directional current channel, under the premise of ensuring the reliability of a gate oxide and the reverse breakdown performance, the multi-directional current channel can effectively improve the channel density and the current density per unit area, the SiC epitaxial layer surface and the metal source electrode above the ohmic contact area of the source groove guarantee the concentrated export of the source current, and the whole realizes the synergistic optimization of low specific on-resistance, high gate oxide reliability and high integration, and the device manufacturing cost is reduced.

The invention provides a trench gate device and a preparation method thereof, the trench gate device comprises a semiconductor layer, a trench gate structure, a first shielding layer, a second shielding layer, a source electrode, a gate electrode and a drain electrode, the semiconductor layer comprises a drift region, a body region located on the upper surface layer of the drift region and a plurality of source regions arranged at intervals and located on the upper surface layer of the body region; the trench gate structure penetrates through the source region and the body region, and the bottom of the trench gate structure extends into the drift region; the first shielding layer is located in the drift region under the trench gate structure and is adjacent to the bottom of the trench gate structure; the second shielding layer is located in the semiconductor layer on the same side of each trench gate structure, the top of the second shielding layer is adjacent to the source region, and the bottom of the second shielding layer is adjacent to the first shielding layer; the source electrode, the grid electrode and the drain electrode are electrically connected with the corresponding areas respectively. The first shielding layer is arranged at the bottom of the groove, and the second shielding layer is arranged in the semiconductor layer on the same side of each groove, so that the channel density and reliability of the device are improved, and the on resistance of the device is reduced.

In a trench MOSFET with a longitudinal channel fin structure, even when the trench spacing is reduced to increase the channel density, the decrease and deviation of the threshold voltage are suppressed. The semiconductor device (1) has: a plurality of trenches (2) which have a length direction in a first direction and a short side direction in a second direction when viewed from above, and are arranged in a plurality of trenches in the second direction; a source region (3) of a first conductivity type, which includes a fin structure divided by the plurality of trenches (2); a channel region (5) of a second conductivity type of fin structure, which is divided by the plurality of trenches (2); and a body region (9) of a second conductivity type, the channel region (5) being connected to the body region (9), and a channel current flowing longitudinally in the channel region (5), the channel region (5) having a first channel region (5A) connected to the lower surface of the source region (3) and a second channel region (5B) disposed below the first channel region (5A), the impurity concentration of the second conductivity type in the first channel region (5A) being higher than that in the second channel region (5B).

The application belongs to the technical field of power devices, and provides a trench gate silicon carbide power device and a preparation method and a chip thereof. A cross-shaped trench gate is arranged, a double-layer structure of a P-type deep well and a P-type heavily doped region is arranged at a cross intersection area of the trench gate, N-type heavily doped regions are arranged on both sides of a first direction trench gate, and the first direction trench gate and the P-type heavily doped region are arranged periodically and alternately. In this way, the current density of the device is greatly improved through a higher channel density. The novel structure can further arrange a deep well as a shielding area at a trench corner, so as to migrate an electric field peak from the trench corner to the bottom of the deep well, so that the depletion region of the device can be closed, the IDSS of the device is reduced, the BVDSS of the device is improved, the reliability of the device is effectively improved, the gate-source coupling is increased by the deep well region, zero-voltage turn-off is beneficial to be realized, and the complexity of a driving system is reduced.

The application discloses a three-dimensional hexagonal cell structure, which comprises a first conductive type epitaxial region, a second conductive type well region in the first conductive type epitaxial region, a first conductive type source region in the second conductive type well region and a second conductive type body region in the first conductive type source region; wherein the second conductive type body region is in a convex shape; and a plurality of convexes with the same width and height are arranged on the first conductive type epitaxial region, the second conductive type well region and the first conductive type source region in the vertical direction of the six sides of the hexagonal cell structure, so as to form a plurality of convex mesa surfaces in each direction and a hexagonal mesa structure intersecting the second conductive type body region on the hexagonal cell structure. The structure makes the device have two channels parallel to the cell surface and perpendicular to the cell surface, thereby improving the channel density, reducing the on-resistance of the channel and improving the current-carrying capacity of the device.

The invention belongs to the technical field of power devices, and provides a trench gate silicon carbide power device, a preparation method thereof and a chip, a cross-shaped trench gate is arranged, a double-layer structure of a P-type deep well and a P-type heavily doped region is arranged in a cross region of the trench gate, and N-type heavily doped regions are arranged on two sides of the trench gate in the first direction, so that the trench gate silicon carbide power device is formed. The first-direction trench gates and the P-type heavily doped regions are periodically and alternately arranged, so that the current density of the device is greatly improved through relatively high channel density, a deep trap can be arranged at a trench corner of the novel structure to serve as a shielding region, and an electric field peak value is migrated to the bottom of the deep trap from the trench corner, so that a depletion region of the device can be closed; iDSS of the device is reduced, BVDSS of the device is improved, reliability of the device is effectively improved, meanwhile, gate-source coupling is added in the deep well region, zero-voltage turn-off is achieved, and complexity of a driving system is reduced.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The invention discloses a semiconductor device and a preparation method, and belongs to the technical field of semiconductors. Comprising a substrate, an N-type drift layer, an N-type source region, a current expansion layer, a P-type shielding layer, a P-type base region, a heavily doped P-type region, a source electrode, a grid electrode, a drain electrode, a grid electrode oxide layer and a source electrode, schottky diodes or channel diodes are integrated on the two sides of the source electrode of the double-groove MOSFET. On the premise that the primitive cell area is not increased and the channel density is not sacrificed, the reverse recovery capability can be obviously improved only by optimizing the existing structure. The core mechanism is that an internally integrated Schottky diode (or channel diode) can bypass a parasitic diode during follow current of an inductive load, so that the reverse recovery capability is directly improved.

This application discloses a MOSFET and its fabrication method, relating to the field of semiconductor technology. The MOSFET includes a substrate and an epitaxial layer and a current spreading layer sequentially disposed on the substrate. A P-type well region is formed on the current spreading layer, extending along a first direction. An N+ doped region and a P+ doped region are formed within the P-type well region, wherein the N+ doped region surrounds the outer periphery of the P+ doped region. A conductive channel is formed between the P-type well region and the epitaxial layer. A source contact is disposed on the P+ doped region. This MOSFET and its fabrication method can reduce cell size and increase channel density without changing the process boundaries.

The invention discloses an ultrahigh-resolution integrated calculation spectrometer based on a single waveguide and an implementation method, and belongs to the field of spectral measurement. The spectrometer comprises a cladding, an input end face coupler, a multi-stage reflection measurement waveguide, a phase modulator, an output end face coupler, a photoelectric detector and a microcontroller. The multi-stage reflection measurement waveguide comprises multiple stages of microstructure reflection units which are sequentially connected through waveguides in the propagation direction. The invention solves the problems of low resolution and insufficient bandwidth and expandability, has high resolution and large bandwidth performance, and realizes 0.9 pm-level double-peak distinguishable and 800nm effective bandwidth in the near-infrared band; due to the simple structure of the single straight waveguide, high independent channel density can be obtained without a long-chain cascade device; the waveguide loss can be maintained within 5 dB by limiting the reflectivity and the segment number of the micro-structure reflection units, and a good detection effect can also be achieved for low-intensity light to be detected; the method is applied to high-precision measurement of various complex spectrums.

The present disclosure relates to a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductor manufacturing. In the semiconductor device, a top surface of a first source region of a first conductive type is flush with a top surface of a substrate and an outer surface is located in the substrate; a first well ring of a second conductive type covers the outer surface of the first source region and is embedded in the substrate via the top surface of the substrate; a semiconductor column of the second conductive type penetrates the first source region and the first well ring in a direction towards the substrate via the top surface of the substrate; and spaced first gate structures and second gate structures cover top surfaces of the first well ring and the first source region, and the first gate structures, the semiconductor column and the second gate structures are sequentially distributed in a first direction parallel to the top surface of the substrate. At least the MOS channel density can be improved, the impedance and power loss during forward conduction of the MOS device can be reduced, and the surge resistance can be improved.

In a trench MOSFET with a vertical channel fin structure, even when the trench spacing is reduced to increase the channel density, a decrease and variation of a threshold voltage are suppressed. A semiconductor device 1 comprises: a plurality of trenches 2, each having, in a plan view, a longitudinal direction extending in a first direction and a transverse direction extending in a second direction, with the plurality of trenches arranged along the second direction; a source region 3 of a first conductivity type, wherein the source region comprises a fin structure defined by the plurality of trenches 2; a channel region 5 of a second conductivity type, wherein the channel region has a fin structure defined by the plurality of trenches 2; and a body region 9 of the second conductivity type.Channel region 5 is connected to body region 9, and a channel current flows vertically through channel region 5. Channel region 5 comprises a first channel region 5A, which is in contact with a lower surface of source region 3, and a second channel region 5B, which is located below the first channel region 5A, and a concentration of a second conductivity-type impurity in the first channel region 5A is greater than a concentration of the second conductivity-type impurity in the second channel region 5B.

The invention discloses a semiconductor device and a manufacturing method thereof, and the device comprises the components of a substrate which is provided with a first source region and a first body region on a first surface; the at least one groove is formed on the first surface of the substrate; the fin-shaped grid electrode is located on the side wall of one side of the groove; the interlayer dielectric layer covers the fin-shaped grid electrode and partially fills the groove; the second source region is located at the bottom of the groove and connected with the fin-shaped grid electrode, the second body region surrounds the second source region, the second source region is provided with the first doping type, and the second body region is provided with the second doping type; the shielding region surrounds the bottom of the groove and has the second doping type, and the depth of the shielding region is larger than that of the second body region; and the source contact layer is in contact with the top of the first source region and the part, which is not covered by the interlayer dielectric layer, in the groove. The device can increase the channel density, reduce the contact resistance and improve the safety.

This invention discloses a silicon carbide MOSFET layout structure with a stepped source doped region, comprising multiple planar gate MOSFET cells. Each planar gate MOSFET cell includes a source doped region, a body contact doped region, a gate structure, and a source ohmic contact hole. The source doped regions are arranged in a stepped manner along the cell width direction and form at least one groove structure. The body contact doped regions are spaced apart within the grooves formed by the source doped regions. The length direction of the gate structure is consistent with the length direction of the cell and is periodically spaced along the width direction of the cell. The source ohmic contact holes are located within the grooves and distributed along the length direction of the cell. This invention aims to reduce the on-resistance of the device by effectively reducing the cell width, thereby increasing the channel density and reducing the on-resistance.

This application discloses an asymmetric in-layer shielding structure, an interposer, and a semiconductor package for optoelectronic co-packaging, belonging to the field of semiconductor device technology. The asymmetric in-layer shielding structure for optoelectronic co-packaging of this application forms an asymmetric shielding layout by setting a first grounding structure and a second grounding structure with different widths and gaps on both sides of the transmission structure. This significantly enhances the shielding effectiveness on the side closer to the electromagnetic interference source, achieving targeted suppression of strong electromagnetic interference on one side. Simultaneously, the size of the grounding structure on the side farther from the interference source is relatively weakened to free up wiring space, balancing shielding effectiveness and signal channel density. The dimensional parameters of each shielding unit are adapted to the preset target value of the characteristic impedance of the transmission structure, ensuring that the characteristic impedance of the transmission structure remains constant at 100Ω±10% during differential signal transmission, effectively avoiding impedance mismatch and signal reflection caused by improper shielding structure dimensions.

The application provides a low-loss trench gate silicon carbide MOSFET device and a manufacturing method, and the device structure comprises an N+ substrate, an N- epitaxial layer, an N+ buffer layer, a P-type well region, an N+ source region, a P+ shielding region, a polysilicon gate, a source metal and a drain metal. The application is based on an asymmetric trench gate silicon carbide MOSFET device, which has a channel on one side of a silicon carbide trench and is wrapped by P+ on the other side. The integrated FinFET structure increases the channel density, and at the same time, the extremely narrow Fin-shaped mesa reduces the electric field intensity at the channel and the interface scattering, so that the mobility of the channel in the Fin-shaped mesa is increased. In addition, the P+ structure wrapping the gate trench reduces the gate oxide electric field at the trench corner, so that the gate oxide electric field intensity of the device after the introduction of the FinFET structure is in the safe working range.