54 results about "Channel density" patented technology

The invention relates to the technical field of bushing detection, and discloses a bushing insulation state detection method based on multi-parameter real-time monitoring. The method comprises the following steps: acquiring multi-dimensional monitoring data such as a partial discharge pulse sequence, dielectric loss angle tangent value fluctuation data and surface leakage current density distribution in a bushing operation environment in real time; carrying out insulation defect feature extraction on the data set, and generating an insulation defect distribution map containing a creeping discharge track, an internal air gap position mark and a carbonization channel density index; high-risk and potential defect areas are divided by adopting a dynamic threshold segmentation algorithm, boundary coordinates are determined, and an insulation state evaluation vector containing parameters such as a surface discharge intensity index and the like is constructed according to the boundary coordinates; and inputting the vector into a pre-trained insulation aging prediction model, and outputting a bushing residual insulation life estimated value and a defect development priority sequence. According to the method, all-around accurate monitoring and pre-judgment of the insulation state of the sleeve are achieved, and scientific support is provided for operation and maintenance decision making of the sleeve.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The invention provides a trench gate silicon carbide MOSFET device integrated with a FinFET structure and a manufacturing method. The device structurally comprises an N + substrate, an N-epitaxial layer, an N + buffer layer, a P-type well region, a carrier expansion layer (CSL layer), an N + source region, a P + shielding region, a polycrystalline silicon gate, a source trench, source metal and drain metal. According to the invention, the FinFET structure with the fin width less than 300nm is integrated into the gate trench of the trench gate silicon carbide MOSFET. The integrated FinFET increases the channel density of the device, meanwhile, the carrier distribution is more uniform due to the extremely narrow Fin-shaped table top, the influence of interface scattering on the carriers is weakened, and the channel mobility is increased. Therefore, after the FinFET structure is integrated, the specific on-resistance of the trench gate silicon carbide MOSFET is obviously reduced. Meanwhile, the device is provided with a source trench which is deep and is wrapped by a P + shielding region, and the P + shielding region prevents the oxide layer at the corner of the trench from being broken down in advance.

The invention provides a low-loss trench gate silicon carbide MOSFET device and a manufacturing method. The device structurally comprises an N + substrate, an N-epitaxial layer, an N + buffer layer, a P-type well region, an N + source region, a P + shielding region, a polycrystalline silicon gate, source metal and drain metal. According to the silicon carbide MOSFET device based on the asymmetric trench gate, a channel is formed in one side of a silicon carbide trench, and the other side of the silicon carbide trench is wrapped by P +. The integrated FinFET structure increases the channel density, and meanwhile, the extremely narrow Fin-shaped mesa weakens the electric field intensity and interface scattering at the channel, so that the mobility of the channel in the Fin-shaped mesa is increased. In addition, the P + structure wrapping the gate trench reduces the electric field of the gate oxide layer at the corner of the trench, so that the electric field intensity of the gate oxide layer of the device is within a safe working range after the FinFET structure is introduced.

A superjunction trench MOSFET structure and its manufacturing method belong to the technical field of superjunction MOSFETs. A superjunction trench MOSFET structure includes an N+ substrate, a first cell structure, and a second cell structure. Among them, both the first cell structure and the second cell structure are regular hexagons. The first cell structure includes a first N pillar region and a first P pillar region surrounding the first N pillar region, and a first source trench is provided on the first N pillar region. The second cell structure includes a second N pillar region and a second P pillar region surrounding the second N pillar region, and a second source trench is provided on the second N pillar region. A number of second cell structures surround the first cell structure. The second cell structure further includes a gate trench, a first channel is formed between the gate trench and the first source trench, a second channel is formed between the gate trench and the second source trench, and the lengths of the first channel and the second channel are different. By setting a regularly tiled cell structure in the shape of a regular hexagon and having an asymmetric double channel, the present application not only improves the channel density but also provides a good gate oxide protection effect.

A semiconductor device is provided which is a trench MOSFET with a vertical channel fin structure, capable of improving short-circuit tolerance and reducing gate capacitance while maintaining high channel density.A semiconductor 1 is configured so that a channel current flows in the vertical direction, and comprises: a plurality of trenches having a longitudinal direction in a first direction and a lateral direction in a second direction in plan view, the plurality of trenches being arranged in the second direction; a first source region 3 of a first conductivity type; a second source region 4 of the first conductivity type and including a region having a fin structure at least partially partitioned by the plurality of trenches 2; a channel region 5 of a second conductivity type and having a fin structure partitioned by the plurality of trenches 2; a gate insulating film and gate electrodes disposed in the trenches 2; and a JFET region 8 of the first conductivity type and a body region 9 of the second conductivity type.The second source region 4 has a shallower depth from a surface than the first source region 3.

The invention provides a semiconductor device capable of improving short-circuit tolerance and reducing gate capacity while maintaining a high channel density in a trench MOSFET having a vertical channel fin structure. The present invention is provided with: a plurality of trenches (2) arranged in a second direction and having a long side direction in a first direction and a short side direction in the second direction in plan view; a first source region (3) of the first conductivity type; a second source region (4) of the first conductivity type including a region at least partially having a fin structure demarcated by the plurality of trenches (2); a second conductivity-type channel region (5) having a fin structure, the channel region (5) being partitioned by the plurality of trenches (2); a gate insulating film and a gate electrode disposed inside the trench (2); a JFET region (8) of the first conductivity type; and a body region (9) of a second conductivity type in which a channel current flows in the vertical direction, and in the semiconductor device (1), the depth of the second source region (4) from the surface is shallower than that of the first source region (3).

The invention discloses an insulated gate bipolar transistor device and a preparation process thereof, and the device comprises a substrate, a drain electrode which is formed below the substrate, a dielectric layer which is formed above the substrate, a source electrode which is formed above the dielectric layer, and a plurality of grooves which are formed in the substrate in a downward etching and sinking manner and are independently arranged, independent trench gates are deposited in the trenches, the cross section of the plurality of trenches is of a circular or annular or polygonal closed structure, and the trench gates are insulated and isolated from the side walls of the trenches and the source electrodes through dielectric layers. The novel groove type IGBT structure is achieved through the groove gates arranged in a circular layout mode, the structure has the advantages of being high in channel density, large in current density, simple in process and the like, and the chip area and the cost can be reduced while the current capacity is kept; or the current density and the power density of the device are improved while the chip area is maintained, and the on-state loss is reduced.

The invention provides a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof. The device comprises a drain metal layer; the epitaxial structure is arranged on the drain electrode metal layer; the at least two grid electrode grooves are formed in one side, deviating from the drain electrode metal layer, of the epitaxial structure; gate polycrystalline silicon is arranged in the gate trench; the at least one source electrode groove is arranged between two adjacent grid electrode grooves, and source electrode polycrystalline silicon is arranged in the source electrode groove; and the source electrode metal layer is electrically connected with the source electrode polycrystalline silicon. According to the invention, under the condition that the channel density is not reduced, the source-drain capacitance can be increased, and the EMI characteristic of the device can be optimized by adjusting the resistance of the source polysilicon in the source trench.

The invention belongs to the technical field of power semiconductor devices, and relates to a super-junction IGBT device with a split gate structure and a preparation method of the super-junction IGBT device. The device comprises collector metal, a P-type collector, an N-type field stop layer, a super junction N column, a super junction P column, a P-type buried layer, a trench gate structure and a trench emitter structure which are sequentially stacked from bottom to top, and the trench gate structure and the trench emitter structure are connected with an N-type charge storage layer, a P-type base region and an N + emitter region. The P columns / N columns of the device are alternately arranged in the Y direction, the cell width is reduced, meanwhile, the parasitic PMOS introduced by only adding one photoetching plate acts, and the device has high channel density and a wide short-circuit safe working area. In addition, the Miller capacitance of the super-junction IGBT is reduced, the negative gate capacitance effect is suppressed, the surge current of the device is reduced, and the control capability of the gate of the device on dv / dt is improved. According to the invention, an extra path is provided for redundant holes stored in the drift region, the turn-off speed of the device is obviously improved, and the switching loss is reduced.

The present application relates to the field of semiconductor technology, and provides a power device layout structure and a manufacturing method thereof, wherein the power device layout structure includes a plurality of cells repeatedly arranged along a first direction and a second direction, wherein the cells include: a P-type well region doping region, an N-type heavily doped region, a P-type heavily doped region, a JFET region doping region, a gate and a source through hole, wherein the first main island portion of each cell is connected to the first auxiliary arm of the cell adjacent in the first direction, and the first auxiliary arm of each cell and the first auxiliary arm of an adjacent cell in the second direction are the same auxiliary arm that overlap with each other; the gate is a split gate structure, covering the edge or all of the JFET region doping region, the P-type well region doping region and the N-type heavily doped region. The present application effectively solves the technical problem of low channel density of planar power devices; while increasing the channel density, it does not increase too much gate-drain capacitance.

The present invention discloses a three-dimensional strip-shaped cell structure, comprising: a first-conductivity-type epitaxial region, a second-conductivity-type well region located within the first-conductivity-type epitaxial region, a meandering first-conductivity-type source region located within the second-conductivity-type well region, and a second-conductivity-type body region located within the meandering first-conductivity-type source region. In the horizontal direction, the first-conductivity-type epitaxial region, the second-conductivity-type well region, the meandering first-conductivity-type source region, and the second-conductivity-type body region are each provided with a plurality of protrusions or grooves of the same height and width, thereby forming a plurality of straight-line mesa structures or a plurality of straight-line groove structures on the strip-shaped cell structure. This structure enables the device to have not only parallel channels parallel to the cell surface but also vertical channels perpendicular to the cell surface, thereby increasing the channel density, reducing the on-resistance of the channel, and thereby improving the current flow capacity of the device.

The invention provides a trench-type power device and a manufacturing method thereof. The power device comprises a semiconductor layer, and a cellular functional region, a shielding structure and a grounding structure which are located in the semiconductor layer. The cellular functional region includes a plurality of trench gates. The shielding structure comprises at least one shielding area, and the shielding area extends below the plurality of trench gates. The grounding structure comprises at least one grounding area which is grounded. At least one grounding area is electrically connected with the same shielding area to form a shielding grounding unit. The conductive type of the shielding grounding unit is different from that of the semiconductor layer. According to the power device, the electric field concentration degree of the bottoms of the trench gates is weakened through the shielding grounding unit, and the reliability of the power device is improved. Through the structure arrangement of the shielding grounding unit, the channel density of the power device can be ensured while a good shielding protection effect is ensured, the conduction capability of the power device is improved, and the overall structure is simple. The manufacturing method is simple in process steps.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The application relates to a power device and a preparation method thereof and electronic equipment. The device comprises a substrate, a first surface of the substrate comprising an epitaxial layer; the epitaxial layer comprising source regions, base regions and shielding regions arranged along a first direction towards the substrate via a top surface; a plurality of gates spaced along a second direction parallel to the first surface and penetrating the source regions and the base regions along the first direction and partially embedded in the shielding regions; the gate comprising a gate conductive layer and a gate oxide layer arranged along the first direction; an interlayer dielectric layer located on the top surface of the epitaxial layer and comprising an extension penetrating the gate conductive layer along the first direction and in contact with the gate oxide layer; and a metal layer located on the top surface of the interlayer dielectric layer and comprising a first source electrode extending into the gate via the top surface of the extension; the width and depth of the first source electrode being related to the gate-source capacitance of the power device. The channel density can be ensured while improving the reliability of the gate oxide layer.

The embodiment of the invention discloses a micro-fluidic chip and application thereof in nucleic acid detection.The micro-fluidic chip comprises a chip part, the chip part comprises a substrate, and the substrate comprises a top layer, a middle layer and a bottom layer; the substrate is provided with a microfluidic channel; three-dimensional patterns are arranged on the upper surface and the lower surface of the middle layer, and the pattern on the upper surface of the middle layer and the top layer define an upper-layer microfluidic channel in the microfluidic channel; the pattern on the lower surface of the middle layer and the bottom layer define a lower-layer microfluidic channel in the microfluidic channel; the extending directions of the upper-layer microfluidic channel and the lower-layer microfluidic channel are parallel to the plane of the substrate; the middle layer comprises a through hole used for forming a vertical microfluidic channel, the extension direction of the vertical microfluidic channel is perpendicular to the plane where the substrate is located, and at least part of the vertical microfluidic channel is used for communicating the upper-layer microfluidic channel with the lower-layer microfluidic channel. According to the embodiment of the invention, an overpass type microfluidic channel can be formed, the channel density can be improved, and a flexible communication relation can be constructed to meet complex reaction requirements.

This application discloses a MOSFET and its fabrication method, relating to the field of semiconductor technology. The MOSFET includes a substrate and an epitaxial layer and a current spreading layer sequentially disposed on the substrate. A P-type well region is formed on the current spreading layer, extending along a first direction. An N-type doped region and a source contact are formed within the P-type well region. The N-type doped region surrounds the outer periphery of the source contact, and the sidewall of the source contact contacts the sidewall of the N-type doped region. This MOSFET and its fabrication method can reduce the cell size and increase the channel density without changing the process boundaries.

The invention relates to the technical field of semiconductor power devices, in particular to a discrete device and a manufacturing method thereof, and the method comprises the steps: providing an N + substrate and growing an N epitaxial layer; depositing and patterning a masking layer to etch to form a deep groove; growing a thin oxide layer and depositing a thick oxide layer; depositing and etching polycrystalline silicon to form a shield gate; removing part of the oxide layer, depositing a new oxide layer, and grinding; depositing an oxide layer as a masking layer, and forming a multidirectional shallow slot pattern through photoetching and etching; adjusting the thickness of the oxide layer through wet etching, growing gate oxide and forming gate polycrystalline silicon; completing the steps of P well and N + source region injection, dielectric layer deposition, contact hole etching and metallization to form a device; the layout design of multidirectional cellular layout is introduced, the process limitation of traditional one-way pitch miniaturization is broken through, on the premise of not depending on a higher-level manufacturing process, the channel density of a unit area is remarkably improved, the on-resistance of the device is effectively reduced, and good process compatibility and reliability are achieved.

The utility model provides an injection structure and a silicon carbide gate-controlled device structure. The injection structure comprises cells arranged in an array and at least one P-doped region. Each cell comprises a pbase doped region, an N + doped region and a P + doped region; a groove is formed in one end face of the pbase doped region, the P + doped region is located at the center of the groove and is in contact connection with a source electrode, and the N + doped region is located between the side face of the P + doped region and the side wall of the groove; the gate dielectric region is provided with a first gap which corresponds to the cell and is plugged by the source contact, and the gate contact is provided with a second gap corresponding to the P doped region and a third gap corresponding to the first gap; the pbase doped region is connected with the gate dielectric region; and one end surface of the P-doped region is connected with the gate dielectric region. The injection structure and the silicon carbide gate-controlled device structure provided by the utility model can improve the channel density, reduce the gate-oxide electric field intensity, block the leakage current of the silicon carbide device, reduce the reverse transmission capacitance, and reduce the switching loss of the device.

The invention relates to a power device and a preparation method thereof, and electronic equipment, and the device comprises the components of a substrate which comprises an epitaxial layer on a first surface; the epitaxial layer internally comprises a source region, a base region and a shielding region which are arranged along a first direction towards the substrate through the top surface; the grid electrodes are distributed at intervals along a second direction parallel to the first surface, penetrate through the source region and the base region along the first direction, and are partially embedded into the shielding region; the gate electrode comprises a gate conductive layer and a gate oxide layer which are arranged along a first direction; the interlayer dielectric layer is located on the top surface of the epitaxial layer and comprises an extension part which penetrates through the gate conductive layer in the first direction and is in contact with the gate oxide layer; the metal layer is positioned on the top surface of the interlayer dielectric layer and comprises a first source electrode which extends into the grid electrode through the top surface of the extension part; the width and depth of the first source are associated with the gate-source capacitance of the power device. The reliability of the gate oxide layer can be improved while the channel density is ensured.

The invention belongs to the technical field of power semiconductor devices, and relates to a super-junction IGBT (Insulated Gate Bipolar Translator) with a split gate structure and a manufacturing method thereof. The device comprises collector metal, a P-type collector, an N-type field stop layer, a super junction N column, a super junction N column contact, a trench gate structure and a trench emitter structure which are sequentially stacked from bottom to top, a P-type doped region is injected into the bottom of a trench gate, and the trench gate structure and the trench emitter structure are connected with an N-type charge storage layer, a P-type base region and an N + emitter region. The P columns / N columns of the device are alternately arranged in the Y direction, cells are reduced, meanwhile, the P columns and the N columns act on a parasitic PMOS, and the device has high channel density and a wide short-circuit safe working area. In addition, the Miller capacitance of the super-junction IGBT is reduced, the negative gate capacitance effect is suppressed, the surge current is reduced, and the control capability of the device on dv / dt is improved. According to the invention, an extra path is provided for redundant holes stored in the drift region, the turn-off speed of the device is obviously improved, and the switching loss is reduced.

According to the trench gate MOSFET structure provided by the invention, the first shielding region and the second shielding region can reduce the maximum electric field in the gate oxide at the bottom of the gate trench structure and improve the reliability of a device, meanwhile, at least one side wall of the first gate trench structure is provided with a channel for conducting current, at least one side wall of the second gate trench structure is provided with a channel for conducting current, and the reliability of the device is improved. The channel density of the device is increased, so that the conduction capability of the device is improved, and the conduction resistance of the device is reduced; besides, a third gate trench structure is arranged between the first gate trench structure and the second gate trench structure, and channels are formed in two side walls of the third gate trench structure and can conduct current, so that the channel density of the device is further increased, and the conduction capability of the device is improved.

A three-dimensional carrier stored trench IGBT and a manufacturing method thereof are provided. A P-type buried layer and a split gate electrode with equal potential to an emitter metal is introduced on the basis of the traditional carrier stored trench IGBT, which can effectively eliminate the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation, and at the same time can reduce the on-state voltage drop and improve the trade-off relationship between the on-state voltage drop Vceon and the turn-off loss Eoff. The split gate electrodes is introduced in the Z-axis direction, so that the gate electrodes are distributed at intervals. Therefore, the channel density is reduced. The turning on of the parasitic PMOS has a potential-clamping effect on the NMOS channel, so that the saturation current can be reduced and a wider short-circuit safe operating area (SCSOA) can be obtained.

The application discloses a MOSFET device and a preparation method thereof, and relates to the technical field of SiC power device design and manufacturing. The MOSFET device comprises a plurality of strip cells, and the strip cells are sequentially stacked from bottom to top with a metal drain, a SiC substrate of a first doping type, a SiC buffer layer of the first doping type and a SiC epitaxial layer of the first doping type, and a plurality of stepped grooves of a symmetrical structure are formed in the SiC epitaxial layer. The MOSFET device utilizes a longitudinal space region to form a multi-directional current channel, under the premise of ensuring the reliability of a gate oxide and the reverse breakdown performance, the multi-directional current channel can effectively improve the channel density and the current density per unit area, the SiC epitaxial layer surface and the metal source electrode above the ohmic contact area of the source groove guarantee the concentrated export of the source current, and the whole realizes the synergistic optimization of low specific on-resistance, high gate oxide reliability and high integration, and the device manufacturing cost is reduced.

The application discloses a high short-circuit resistance current carrier storage trench gate IGBT device, which is configured to comprise a plurality of interval trenches (1), and a P+ area (2) for improving short-circuit resistance of the IGBT is formed between adjacent trenches (1). The IGBT device provided by the application forms the P+ area periodically between the trenches, so that the trench sidewall of the P+ area cannot form a conductive channel, thereby reducing the overall channel density, reducing the saturation current of the device, and greatly improving the short-circuit resistance of the device.

The present invention discloses a silicon carbide trench gate MOSFET device and a method for preparing the same. The device is composed of two alternating cell structures, wherein structure one is a conventional silicon carbide trench gate MOSFET structure with a P-type shielding layer below the gate, while structure two utilizes selective tilted ion implantation to form a P-type connection region below the gate trench side that connects the P-type base region on the side of the gate and the P-type shielding layer below the gate, thereby achieving effective grounding of the P-type shielding layer and improving the shielding effect of the P-type shielding layer. Furthermore, an additional N-type connection region for connecting the channel is added inside the P-type connection region, so that electrons in the source region can flow to the JFET region through the N-type connection region along the alternating arrangement direction of the two structures after passing through the base region channel, thereby increasing the effective channel density and reducing the on-resistance of the device.

The invention provides a trench gate MOS device and a preparation method thereof, the trench gate MOS device comprises a semiconductor structure, a shielding layer, a body region, a source region, a contact region, a trench structure, an injection region and a source / drain / gate, the semiconductor structure comprises a substrate, a drift region and a current transmission layer; the shielding layers arranged at intervals are located in the current transmission layer; the body region is positioned on the upper surface layers of the shielding layer and the current transmission layer; two ends of the source region are respectively positioned on the shielding layer and the current transmission layer; the contact regions are located between the adjacent source regions; the trench structure comprises a trench, a gate dielectric layer and a gate conductive layer, wherein the trench penetrates through the source region and the body region, and two side walls of the trench are positioned in the current transmission layer and the shielding layer; the upper surface of the injection region is flush with the bottom surface of the body region; and the source / drain / grid electrode is electrically connected with the corresponding region respectively. Through the combination of the shielding layer and the injection region, the channel density of the device is improved, the on-resistance of the device is reduced, and the ratio of Cgd / Cgs is reduced at the same time.

The present invention discloses a silicon carbide power MOSFET device and a manufacturing method thereof. By using a self-alignment process and a deep P-type sidewall region formed by one or more ion implantations on both sides of the trench gate, the side of the trench serves as the channel region, and the side below serves as the shielding layer, making the device cell structure more compact, increasing the channel density, reducing the channel resistance, and shortening the distance from the P-type shielding layer to the trench, which can effectively shield the gate oxide electric field.

The present invention suppresses a decrease or variation in a threshold voltage even when a trench pitch is reduced in order to increase a channel density in a trench MOSFET having a vertical channel fin structure. A semiconductor device 1 includes: a plurality of trenches 2 having a long-side direction as a first direction, and a short-side direction as a second direction when seen in plan view, and arranged in the second direction; a source region 3 of a first conductivity type including a fin structure partitioned by the plurality of trenches 2; a channel region 5 of a second conductivity type having a fin structure partitioned by the plurality of trenches 2; and a body region 9 of the second conductivity type. The channel region 5 is connected to the body region 9, and a channel current flows in the channel region 5 vertically. The channel region 5 has a first channel region 5A contacting the lower surface of the source region 3, and a second channel region 5B disposed below the first channel region 5A. The first channel region 5A has a higher impurity concentration of the second conductivity type than the second channel region 5B.

The invention provides a trench gate device and a preparation method thereof, the trench gate device comprises a semiconductor layer, a trench gate structure, a first shielding layer, a second shielding layer, a source electrode, a gate electrode and a drain electrode, the semiconductor layer comprises a drift region, a body region located on the upper surface layer of the drift region and a plurality of source regions arranged at intervals and located on the upper surface layer of the body region; the trench gate structure penetrates through the source region and the body region, and the bottom of the trench gate structure extends into the drift region; the first shielding layer is located in the drift region under the trench gate structure and is adjacent to the bottom of the trench gate structure; the second shielding layer is located in the semiconductor layer on the same side of each trench gate structure, the top of the second shielding layer is adjacent to the source region, and the bottom of the second shielding layer is adjacent to the first shielding layer; the source electrode, the grid electrode and the drain electrode are electrically connected with the corresponding areas respectively. The first shielding layer is arranged at the bottom of the groove, and the second shielding layer is arranged in the semiconductor layer on the same side of each groove, so that the channel density and reliability of the device are improved, and the on resistance of the device is reduced.