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Fast readout method and switched capacitor array circuitry for waveform digitizing

A technology of switched capacitors and circuits, applied in the field of switched capacitor array circuits

Active Publication Date: 2011-01-19
PAUL SCHERRER INSTITUT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, when focusing on extremely fast readout of a single event, this technique suffers from the dead time periods required to read out all 1024 cells per channel

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  • Fast readout method and switched capacitor array circuitry for waveform digitizing
  • Fast readout method and switched capacitor array circuitry for waveform digitizing
  • Fast readout method and switched capacitor array circuitry for waveform digitizing

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Embodiment Construction

[0030] is shown as figure 1 The present invention in the functional block diagram in FIG. 1 represents an SCA chip 2 capable of sampling 12 differential input channels CH0 to CH11 at a sampling speed of 10 MSPS to 5 GSPS. Analog signal waveform 18 (see Figure 5 ) are stored in 1024 sample cells CELL0 to CELL1023 per channel CH0 to CH11 and can be read out for external digitization after sampling via the read shift register 4 clocked at 33 MHz. The write signal for the sampling cells CELL0 to CELL1023 is generated by a chain of inverters generated in a domino wave circuit 6 on chip 2 (domino principle). The domino wave runs continuously until stopped by a trigger signal that makes DENABLE low. (It has to be noted: the domino wave is still running, but separate from the sampling unit and therefore has no effect on waveform sampling as long as the DENABLE signal is set low). The read shift register 4 clocks the content of the sampling cells to the multiplexed output MUX or th...

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Abstract

The present invention represents a technique to reduce the readout time of switched capacitor array (SCA) circuitries. A possible implementation is a SCA chip capable of sampling 12 differential input channels at a sampling speed of 10 MSPS to 5 GSPS. The analog waveform can be stored in 1024 sampling cells per channel, and can be read out after sampling via a shift register clocked at 33 MHz for external digitization. The write signal for the sampling ceils is generated by a chain of inverters (domino principle) generated on the chip. The domino wave is running continuously until stopped by a trigger. A read shift register clocks the contents of the sampling cells either to a multiplexed or to individual outputs, where it can be digitized with an external ADC. It is possible to read out only a part of the waveform for reducing the digitization time. The high channel density, high analog bandwidth of 450 MHz, and low noise of 0.35 mV (after offset calibration) makes this chip ideally suited for low power, high speed, high precision waveform digitizing. Fabricated on an advanced CMOS process in a radiation hard design, the present chip is available in a 64-lead low profile quad flat pack (LQFP) and a 64-pin quad flat non-leaded package (QFN).

Description

technical field [0001] The present invention relates to switched capacitor array circuits and methods for fast waveform digitization. Background technique [0002] Many industries and research fields require high sampling rates to digitize waveforms. This includes the readout of photomultiplier tubes, gas detectors and silicon detectors in particle physics experiments and synchrotron radiation sources. Traditionally, these applications have used blink-type ADCs with sampling speeds up to several GHz, but the technology reaches its limits when high channel density, low power, and accuracy greater than 10 bits are required. An alternative method is a switched capacitor array (SCA). [0003] Such an SCA chip has been developed at the Paul Scherrer Institute in Switzerland for fast waveform digitization of PMT and drift chamber signals for MEG experiments. The experimental search sensitivity is as low as 10 -13 The lepton-flavor-violating decay of μ + →e + gamma. The chip...

Claims

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Application Information

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IPC IPC(8): G11C27/02G11C27/04
CPCG06G7/26G11C27/04G11C27/024G11C19/188
Inventor S·里特R·蒂纳波里
Owner PAUL SCHERRER INSTITUT
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