71 results about "Switched capacitor array" patented technology

The invention provides a successive approximation type single-slope analog-to-digital converter, a readout circuit and an image sensor, and the analog-to-digital converter comprises a high-order analog-to-digital conversion module which carries out the successive approximation type conversion of a pixel signal to obtain high-order conversion data and residual pixel data, and comprises a switched capacitor array, a comparator, a logic control circuit and a prediction circuit; the switched capacitor array receives pixel signals, and the upper electrode plate is connected to the comparator; the prediction circuit is connected with the switched capacitor array and controls the voltage of a lower pole plate of the switched capacitor array under the control of the logic control circuit and the comparator; and the low-order analog-to-digital conversion module is used for performing single-slope conversion on the residual pixel data to obtain low-order conversion data. The high-order conversion data of the current row of pixels is predicted through the prediction circuit according to the quantization result of the previous row of pixels, so that the quantization frequency can be effectively reduced, the power consumption can be reduced, the quantization efficiency can be improved, and the problem of how to improve the quantization efficiency of an analog-to-digital converter in the image sensor is solved.

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

The invention relates to the technical field of radio frequency integrated circuits, and discloses a dynamic bias C-type voltage-controlled oscillator based on a CMOS (complementary metal oxide semiconductor) process, the voltage-controlled oscillator adopts a C-type structure, a cross-coupled network adds two resistors and a capacitor on the basis of a cross-coupled transistor, a circuit works in the C type by adjusting bias voltage at a resistor end, and the voltage-controlled oscillator works in the C type. The C-type voltage-controlled oscillator, a tail current source, a variable capacitance network, a switched capacitor array and a fixed LC resonance network form a core structure of the C-type voltage-controlled oscillator capable of numerical control tuning and voltage-controlled tuning, so as to determine the working frequency of the circuit and realize numerical control and voltage-controlled tuning functions; and the operational amplifiers with two bandwidth modes are introduced, so that the problem of difficult oscillation starting is solved, and the oscillation starting speed and the phase noise performance in a stable state are considered at the same time.

The invention discloses a voltage-controlled oscillator with small-area and wide-band modulation capability, and particularly relates to the technical field of radio frequency integrated circuits. The voltage-controlled oscillator comprises two symmetrical voltage-controlled oscillation units; wherein each voltage-controlled oscillation unit comprises a resonance circuit; the resonance circuit comprises an LC resonance circuit and a negative resistance active circuit; the LC resonant circuit comprises a switched capacitor array; two ports of the LC resonance circuit are respectively connected to the output ends of the cross coupling MOS pair; the switched capacitor array is used for providing at least two gears of variable capacitance; the negative resistance active circuit comprises a cross coupling pair transistor and a bias current source; the mode change-over switch circuit comprises two groups of symmetrical switch MOS (Metal Oxide Semiconductor) tubes and mutual inductance transformer taps; and in each voltage-controlled oscillation unit, a tap of the resonant inductor is connected with a corresponding port of the mode switching switch MOS tube. According to the scheme, the mismatch effect caused by a small process and the stray capacitance caused by layout and wiring can be reduced as much as possible, and the chip area can be reduced while the performance is ensured, so that the tape-out cost is reduced.

The invention discloses an electric meter sampling filter chip and system integrated with a programmable anti-aliasing filter, and relates to the field of electric energy metering chips, the electric meter sampling filter chip comprises a programmable anti-aliasing filter module, a digital control and interface module and a cooperative control unit, through binary weighted control of a switched capacitor array, the cut-off frequency can be dynamically adjusted within the range of 1 kHz to 100 kHz, and the cut-off frequency can be adjusted within the range of 1 kHz to 100 kHz. Switching of a Bessel mode, a Butterworth mode and a Chebyshev mode is physically achieved by reconstructing a feedback network, a programmable AAF, an ADC, control logic and a digital interface are integrated into a single chip, and the number of external elements such as an RC network and an operational amplifier is reduced; aDC sampling data is analyzed through FFT, the signal-to-noise ratio is calculated in real time, the filter mode is automatically switched, a hardware interrupt pin triggers notification after configuration is completed, MCU polling is replaced, and frequency response is ensured to be accurate and controllable through laser trimming of a switched capacitor array.

The invention discloses a charging system and a charging method for an aircraft. The self-adaptive battery equalization module is integrated in the aircraft energy storage module and is matched with the transmitting end resonant coupling module and the energy scheduling control module which are arranged on the ground charging station, so that deep integration of an electric energy transmission link is realized through modular topology reconstruction. Wherein a multi-channel active equalization topology is embedded in the self-adaptive battery equalization module, and a dynamic charge redistribution technology based on a switched capacitor array is adopted to realize single voltage deviation control in a battery pack. According to the system, a bidirectional magnetic resonance coupling technology is added on the basis of a traditional physical contact type charging interface, so that an adaptive charging protocol can be triggered without mechanical alignment after an aircraft lands on a base, cross-air-gap energy transmission is realized through high-frequency inversion and resonance compensation, the energy conversion efficiency of the system and the reliability of the charging process are successfully and remarkably improved, and the charging efficiency is improved. And an all-weather autonomous energy supply solution is provided for mobile platforms such as an unmanned aerial vehicle cluster.

The invention relates to the technical field of integrated circuits, and provides a multi-nuclear inductance-capacitance type voltage-controlled oscillator, which comprises at least two oscillation units which are symmetrically distributed and a digital control unit, wherein each oscillation unit comprises a switched capacitor array, and the oscillation units are in annular synchronous connection through a synchronous resistor; and the digital control unit is used for generating control signals for respectively controlling the oscillation units so as to control the switches of the switched capacitor arrays in the corresponding oscillation units through the control signals. According to the oscillator, the effect of improving the precision of the oscillator can be achieved by improving the precision of the switched capacitor array.

The invention belongs to the technical field of integrated circuits, and discloses a noise circulation voltage-controlled oscillator based on a switch coupling inductor, which comprises a switch coupling inductor module, a tuning gain module, a switch capacitor array and a noise circulation module which are connected in sequence, the switch coupling inductance module comprises a primary coil, a secondary coil, a switch tube, a first resistor, a second resistor, a first phase inverter and a second phase inverter; a drain electrode and a source electrode of the switching tube are respectively connected with two ends of the secondary coil; the input end of the first inverter receives a first control voltage, and the output end of the first inverter is connected with the input end of the second inverter, the positive electrode of the first resistor and the positive electrode of the second resistor; the output end of the second phase inverter is connected with the grid electrode of the switching tube; the negative electrode of the first resistor is connected with the drain electrode of the switch tube. The negative electrode of the second resistor is connected with the source electrode of the switch tube. The frequency working range of the voltage-controlled oscillator can be enlarged.

The application relates to a configurable time domain pipeline analog-to-digital converter, comprising: a first configurable analog-to-digital converter and a plurality of cascaded second configurable analog-to-digital converters, wherein the first configurable analog-to-digital converter serves as a first stage of the configurable time domain pipeline analog-to-digital converter, is used for converting an input voltage signal into a time signal, and transmitting the quantized time signal to the plurality of cascaded second configurable analog-to-digital converters; the second configurable analog-to-digital converter is used for amplifying and quantizing the input residual time signal stage by stage to generate corresponding digital codes and residual time signals; wherein the first configurable analog-to-digital converter and the second configurable analog-to-digital converter realize the time gain configurable function through a set of discharge and charge switch capacitor arrays. The application adopts the structure of the configurable TA and SA TDC, avoids the use of a voltage amplifier, has high linearity, meets the precision configuration requirements of the ADC, and does not need a time residual generator.

A fractional sampling phase-locked loop based on multi-stage quantization noise compensation provided by the present invention includes: a two-step quantization noise compensation circuit, which uses a combined compensation method of an N1-bit phase interpolator PI and an N2-bit digitally controlled switched capacitor array DCCA to perform two compensations on the quantization noise caused by the quantization error of the DSM in the fractional sampling phase-locked loop; wherein, the compensation of the N1-bit phase interpolator in the first-step quantization noise compensation circuit can reduce the quantization noise by 6*(N1 + 2) dB, and the compensation of the N2-bit capacitor array in the second-step quantization noise compensation circuit can further reduce the quantization noise by 6*N2 dB, greatly reducing the quantization noise and integer boundary spurs of the fractional phase-locked loop.

The invention provides a wave trap comprising three switched capacitor arrays, and relates to the field of microelectronics and solid-state electronics. The circuit is applied to the fields of microelectronics and solid-state electronics, in particular to low-noise and low-offset circuit systems in the fields. According to the switched capacitor wave trap, a large resistor and a large capacitor are not needed to adjust the wave trapping frequency, only corresponding clock signals need to be added, filtering can be achieved at the specified frequency, and static power consumption does not exist. The device has the advantages of small area, low power consumption, simple structure, high PVT resistance and the like. Simulation results show that the low-frequency gain of the wave trap is 404.497 mdB, the high-frequency notch gain of the wave trap is-91.102 dB, harmful high-frequency components at specific frequencies in signals can be well filtered out, and useful low-frequency signal components are reserved.

The invention discloses an emission driver capable of controlling the slew rate and reducing the internal pressure difference, and belongs to the technical field of signal drivers, and the emission driver comprises a level conversion circuit, a pre-driving circuit and an output circuit. The level conversion circuit generates a first data signal according to an input data signal and generates a first control signal according to an enable signal. The pre-driving circuit generates a second data signal and a second control signal according to the first data signal and the first control signal, and adjusts the level of the first output node according to the first data signal and the first control signal. The output circuit selectively pulls up the level of the second output node according to the second data signal and selectively pulls down the level of the second output node according to the second control signal so as to generate an output data signal through the second output node. The output circuit includes a switched capacitor array coupled between the first and second output nodes for adjusting a slew rate of the output data signal.

The invention provides a medium-power frequency hopping filter suitable for a broadband of 200-700MHz. The medium-power frequency hopping filter comprises a radio frequency input port, a radio frequency output port, an input matching inductor module, an output matching inductor module, a resonant inductor and a PIN diode switched capacitor array, each resonant inductor is connected with the PIN diode switched capacitor array; each PIN diode switched capacitor array is formed by connecting N groups of PIN diode switched capacitor units in parallel; each group of PIN diode switched capacitor unit is formed by connecting a PIN diode and a resonant capacitor in series; and the total capacitance of each PIN diode switch capacitor array is limited, so that the working frequency of the frequency hopping filter can be greater than or equal to 700MHz when all the PIN diodes are cut off, and the working frequency of the frequency hopping filter can be less than or equal to 200MHz when all the PIN diodes are conducted. According to the frequency hopping filter, 200-700MHz full-band coverage can be met by a single device, the size of a frequency hopping filtering system is reduced, and the weight of the frequency hopping filtering system is reduced.

The invention provides a differential analog-to-digital converter, a conversion method and electronic equipment, and the converter comprises an analog-to-digital conversion module, and lower electrode plates of sampling capacitors of a first switched capacitor array and a second switched capacitor array are respectively connected with positive and negative phase input signals through switches; an upper pole plate of the sampling capacitor is respectively connected with positive and negative phase input ends of the pre-amplifier; two ends of the first resistor and the second resistor are respectively connected with a group of in-phase input and output ends of the pre-amplifier through switches; the quantization circuit is connected with the output end of the pre-amplifier and generates a switch control signal of the switched capacitor array; the first compensation module and the second compensation module are respectively connected with a group of inverted input and output ends of the pre-amplifier, and compensate the change of an input signal coupled to the input end of the pre-amplifier. The sampling thermal noise elimination technology is adopted, the signal bandwidth limited by the saturation problem of the amplifier is increased through the first-order approximate compensation module, and the sampling thermal noise elimination circuit has the advantages of being small in sampling capacitance, low in noise, small in occupied area, large in signal bandwidth and the like.

The invention discloses a switched capacitor DAC (Digital-to-Analog Converter) circuit in a Sigma-Delta digital-to-analog converter. The switched capacitor DAC circuit comprises a signal input module, a first feedback module, a second feedback module and an integration module. The signal input module is composed of fifteen groups of switched capacitor arrays, wherein each group of switched capacitor array comprises ten switches and two capacitors; the first feedback module comprises four switches and a capacitor; the second feedback module comprises four switches and a capacitor; the integration module comprises a fully differential operational amplifier and two capacitors. According to the technical scheme, by optimizing the structure of the switched capacitor DAC, the transfer function is changed, the integral establishment speed is increased, the requirement for an operational amplifier is reduced, in addition, the influence of capacitor mismatch on the digital-to-analog converter is reduced, and design is more convenient.

Disclosed herein is a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a capacitive digital-to-analog converter (DAC) including a binary-weighted capacitor array, and a bridge capacitor separating the binary-weighted capacitor array into a first switched capacitor array connected to a first node and a second switched capacitor array connected to a second node, with a first terminal of the bridge capacitor being connected to the first node and a second terminal of the bridge capacitor being connected to the second node. A multipurpose capacitor is connected to the first node, with the multipurpose capacitor serving as both a termination capacitor for the first switched capacitor array and a shield between the first node and the bridge capacitor. A dummy is capacitor connected to the second node and serving as a shield between the second node and the bridge capacitor.

The application discloses a radio frequency quadrature switched capacitor transmitter, comprising an up-conversion circuit, a Doherty stage switched capacitor array and an output matching circuit, wherein the Doherty stage switched capacitor array comprises an amplification unit; the up-conversion circuit is used for up-converting a first baseband phase signal and a second baseband phase signal to obtain a radio frequency phase signal; the Doherty stage switched capacitor array is used for controlling the number of the opened amplification units according to the baseband amplitude signal and the radio frequency phase signal to obtain a radio frequency amplification signal, realizing power amplification and digital-to-analog conversion; and the output matching circuit is used for impedance matching the radio frequency amplification signal. The application directly modulates the carrier in amplitude by controlling the number of the opened amplification units, thereby realizing the functions of digital-to-analog conversion and power amplification, improving the system efficiency, reducing the circuit power consumption, and being widely applicable to the field of wireless communication technology.

The present invention discloses an ultra-wideband voltage-controlled oscillator circuit, which relates to the technical field of semiconductor integrated circuits and is used to solve the problems of electromagnetic interference risk, narrow frequency adjustment range and high power consumption in the existing voltage-controlled oscillator. It includes a switched capacitor array, a transformer-loaded switched inductor, a variable capacitor and cross-coupled transistors; both ends of the transformer-loaded switched inductor are respectively connected to both ends of the switched capacitor array, and the transformer-loaded switched inductor is connected in parallel with the switched capacitor array; both ends of the switched capacitor array are respectively connected to a variable capacitor, and the variable capacitor is connected to the cross-coupled transistors. By adopting an 8-shaped transformer-loaded switched inductor, the output frequency adjustment range of the single-core voltage-controlled oscillator is expanded, and the problem of serious frequency perturbation caused by electromagnetic interference to external circuit modules is solved. It has a wider frequency adjustment range compared with other single-core LC_VCOs, and has a smaller area and lower power consumption performance compared with other multi-core multi-mode LC_VCOs.

The present invention discloses an automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier, comprising a class F oscillator, a third harmonic extraction frequency multiplier, a negative peak detection circuit, a low-pass filter, a sample-and-hold circuit, a comparator, and a logic circuit. The class F oscillator obtains a periodic pseudo-square wave AC differential signal; the third harmonic extraction frequency multiplier obtains a third harmonic differential signal after fundamental frequency suppression; the negative peak detection circuit extracts the amplitude signal of the third harmonic differential signal; the low-pass filter filters the amplitude signal to a DC level; the comparator compares the amplitude signals of different frequency bands and outputs the comparison result; and the logic circuit controls the switched capacitor array in the third harmonic extraction frequency multiplier to adaptively switch the frequency band to the desired frequency band. The present invention can achieve automatic tracking of the third harmonic, solving the problems that the third harmonic frequency multiplier can only achieve excellent phase noise within a narrow frequency band and requires manual adjustment of the frequency band, which takes too much time.

The invention relates to a C-type differential series voltage-controlled oscillator, and belongs to the technical field of radio frequency integrated circuits. The voltage-controlled oscillator comprises a differential structure, a resonant network and a frequency tuning unit. According to the invention, low equivalent impedance and large oscillation current are formed at the resonant frequency by using the series resonance path under the driving of the differential active negative resistance, so that stable oscillation is realized. The series resonance structure has lower equivalent impedance at a resonance point, so that disturbance of thermal noise and noise of an active device to an oscillation phase is remarkably reduced. The multi-position switched capacitor array is realized at the same time, the switched capacitor array and the variable capacitor are adopted for frequency tuning, the effect of improving the precision of the oscillator is achieved while the wide tuning range is realized, the phenomena of multi-mode oscillation and mode competition possibly occurring in a composite resonant structure are avoided, and the oscillation mode has good uniqueness and predictability.

The invention discloses a high-speed synchronous SAR ADC switching circuit, and belongs to the technical field of integrated circuits. The circuit comprises a coarse successive approximation circuit, a fine successive approximation circuit and a clock generation circuit. Wherein the rough successive approximation comprises CDAC, CCMP and CSARLOG; the CDAC is composed of an M-bit switched capacitor array, and each bit of capacitor is split into two half capacitors by adopting a sampling mode of lower-level plate sampling and a capacitor splitting mode; according to the invention, through combination of coarse successive approximation and fine successive approximation with a weak pull-up and weak pull-down switch, a redundant bit capacitor and corresponding time sequence control, on-chip decoupling capacitance required by a high-precision high-speed synchronous SAR ADC due to the fact that Vrefp and Vrefn are packaged to a parasitic inductor can be relieved, so that the chip area is reduced and the sampling speed of the SAR ADC is improved.

The application discloses a relaxation oscillator based on a switched capacitor array and a peak feedback structure and a stabilizing method, the oscillator comprising a reference source, a switched capacitor array, a peak voltage feedback module, a comparator and a digital logic circuit, the switched capacitor array comprising two symmetric charge-discharge branches, each branch having a main charging capacitor and a tracking holding capacitor, and the peak voltage feedback module being composed of an operational amplifier, a feedback capacitor and a sampling switch. In operation, the capacitor voltage of one branch charged alternately is compared with a dynamic threshold, and the peak voltage on the tracking holding capacitor of the other branch is sampled to the feedback module at the switching moment, the comparator threshold is dynamically adjusted through the integral action, and finally the capacitor peak voltage is locked to the fixed reference voltage, so that the influence of non-ideal factors such as comparator delay on the oscillation period is systematically offset. The application also adopts a chopping comparator to eliminate the offset. The architecture significantly improves the stability of the oscillation frequency to the power supply voltage and temperature, and helps to realize low phase noise, and is suitable for high-precision on-chip clock sources.

The invention belongs to the technical field of CMOS (complementary metal oxide semiconductor) image sensors, and particularly relates to a global and rolling compatible high-frame-frequency 3D (three-dimensional) stacked image sensor and a readout method.According to the image sensor, a readout circuit and pixel layers are stacked after being designed from the structure, pixel array layers are divided into UP and DN groups, each group is independently subjected to two-way readout, and the readout circuit and the pixel layers are subjected to two-way readout; the reading circuit layer adopts the same group for the column level and adopts a mode of parallel working of a plurality of sub-column level ADCs for the column level ADC to improve the frame frequency; meanwhile, a switched capacitor array is added to an analog front-end circuit (AFE), and the inconsistency of the sequence of integral signals and reset signals output by pixels in a global shutter mode and a rolling shutter mode is adjusted, so that the requirement that a programmable gain amplifier (PGA) and an analog-to-digital converter (ADC) firstly process the reset signals and then process the integral signals is met. Compatibility of a global shutter mode and a rolling shutter mode is achieved, and the pixel structure design is more flexible.

The present invention discloses an analog-to-digital converter, comprising: a first switched capacitor array, for receiving an input signal and sampling the input signal to generate a first sampled signal; a second switched capacitor array, for sampling the input signal to generate a second sampled signal and generate a first quantization error; a third switched capacitor array, for sampling the input signal to generate a third sampled signal and generate a second quantization error; an integrator, coupled to the second switched capacitor array and the third switched capacitor array, for receiving and integrating the first quantization error and the second quantization error in a time-interleaved manner to generate an integrated quantization error; and a quantizer, coupled to the first switched capacitor array and the integrator, for quantizing the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal. The implementation of the present invention can improve the operating speed of the analog-to-digital converter.

The invention discloses a third-order noise shaping successive approximation analog-to-digital converter, and belongs to the technical field of analog-to-digital converters. Comprising four parts, namely a sampling and holding and DAC circuit, a third-order loop filter, a voltage comparator and a successive approximation logic circuit, and the sampling and holding and DAC circuit is connected with an input voltage signal and the third-order loop filter, and is controlled by the successive approximation logic circuit. The third-order loop filter performs delay integral operation on a residual signal of a previous period, introduces a plurality of time sequence control switch capacitor arrays to perform charge redistribution operation, and couples an input voltage signal and a weighted residual signal generated by the third-order loop filter to the input end of the voltage comparator through a capacitor; a noise shaping technology is introduced in the voltage comparison and conversion process, and the voltage is output to an analog-digital conversion circuit to complete the whole circuit conversion work; the device is simple in structure and has good PVT characteristics.

The invention relates to a class-C voltage-controlled oscillator with K-band low phase noise, a phase-locked loop and a chip. The K-band low-phase-noise C-type voltage-controlled oscillator comprises an oscillating circuit, a switched capacitor array circuit and a dynamic starting circuit. The oscillation circuit is used for providing oscillation signals. The switched capacitor array circuit is used for changing the self capacitance value according to the control signal group sel so as to adjust the frequency of the oscillation signal. The dynamic starting circuit is used for dynamically controlling the voltage of the cross coupling pair circuit according to the reference voltage Vref so as to adjust the amplitude of the oscillation signal. A dynamic starting circuit is introduced into the C-type inductance-capacitance voltage-controlled oscillator and is composed of an operational amplifier with extremely low static power consumption, rapid and stable oscillation starting of the oscillator can be effectively ensured through high gain of the dynamic starting circuit, and in addition, the influence of low-frequency noise of the amplifier on phase noise of the oscillator can be effectively reduced through extremely low static current. And the power consumption and the phase noise performance of the voltage-controlled oscillator are improved.

The invention relates to a voltage-controlled oscillator circuit which comprises a resonant cavity, a cross coupling negative resistance circuit, a switched capacitor array, a switched negative resistance array and a programmable biasing circuit. Wherein the cross coupling negative resistance circuit, the switched capacitor array and the switched negative resistance array are respectively connected with the resonant cavity in parallel, and the output end of the programmable bias circuit is connected with the resonant cavity; the resonant cavity is used for forming a resonant loop of the voltage-controlled oscillator circuit; the cross coupling negative resistance circuit is used for providing basic negative resistance required for maintaining oscillation for the resonant cavity; the switched capacitor array is used for adjusting the oscillation frequency of the resonant cavity by changing the equivalent capacitance value of the resonant cavity; the switch negative resistance array is used for adjusting the equivalent negative resistance value of the resonant cavity; and the programmable bias circuit is used for injecting bias current into the resonant cavity and triggering oscillation starting of the resonant cavity. According to the voltage-controlled oscillator, the problems of overlarge parasitic capacitance and limited tuning range caused by a fixed negative resistance structure in a traditional voltage-controlled oscillator are effectively solved, and the frequency coverage range of the oscillator is remarkably expanded.

The invention provides a control circuit and method based on a multiphase filter, the circuit comprises a decoder, a process calibration module and multiple stages of RC PPF circuits, and each stage of RC PPF circuit comprises a resistor array and a capacitor array; the resistor array comprises m + 1 resistors and m + 1 switches, and the capacitor array comprises n + 1 capacitors and n + 1 switches; after the working frequency band code word of the RC PPF circuit is determined, the decoder outputs a corresponding frequency band control code word; controlling m + 1 switches in the resistor array according to the frequency band control code word, and adjusting the working frequency point of each level of RC PPF circuit; when the enable signal is valid, the process calibration module outputs a corresponding process calibration code word; controlling n + 1 switches of the capacitor array according to the process calibration code word; the multi-phase filter not only can adjust the bandwidth frequency band, but also can calibrate the mismatch of the resistor and the capacitor at different process corners, thereby greatly reducing the frequency point deviation of the multi-phase filter caused by the fluctuation of the process corners.

The invention relates to an analog-to-digital conversion device and an analog-to-digital conversion method. The analog-to-digital conversion device comprises a switch, a capacitor array, a comparator and a logic control circuit. The switch is configured to sample at least one input signal according to a sampling signal. The capacitor array comprises a plurality of capacitors which are used for storing at least one input signal. The comparator is configured to generate a comparison result according to at least one input signal stored by a plurality of capacitors of the capacitor array. The logic control circuit is configured to reset the plurality of capacitors according to the conversion end signal or the sampling signal, respectively.

The invention discloses a successive approximation type analog-to-digital converter based on a dual-threshold comparator. The successive approximation type analog-to-digital converter comprises a switched capacitor DAC array, the dual-threshold comparator and an SAR logic circuit. After an input voltage passes through the switched capacitor DAC array, a differential signal is output to a differential input end of the dual-threshold comparator. The double-threshold comparator divides three comparison intervals by setting two thresholds, judges an interval corresponding to an input differential input signal, obtains an output code and sends the output code to the SAR logic circuit; and the SAR logic circuit controls the switch of the capacitor at the corresponding position in the switched capacitor DAC array to convert, so that the differential input signal jumps towards the approaching direction gradually. According to the successive approximation type analog-to-digital converter, the problem that the ADC performance is reduced due to the fact that a traditional comparator is prone to making mistakes when an input signal is close to 0V is solved, and meanwhile the same conversion precision is achieved with fewer conversion periods, lower power consumption and smaller area.