58 results about "Switched capacitor array" patented technology

The invention provides a successive approximation type single-slope analog-to-digital converter, a readout circuit and an image sensor, and the analog-to-digital converter comprises a high-order analog-to-digital conversion module which carries out the successive approximation type conversion of a pixel signal to obtain high-order conversion data and residual pixel data, and comprises a switched capacitor array, a comparator, a logic control circuit and a prediction circuit; the switched capacitor array receives pixel signals, and the upper electrode plate is connected to the comparator; the prediction circuit is connected with the switched capacitor array and controls the voltage of a lower pole plate of the switched capacitor array under the control of the logic control circuit and the comparator; and the low-order analog-to-digital conversion module is used for performing single-slope conversion on the residual pixel data to obtain low-order conversion data. The high-order conversion data of the current row of pixels is predicted through the prediction circuit according to the quantization result of the previous row of pixels, so that the quantization frequency can be effectively reduced, the power consumption can be reduced, the quantization efficiency can be improved, and the problem of how to improve the quantization efficiency of an analog-to-digital converter in the image sensor is solved.

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

The invention relates to the technical field of radio frequency integrated circuits, and discloses a dynamic bias C-type voltage-controlled oscillator based on a CMOS (complementary metal oxide semiconductor) process, the voltage-controlled oscillator adopts a C-type structure, a cross-coupled network adds two resistors and a capacitor on the basis of a cross-coupled transistor, a circuit works in the C type by adjusting bias voltage at a resistor end, and the voltage-controlled oscillator works in the C type. The C-type voltage-controlled oscillator, a tail current source, a variable capacitance network, a switched capacitor array and a fixed LC resonance network form a core structure of the C-type voltage-controlled oscillator capable of numerical control tuning and voltage-controlled tuning, so as to determine the working frequency of the circuit and realize numerical control and voltage-controlled tuning functions; and the operational amplifiers with two bandwidth modes are introduced, so that the problem of difficult oscillation starting is solved, and the oscillation starting speed and the phase noise performance in a stable state are considered at the same time.

The invention discloses a voltage-controlled oscillator with small-area and wide-band modulation capability, and particularly relates to the technical field of radio frequency integrated circuits. The voltage-controlled oscillator comprises two symmetrical voltage-controlled oscillation units; wherein each voltage-controlled oscillation unit comprises a resonance circuit; the resonance circuit comprises an LC resonance circuit and a negative resistance active circuit; the LC resonant circuit comprises a switched capacitor array; two ports of the LC resonance circuit are respectively connected to the output ends of the cross coupling MOS pair; the switched capacitor array is used for providing at least two gears of variable capacitance; the negative resistance active circuit comprises a cross coupling pair transistor and a bias current source; the mode change-over switch circuit comprises two groups of symmetrical switch MOS (Metal Oxide Semiconductor) tubes and mutual inductance transformer taps; and in each voltage-controlled oscillation unit, a tap of the resonant inductor is connected with a corresponding port of the mode switching switch MOS tube. According to the scheme, the mismatch effect caused by a small process and the stray capacitance caused by layout and wiring can be reduced as much as possible, and the chip area can be reduced while the performance is ensured, so that the tape-out cost is reduced.

The invention discloses an electric meter sampling filter chip and system integrated with a programmable anti-aliasing filter, and relates to the field of electric energy metering chips, the electric meter sampling filter chip comprises a programmable anti-aliasing filter module, a digital control and interface module and a cooperative control unit, through binary weighted control of a switched capacitor array, the cut-off frequency can be dynamically adjusted within the range of 1 kHz to 100 kHz, and the cut-off frequency can be adjusted within the range of 1 kHz to 100 kHz. Switching of a Bessel mode, a Butterworth mode and a Chebyshev mode is physically achieved by reconstructing a feedback network, a programmable AAF, an ADC, control logic and a digital interface are integrated into a single chip, and the number of external elements such as an RC network and an operational amplifier is reduced; aDC sampling data is analyzed through FFT, the signal-to-noise ratio is calculated in real time, the filter mode is automatically switched, a hardware interrupt pin triggers notification after configuration is completed, MCU polling is replaced, and frequency response is ensured to be accurate and controllable through laser trimming of a switched capacitor array.

The invention discloses a charging system and a charging method for an aircraft. The self-adaptive battery equalization module is integrated in the aircraft energy storage module and is matched with the transmitting end resonant coupling module and the energy scheduling control module which are arranged on the ground charging station, so that deep integration of an electric energy transmission link is realized through modular topology reconstruction. Wherein a multi-channel active equalization topology is embedded in the self-adaptive battery equalization module, and a dynamic charge redistribution technology based on a switched capacitor array is adopted to realize single voltage deviation control in a battery pack. According to the system, a bidirectional magnetic resonance coupling technology is added on the basis of a traditional physical contact type charging interface, so that an adaptive charging protocol can be triggered without mechanical alignment after an aircraft lands on a base, cross-air-gap energy transmission is realized through high-frequency inversion and resonance compensation, the energy conversion efficiency of the system and the reliability of the charging process are successfully and remarkably improved, and the charging efficiency is improved. And an all-weather autonomous energy supply solution is provided for mobile platforms such as an unmanned aerial vehicle cluster.

The invention relates to the technical field of integrated circuits, and provides a multi-nuclear inductance-capacitance type voltage-controlled oscillator, which comprises at least two oscillation units which are symmetrically distributed and a digital control unit, wherein each oscillation unit comprises a switched capacitor array, and the oscillation units are in annular synchronous connection through a synchronous resistor; and the digital control unit is used for generating control signals for respectively controlling the oscillation units so as to control the switches of the switched capacitor arrays in the corresponding oscillation units through the control signals. According to the oscillator, the effect of improving the precision of the oscillator can be achieved by improving the precision of the switched capacitor array.

The application relates to a configurable time domain pipeline analog-to-digital converter, comprising: a first configurable analog-to-digital converter and a plurality of cascaded second configurable analog-to-digital converters, wherein the first configurable analog-to-digital converter serves as a first stage of the configurable time domain pipeline analog-to-digital converter, is used for converting an input voltage signal into a time signal, and transmitting the quantized time signal to the plurality of cascaded second configurable analog-to-digital converters; the second configurable analog-to-digital converter is used for amplifying and quantizing the input residual time signal stage by stage to generate corresponding digital codes and residual time signals; wherein the first configurable analog-to-digital converter and the second configurable analog-to-digital converter realize the time gain configurable function through a set of discharge and charge switch capacitor arrays. The application adopts the structure of the configurable TA and SA TDC, avoids the use of a voltage amplifier, has high linearity, meets the precision configuration requirements of the ADC, and does not need a time residual generator.

A fractional sampling phase-locked loop based on multi-stage quantization noise compensation provided by the present invention includes: a two-step quantization noise compensation circuit, which uses a combined compensation method of an N1-bit phase interpolator PI and an N2-bit digitally controlled switched capacitor array DCCA to perform two compensations on the quantization noise caused by the quantization error of the DSM in the fractional sampling phase-locked loop; wherein, the compensation of the N1-bit phase interpolator in the first-step quantization noise compensation circuit can reduce the quantization noise by 6*(N1 + 2) dB, and the compensation of the N2-bit capacitor array in the second-step quantization noise compensation circuit can further reduce the quantization noise by 6*N2 dB, greatly reducing the quantization noise and integer boundary spurs of the fractional phase-locked loop.

The invention provides a wave trap comprising three switched capacitor arrays, and relates to the field of microelectronics and solid-state electronics. The circuit is applied to the fields of microelectronics and solid-state electronics, in particular to low-noise and low-offset circuit systems in the fields. According to the switched capacitor wave trap, a large resistor and a large capacitor are not needed to adjust the wave trapping frequency, only corresponding clock signals need to be added, filtering can be achieved at the specified frequency, and static power consumption does not exist. The device has the advantages of small area, low power consumption, simple structure, high PVT resistance and the like. Simulation results show that the low-frequency gain of the wave trap is 404.497 mdB, the high-frequency notch gain of the wave trap is-91.102 dB, harmful high-frequency components at specific frequencies in signals can be well filtered out, and useful low-frequency signal components are reserved.

The invention discloses an emission driver capable of controlling the slew rate and reducing the internal pressure difference, and belongs to the technical field of signal drivers, and the emission driver comprises a level conversion circuit, a pre-driving circuit and an output circuit. The level conversion circuit generates a first data signal according to an input data signal and generates a first control signal according to an enable signal. The pre-driving circuit generates a second data signal and a second control signal according to the first data signal and the first control signal, and adjusts the level of the first output node according to the first data signal and the first control signal. The output circuit selectively pulls up the level of the second output node according to the second data signal and selectively pulls down the level of the second output node according to the second control signal so as to generate an output data signal through the second output node. The output circuit includes a switched capacitor array coupled between the first and second output nodes for adjusting a slew rate of the output data signal.

The invention discloses a switched capacitor DAC (Digital-to-Analog Converter) circuit in a Sigma-Delta digital-to-analog converter. The switched capacitor DAC circuit comprises a signal input module, a first feedback module, a second feedback module and an integration module. The signal input module is composed of fifteen groups of switched capacitor arrays, wherein each group of switched capacitor array comprises ten switches and two capacitors; the first feedback module comprises four switches and a capacitor; the second feedback module comprises four switches and a capacitor; the integration module comprises a fully differential operational amplifier and two capacitors. According to the technical scheme, by optimizing the structure of the switched capacitor DAC, the transfer function is changed, the integral establishment speed is increased, the requirement for an operational amplifier is reduced, in addition, the influence of capacitor mismatch on the digital-to-analog converter is reduced, and design is more convenient.

Disclosed herein is a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a capacitive digital-to-analog converter (DAC) including a binary-weighted capacitor array, and a bridge capacitor separating the binary-weighted capacitor array into a first switched capacitor array connected to a first node and a second switched capacitor array connected to a second node, with a first terminal of the bridge capacitor being connected to the first node and a second terminal of the bridge capacitor being connected to the second node. A multipurpose capacitor is connected to the first node, with the multipurpose capacitor serving as both a termination capacitor for the first switched capacitor array and a shield between the first node and the bridge capacitor. A dummy is capacitor connected to the second node and serving as a shield between the second node and the bridge capacitor.

The application discloses a radio frequency quadrature switched capacitor transmitter, comprising an up-conversion circuit, a Doherty stage switched capacitor array and an output matching circuit, wherein the Doherty stage switched capacitor array comprises an amplification unit; the up-conversion circuit is used for up-converting a first baseband phase signal and a second baseband phase signal to obtain a radio frequency phase signal; the Doherty stage switched capacitor array is used for controlling the number of the opened amplification units according to the baseband amplitude signal and the radio frequency phase signal to obtain a radio frequency amplification signal, realizing power amplification and digital-to-analog conversion; and the output matching circuit is used for impedance matching the radio frequency amplification signal. The application directly modulates the carrier in amplitude by controlling the number of the opened amplification units, thereby realizing the functions of digital-to-analog conversion and power amplification, improving the system efficiency, reducing the circuit power consumption, and being widely applicable to the field of wireless communication technology.

The present invention discloses an ultra-wideband voltage-controlled oscillator circuit, which relates to the technical field of semiconductor integrated circuits and is used to solve the problems of electromagnetic interference risk, narrow frequency adjustment range and high power consumption in the existing voltage-controlled oscillator. It includes a switched capacitor array, a transformer-loaded switched inductor, a variable capacitor and cross-coupled transistors; both ends of the transformer-loaded switched inductor are respectively connected to both ends of the switched capacitor array, and the transformer-loaded switched inductor is connected in parallel with the switched capacitor array; both ends of the switched capacitor array are respectively connected to a variable capacitor, and the variable capacitor is connected to the cross-coupled transistors. By adopting an 8-shaped transformer-loaded switched inductor, the output frequency adjustment range of the single-core voltage-controlled oscillator is expanded, and the problem of serious frequency perturbation caused by electromagnetic interference to external circuit modules is solved. It has a wider frequency adjustment range compared with other single-core LC_VCOs, and has a smaller area and lower power consumption performance compared with other multi-core multi-mode LC_VCOs.

The present invention discloses an automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier, comprising a class F oscillator, a third harmonic extraction frequency multiplier, a negative peak detection circuit, a low-pass filter, a sample-and-hold circuit, a comparator, and a logic circuit. The class F oscillator obtains a periodic pseudo-square wave AC differential signal; the third harmonic extraction frequency multiplier obtains a third harmonic differential signal after fundamental frequency suppression; the negative peak detection circuit extracts the amplitude signal of the third harmonic differential signal; the low-pass filter filters the amplitude signal to a DC level; the comparator compares the amplitude signals of different frequency bands and outputs the comparison result; and the logic circuit controls the switched capacitor array in the third harmonic extraction frequency multiplier to adaptively switch the frequency band to the desired frequency band. The present invention can achieve automatic tracking of the third harmonic, solving the problems that the third harmonic frequency multiplier can only achieve excellent phase noise within a narrow frequency band and requires manual adjustment of the frequency band, which takes too much time.

The invention relates to a C-type differential series voltage-controlled oscillator, and belongs to the technical field of radio frequency integrated circuits. The voltage-controlled oscillator comprises a differential structure, a resonant network and a frequency tuning unit. According to the invention, low equivalent impedance and large oscillation current are formed at the resonant frequency by using the series resonance path under the driving of the differential active negative resistance, so that stable oscillation is realized. The series resonance structure has lower equivalent impedance at a resonance point, so that disturbance of thermal noise and noise of an active device to an oscillation phase is remarkably reduced. The multi-position switched capacitor array is realized at the same time, the switched capacitor array and the variable capacitor are adopted for frequency tuning, the effect of improving the precision of the oscillator is achieved while the wide tuning range is realized, the phenomena of multi-mode oscillation and mode competition possibly occurring in a composite resonant structure are avoided, and the oscillation mode has good uniqueness and predictability.

The application discloses a relaxation oscillator based on a switched capacitor array and a peak feedback structure and a stabilizing method, the oscillator comprising a reference source, a switched capacitor array, a peak voltage feedback module, a comparator and a digital logic circuit, the switched capacitor array comprising two symmetric charge-discharge branches, each branch having a main charging capacitor and a tracking holding capacitor, and the peak voltage feedback module being composed of an operational amplifier, a feedback capacitor and a sampling switch. In operation, the capacitor voltage of one branch charged alternately is compared with a dynamic threshold, and the peak voltage on the tracking holding capacitor of the other branch is sampled to the feedback module at the switching moment, the comparator threshold is dynamically adjusted through the integral action, and finally the capacitor peak voltage is locked to the fixed reference voltage, so that the influence of non-ideal factors such as comparator delay on the oscillation period is systematically offset. The application also adopts a chopping comparator to eliminate the offset. The architecture significantly improves the stability of the oscillation frequency to the power supply voltage and temperature, and helps to realize low phase noise, and is suitable for high-precision on-chip clock sources.

The invention belongs to the technical field of CMOS (complementary metal oxide semiconductor) image sensors, and particularly relates to a global and rolling compatible high-frame-frequency 3D (three-dimensional) stacked image sensor and a readout method.According to the image sensor, a readout circuit and pixel layers are stacked after being designed from the structure, pixel array layers are divided into UP and DN groups, each group is independently subjected to two-way readout, and the readout circuit and the pixel layers are subjected to two-way readout; the reading circuit layer adopts the same group for the column level and adopts a mode of parallel working of a plurality of sub-column level ADCs for the column level ADC to improve the frame frequency; meanwhile, a switched capacitor array is added to an analog front-end circuit (AFE), and the inconsistency of the sequence of integral signals and reset signals output by pixels in a global shutter mode and a rolling shutter mode is adjusted, so that the requirement that a programmable gain amplifier (PGA) and an analog-to-digital converter (ADC) firstly process the reset signals and then process the integral signals is met. Compatibility of a global shutter mode and a rolling shutter mode is achieved, and the pixel structure design is more flexible.

The invention discloses a third-order noise shaping successive approximation analog-to-digital converter, and belongs to the technical field of analog-to-digital converters. Comprising four parts, namely a sampling and holding and DAC circuit, a third-order loop filter, a voltage comparator and a successive approximation logic circuit, and the sampling and holding and DAC circuit is connected with an input voltage signal and the third-order loop filter, and is controlled by the successive approximation logic circuit. The third-order loop filter performs delay integral operation on a residual signal of a previous period, introduces a plurality of time sequence control switch capacitor arrays to perform charge redistribution operation, and couples an input voltage signal and a weighted residual signal generated by the third-order loop filter to the input end of the voltage comparator through a capacitor; a noise shaping technology is introduced in the voltage comparison and conversion process, and the voltage is output to an analog-digital conversion circuit to complete the whole circuit conversion work; the device is simple in structure and has good PVT characteristics.

The invention relates to a class-C voltage-controlled oscillator with K-band low phase noise, a phase-locked loop and a chip. The K-band low-phase-noise C-type voltage-controlled oscillator comprises an oscillating circuit, a switched capacitor array circuit and a dynamic starting circuit. The oscillation circuit is used for providing oscillation signals. The switched capacitor array circuit is used for changing the self capacitance value according to the control signal group sel so as to adjust the frequency of the oscillation signal. The dynamic starting circuit is used for dynamically controlling the voltage of the cross coupling pair circuit according to the reference voltage Vref so as to adjust the amplitude of the oscillation signal. A dynamic starting circuit is introduced into the C-type inductance-capacitance voltage-controlled oscillator and is composed of an operational amplifier with extremely low static power consumption, rapid and stable oscillation starting of the oscillator can be effectively ensured through high gain of the dynamic starting circuit, and in addition, the influence of low-frequency noise of the amplifier on phase noise of the oscillator can be effectively reduced through extremely low static current. And the power consumption and the phase noise performance of the voltage-controlled oscillator are improved.

The invention relates to a voltage-controlled oscillator circuit which comprises a resonant cavity, a cross coupling negative resistance circuit, a switched capacitor array, a switched negative resistance array and a programmable biasing circuit. Wherein the cross coupling negative resistance circuit, the switched capacitor array and the switched negative resistance array are respectively connected with the resonant cavity in parallel, and the output end of the programmable bias circuit is connected with the resonant cavity; the resonant cavity is used for forming a resonant loop of the voltage-controlled oscillator circuit; the cross coupling negative resistance circuit is used for providing basic negative resistance required for maintaining oscillation for the resonant cavity; the switched capacitor array is used for adjusting the oscillation frequency of the resonant cavity by changing the equivalent capacitance value of the resonant cavity; the switch negative resistance array is used for adjusting the equivalent negative resistance value of the resonant cavity; and the programmable bias circuit is used for injecting bias current into the resonant cavity and triggering oscillation starting of the resonant cavity. According to the voltage-controlled oscillator, the problems of overlarge parasitic capacitance and limited tuning range caused by a fixed negative resistance structure in a traditional voltage-controlled oscillator are effectively solved, and the frequency coverage range of the oscillator is remarkably expanded.

The invention relates to an analog-to-digital conversion device and an analog-to-digital conversion method. The analog-to-digital conversion device comprises a switch, a capacitor array, a comparator and a logic control circuit. The switch is configured to sample at least one input signal according to a sampling signal. The capacitor array comprises a plurality of capacitors which are used for storing at least one input signal. The comparator is configured to generate a comparison result according to at least one input signal stored by a plurality of capacitors of the capacitor array. The logic control circuit is configured to reset the plurality of capacitors according to the conversion end signal or the sampling signal, respectively.

The application discloses a switch capacitor circuit based on charge transfer, a sampling control end of a sampling clock generation circuit is electrically connected with a sampling switch control end of a sampling switch capacitor array; a control end of a transfer driving array is connected with a driving control circuit, and the driving control circuit controls on-off of each switch of the transfer driving array; an output end of the transfer driving array is electrically connected with a storage switch capacitor array, cyclic sampling is continuously carried out through the sampling clock generation circuit and the sampling switch capacitor array, and the voltage value sampled cyclically is transferred to the storage switch capacitor array through the transfer driving array; an output end of the storage switch capacitor array is electrically connected with a quantization circuit; a quantization readout control circuit receives readout data of the quantization circuit, and outputs the data to an off-chip through serial output. The circuit can avoid the contradiction between the sampling depth and the analog bandwidth, significantly improve the bandwidth of an analog bus, and increase the sampling depth of the switch capacitor array.

The present application relates to the technical field of radio frequency power supply, in particular to a power supply system and a matching method suitable for multi-stage pulse, the power supply system comprises: a radio frequency power supply, outputting multi-stage pulse; a matching network, comprising a mechanical variable capacitor and a switch capacitor array, connected between the radio frequency power supply and a load, the present application matches the multi-stage pulse by mixing the impedance network and the frequency of the radio frequency power supply, so as to achieve the purpose of quickly matching the multi-stage pulse, meanwhile, by using the idea of segmented matching, the first stage pulse of the multi-stage pulse is matched in impedance by the mechanical variable capacitor and the frequency of the radio frequency power supply, in the subsequent pulse, the capacitance value of the mechanical variable capacitor is kept unchanged, and the impedance is matched by the switch capacitor array and the frequency of the radio frequency power supply, so as to realize the fast and accurate impedance matching in the complex multi-stage pulse process, and ensure that the radio frequency energy is transmitted to the load efficiently and stably.

The invention discloses a self-trimming ring oscillator for a phase-locked loop, which belongs to the field of CMOS (complementary metal oxide semiconductor) phase-locked loops and comprises a control voltage sampling unit, a gear counter and a multi-gear differential pair. The control voltage sampling unit needs oscillator control voltage generated by the phase-locked loop as input and is used for realizing an automatic frequency gear switching function; the gear counter is connected with the control voltage sampling unit and is used for recording a current frequency gear and generating a gear control signal; the multi-gear differential pair is connected with the gear counter, and the multi-gear differential pair needs an oscillator control voltage of the phase-locked loop as input, receives a gear control signal sent by the gear counter and is used for generating clock signals of various frequencies. According to the multi-gear differential pair, the frequency modulation range is greatly expanded in a mode of adding a switchable capacitor array; by sampling the control voltage and counting the current frequency gear, the automatic adjustment of the frequency gear by the difference is realized by means of the feedback logic of the phase-locked loop.

The invention discloses a high-speed synchronous SAR ADC switch circuit, belonging to the technical field of integrated circuits; the invention comprises a coarse successive approximation, a fine successive approximation and a clock generation circuit; the coarse successive approximation comprises CDAC, CCMP and CSAR_LOG; the CDAC is composed of an M-bit switch capacitor array, adopts a sampling method of lower-level board sampling and uses a split capacitor method to split each bit capacitor into two half capacitors; the invention combines coarse successive approximation and fine successive approximation with weak pull-up and weak pull-down switches, redundant bit capacitors and corresponding timing control, thereby alleviating the on-chip decoupling capacitor required by a high-precision, high-speed synchronous SAR ADC due to Vrefp and Vrefn being packaged to parasitic inductance, thereby reducing the chip area and improving the sampling speed of the SAR ADC.

An analog or mixed-signal ASIC implements and trains a neural-network model entirely in the analog domain. Weights and activations are encoded as pulse frequencies. Forward propagation is performed by analog multipliers, while reverse-propagation error signals are conveyed through reverse directional nodes and error neurons that inject pulse-based corrections upstream, eliminating digital gradient arithmetic. Variable analog weight-storage elements—including field-effect transistors, switched-capacitor arrays, and phase-change memory—are updated in real time. Additional features include flash-ADC calibration with temperature compensation, auto-associative pattern completion, stochastic-computing variants, dynamic gate-array reconfiguration, and optional wireless telemetry. Continuous on-edge learning is achieved at ultra-low power for sensor-rich edge-AI applications.

The present invention discloses an FMCW phase-locked loop (PLL) system based on a two-point modulation multi-subband voltage-controlled oscillator (VCO). The system includes a phase frequency detector (PFD), a charge pump, a loop filter, a VCO, a digital-to-analog conversion (DAC) module, an injection-locked frequency divider, a frequency divider module, a multi-mode frequency divider, a ΔΣ modulator, an FMCW multi-function module, a sub-band compensation module, a system linearity calibration module, and a switched capacitor array. The system uses multi-subband oscillator (MSO) technology to broaden the frequency bandwidth of the frequency source; employs two-point modulation technology to mitigate the loop bandwidth of the PLL loop, ensuring a stable fast chirp state; combines a D / A conversion module with a multi-subband oscillator to achieve ultra-low frequency resolution and reduce RMS frequency error; employs frequency compensation technology to eliminate the impact of the multi-subband oscillator on fast chirps; and employs system linearity calibration technology to eliminate the impact of nonlinearities in the oscillator and D / A conversion module on the PLL.

The invention relates to a four-phase high-robustness oscillator for high-speed radio frequency communication. The four-phase high-robustness oscillator comprises two sub-circuits with the same structure, each sub-circuit comprises a switched capacitor array and two resonance units with the same structure; the input end of each resonance unit in one sub-circuit is connected with the output ends of the two resonance units in the other sub-circuit; each resonance unit comprises a protection capacitor subunit, an amplitude adjustment subunit, an active core subunit and a series resonant cavity subunit; the amplitude adjusting subunit and the bias voltage are used for reducing the input voltage amplitude of the control end of the active core subunit. The input voltage amplitude of the control end of the active core subunit is reduced through the amplitude adjusting subunit and the bias voltage, so that the voltage difference of each end of an active device in the active core subunit is lower than the power supply voltage, the large voltage amplitude is controlled in a passive device, and the reliability is greatly improved while low phase noise is realized.