33 results about "Switched capacitor array" patented technology

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

The invention relates to the technical field of radio frequency integrated circuits, and discloses a dynamic bias C-type voltage-controlled oscillator based on a CMOS (complementary metal oxide semiconductor) process, the voltage-controlled oscillator adopts a C-type structure, a cross-coupled network adds two resistors and a capacitor on the basis of a cross-coupled transistor, a circuit works in the C type by adjusting bias voltage at a resistor end, and the voltage-controlled oscillator works in the C type. The C-type voltage-controlled oscillator, a tail current source, a variable capacitance network, a switched capacitor array and a fixed LC resonance network form a core structure of the C-type voltage-controlled oscillator capable of numerical control tuning and voltage-controlled tuning, so as to determine the working frequency of the circuit and realize numerical control and voltage-controlled tuning functions; and the operational amplifiers with two bandwidth modes are introduced, so that the problem of difficult oscillation starting is solved, and the oscillation starting speed and the phase noise performance in a stable state are considered at the same time.

The application relates to a configurable time domain pipeline analog-to-digital converter, comprising: a first configurable analog-to-digital converter and a plurality of cascaded second configurable analog-to-digital converters, wherein the first configurable analog-to-digital converter serves as a first stage of the configurable time domain pipeline analog-to-digital converter, is used for converting an input voltage signal into a time signal, and transmitting the quantized time signal to the plurality of cascaded second configurable analog-to-digital converters; the second configurable analog-to-digital converter is used for amplifying and quantizing the input residual time signal stage by stage to generate corresponding digital codes and residual time signals; wherein the first configurable analog-to-digital converter and the second configurable analog-to-digital converter realize the time gain configurable function through a set of discharge and charge switch capacitor arrays. The application adopts the structure of the configurable TA and SA TDC, avoids the use of a voltage amplifier, has high linearity, meets the precision configuration requirements of the ADC, and does not need a time residual generator.

The invention discloses an emission driver capable of controlling the slew rate and reducing the internal pressure difference, and belongs to the technical field of signal drivers, and the emission driver comprises a level conversion circuit, a pre-driving circuit and an output circuit. The level conversion circuit generates a first data signal according to an input data signal and generates a first control signal according to an enable signal. The pre-driving circuit generates a second data signal and a second control signal according to the first data signal and the first control signal, and adjusts the level of the first output node according to the first data signal and the first control signal. The output circuit selectively pulls up the level of the second output node according to the second data signal and selectively pulls down the level of the second output node according to the second control signal so as to generate an output data signal through the second output node. The output circuit includes a switched capacitor array coupled between the first and second output nodes for adjusting a slew rate of the output data signal.

The invention discloses a switched capacitor DAC (Digital-to-Analog Converter) circuit in a Sigma-Delta digital-to-analog converter. The switched capacitor DAC circuit comprises a signal input module, a first feedback module, a second feedback module and an integration module. The signal input module is composed of fifteen groups of switched capacitor arrays, wherein each group of switched capacitor array comprises ten switches and two capacitors; the first feedback module comprises four switches and a capacitor; the second feedback module comprises four switches and a capacitor; the integration module comprises a fully differential operational amplifier and two capacitors. According to the technical scheme, by optimizing the structure of the switched capacitor DAC, the transfer function is changed, the integral establishment speed is increased, the requirement for an operational amplifier is reduced, in addition, the influence of capacitor mismatch on the digital-to-analog converter is reduced, and design is more convenient.

Disclosed herein is a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a capacitive digital-to-analog converter (DAC) including a binary-weighted capacitor array, and a bridge capacitor separating the binary-weighted capacitor array into a first switched capacitor array connected to a first node and a second switched capacitor array connected to a second node, with a first terminal of the bridge capacitor being connected to the first node and a second terminal of the bridge capacitor being connected to the second node. A multipurpose capacitor is connected to the first node, with the multipurpose capacitor serving as both a termination capacitor for the first switched capacitor array and a shield between the first node and the bridge capacitor. A dummy is capacitor connected to the second node and serving as a shield between the second node and the bridge capacitor.

The invention relates to a C-type differential series voltage-controlled oscillator, and belongs to the technical field of radio frequency integrated circuits. The voltage-controlled oscillator comprises a differential structure, a resonant network and a frequency tuning unit. According to the invention, low equivalent impedance and large oscillation current are formed at the resonant frequency by using the series resonance path under the driving of the differential active negative resistance, so that stable oscillation is realized. The series resonance structure has lower equivalent impedance at a resonance point, so that disturbance of thermal noise and noise of an active device to an oscillation phase is remarkably reduced. The multi-position switched capacitor array is realized at the same time, the switched capacitor array and the variable capacitor are adopted for frequency tuning, the effect of improving the precision of the oscillator is achieved while the wide tuning range is realized, the phenomena of multi-mode oscillation and mode competition possibly occurring in a composite resonant structure are avoided, and the oscillation mode has good uniqueness and predictability.

The application discloses a relaxation oscillator based on a switched capacitor array and a peak feedback structure and a stabilizing method, the oscillator comprising a reference source, a switched capacitor array, a peak voltage feedback module, a comparator and a digital logic circuit, the switched capacitor array comprising two symmetric charge-discharge branches, each branch having a main charging capacitor and a tracking holding capacitor, and the peak voltage feedback module being composed of an operational amplifier, a feedback capacitor and a sampling switch. In operation, the capacitor voltage of one branch charged alternately is compared with a dynamic threshold, and the peak voltage on the tracking holding capacitor of the other branch is sampled to the feedback module at the switching moment, the comparator threshold is dynamically adjusted through the integral action, and finally the capacitor peak voltage is locked to the fixed reference voltage, so that the influence of non-ideal factors such as comparator delay on the oscillation period is systematically offset. The application also adopts a chopping comparator to eliminate the offset. The architecture significantly improves the stability of the oscillation frequency to the power supply voltage and temperature, and helps to realize low phase noise, and is suitable for high-precision on-chip clock sources.

The invention belongs to the technical field of CMOS (complementary metal oxide semiconductor) image sensors, and particularly relates to a global and rolling compatible high-frame-frequency 3D (three-dimensional) stacked image sensor and a readout method.According to the image sensor, a readout circuit and pixel layers are stacked after being designed from the structure, pixel array layers are divided into UP and DN groups, each group is independently subjected to two-way readout, and the readout circuit and the pixel layers are subjected to two-way readout; the reading circuit layer adopts the same group for the column level and adopts a mode of parallel working of a plurality of sub-column level ADCs for the column level ADC to improve the frame frequency; meanwhile, a switched capacitor array is added to an analog front-end circuit (AFE), and the inconsistency of the sequence of integral signals and reset signals output by pixels in a global shutter mode and a rolling shutter mode is adjusted, so that the requirement that a programmable gain amplifier (PGA) and an analog-to-digital converter (ADC) firstly process the reset signals and then process the integral signals is met. Compatibility of a global shutter mode and a rolling shutter mode is achieved, and the pixel structure design is more flexible.

The invention discloses a third-order noise shaping successive approximation analog-to-digital converter, and belongs to the technical field of analog-to-digital converters. Comprising four parts, namely a sampling and holding and DAC circuit, a third-order loop filter, a voltage comparator and a successive approximation logic circuit, and the sampling and holding and DAC circuit is connected with an input voltage signal and the third-order loop filter, and is controlled by the successive approximation logic circuit. The third-order loop filter performs delay integral operation on a residual signal of a previous period, introduces a plurality of time sequence control switch capacitor arrays to perform charge redistribution operation, and couples an input voltage signal and a weighted residual signal generated by the third-order loop filter to the input end of the voltage comparator through a capacitor; a noise shaping technology is introduced in the voltage comparison and conversion process, and the voltage is output to an analog-digital conversion circuit to complete the whole circuit conversion work; the device is simple in structure and has good PVT characteristics.

The invention relates to a voltage-controlled oscillator circuit which comprises a resonant cavity, a cross coupling negative resistance circuit, a switched capacitor array, a switched negative resistance array and a programmable biasing circuit. Wherein the cross coupling negative resistance circuit, the switched capacitor array and the switched negative resistance array are respectively connected with the resonant cavity in parallel, and the output end of the programmable bias circuit is connected with the resonant cavity; the resonant cavity is used for forming a resonant loop of the voltage-controlled oscillator circuit; the cross coupling negative resistance circuit is used for providing basic negative resistance required for maintaining oscillation for the resonant cavity; the switched capacitor array is used for adjusting the oscillation frequency of the resonant cavity by changing the equivalent capacitance value of the resonant cavity; the switch negative resistance array is used for adjusting the equivalent negative resistance value of the resonant cavity; and the programmable bias circuit is used for injecting bias current into the resonant cavity and triggering oscillation starting of the resonant cavity. According to the voltage-controlled oscillator, the problems of overlarge parasitic capacitance and limited tuning range caused by a fixed negative resistance structure in a traditional voltage-controlled oscillator are effectively solved, and the frequency coverage range of the oscillator is remarkably expanded.

The invention relates to an analog-to-digital conversion device and an analog-to-digital conversion method. The analog-to-digital conversion device comprises a switch, a capacitor array, a comparator and a logic control circuit. The switch is configured to sample at least one input signal according to a sampling signal. The capacitor array comprises a plurality of capacitors which are used for storing at least one input signal. The comparator is configured to generate a comparison result according to at least one input signal stored by a plurality of capacitors of the capacitor array. The logic control circuit is configured to reset the plurality of capacitors according to the conversion end signal or the sampling signal, respectively.

The application discloses a switch capacitor circuit based on charge transfer, a sampling control end of a sampling clock generation circuit is electrically connected with a sampling switch control end of a sampling switch capacitor array; a control end of a transfer driving array is connected with a driving control circuit, and the driving control circuit controls on-off of each switch of the transfer driving array; an output end of the transfer driving array is electrically connected with a storage switch capacitor array, cyclic sampling is continuously carried out through the sampling clock generation circuit and the sampling switch capacitor array, and the voltage value sampled cyclically is transferred to the storage switch capacitor array through the transfer driving array; an output end of the storage switch capacitor array is electrically connected with a quantization circuit; a quantization readout control circuit receives readout data of the quantization circuit, and outputs the data to an off-chip through serial output. The circuit can avoid the contradiction between the sampling depth and the analog bandwidth, significantly improve the bandwidth of an analog bus, and increase the sampling depth of the switch capacitor array.

The present application relates to the technical field of radio frequency power supply, in particular to a power supply system and a matching method suitable for multi-stage pulse, the power supply system comprises: a radio frequency power supply, outputting multi-stage pulse; a matching network, comprising a mechanical variable capacitor and a switch capacitor array, connected between the radio frequency power supply and a load, the present application matches the multi-stage pulse by mixing the impedance network and the frequency of the radio frequency power supply, so as to achieve the purpose of quickly matching the multi-stage pulse, meanwhile, by using the idea of segmented matching, the first stage pulse of the multi-stage pulse is matched in impedance by the mechanical variable capacitor and the frequency of the radio frequency power supply, in the subsequent pulse, the capacitance value of the mechanical variable capacitor is kept unchanged, and the impedance is matched by the switch capacitor array and the frequency of the radio frequency power supply, so as to realize the fast and accurate impedance matching in the complex multi-stage pulse process, and ensure that the radio frequency energy is transmitted to the load efficiently and stably.

The invention discloses a self-trimming ring oscillator for a phase-locked loop, which belongs to the field of CMOS (complementary metal oxide semiconductor) phase-locked loops and comprises a control voltage sampling unit, a gear counter and a multi-gear differential pair. The control voltage sampling unit needs oscillator control voltage generated by the phase-locked loop as input and is used for realizing an automatic frequency gear switching function; the gear counter is connected with the control voltage sampling unit and is used for recording a current frequency gear and generating a gear control signal; the multi-gear differential pair is connected with the gear counter, and the multi-gear differential pair needs an oscillator control voltage of the phase-locked loop as input, receives a gear control signal sent by the gear counter and is used for generating clock signals of various frequencies. According to the multi-gear differential pair, the frequency modulation range is greatly expanded in a mode of adding a switchable capacitor array; by sampling the control voltage and counting the current frequency gear, the automatic adjustment of the frequency gear by the difference is realized by means of the feedback logic of the phase-locked loop.

The application relates to a K-band low-phase-noise class-C voltage-controlled oscillator, a phase-locked loop and a chip. The K-band low-phase-noise class-C voltage-controlled oscillator comprises an oscillation circuit, a switched-capacitor array circuit and a dynamic starting circuit. The oscillation circuit is used for providing an oscillation signal. The switched-capacitor array circuit is used for changing a self-capacitance value according to a control signal group sel to adjust the frequency of the oscillation signal. The dynamic starting circuit is used for dynamically controlling the voltage of a cross-coupled pair circuit according to a reference voltage V ref to adjust the amplitude of the oscillation signal. The application introduces a dynamic starting circuit in the class-C inductance-capacitance voltage-controlled oscillator, which is composed of an operational amplifier with extremely low static power consumption. The high gain of the operational amplifier can effectively ensure the rapid stable starting of the oscillator. In addition, the extremely low static current can effectively reduce the influence of the low-frequency noise of the amplifier on the phase noise of the oscillator, and the power consumption and phase noise performance of the voltage-controlled oscillator are improved.

The invention discloses an alternating current-direct current converter which performs preliminary voltage division on input voltage through a first voltage division capacitor and a second voltage division capacitor, and controls opening and closing of a first bus switch and a second bus switch according to the input voltage through a logic control module. The logic control module controls the connection state of the switched capacitor array according to the input voltage, the input voltage is converted into direct-current voltage through the rectifier, and the direct-current voltage is output through the output capacitor. According to the invention, by introducing the active rectifier and adopting a dynamic capacitance distribution architecture, uniform distribution of rectifier conduction time in a full period is realized, the conversion efficiency of converting AC commercial power input into low-voltage DC output is improved, and output ripples can be reduced while stable operation under various commercial power standards can be realized.

The invention relates to a broadband low-phase-noise voltage-controlled oscillator based on a CMOS (Complementary Metal Oxide Semiconductor) process, aiming at solving the problems that the wide tuning and low-phase-noise of the traditional Class-F VCO are difficult to be compatible, the tuning range is narrow and the like. The core architecture comprises four parallel VCO (Voltage Controlled Oscillator) units, a matched buffer and a two-stage alternative selector, each VCO unit is integrated with an exclusive optimized transformer, a multi-bit digital controlled switched capacitor array and a parallel resistor array, and a unilateral tuning design is adopted. The switched capacitor array comprises a coarse tuning unit and a fine tuning unit, and is matched with the overlapping margin of each VCO sub-band to realize seamless connection; the transformer adopts a composite regular octagonal structure, so that the quality factor and the coupling coefficient are improved; the buffer suppresses signal crosstalk, and the selector ensures rapid low-loss switching. According to the scheme, ultra-wide continuous tuning is achieved, the full-band phase noise optimally reaches-131.666 dBc / Hz and 1 MHz, the frequency stepping precision and the signal stability are both considered, and the antenna is suitable for high-frequency and high-requirement scenes such as 5G millimeter wave communication and radar detection.

The invention relates to the technical field of power supply systems, in particular to a charger power factor increasing method based on dynamic impedance matching, and the method comprises the steps: determining a resistance component and a reactance component of input impedance based on a voltage signal and a current signal of a transmitting side input end of a charger; based on the resistance component and the reactance component, constructing an impedance detuning compensation factor representing the degree and direction of the charger deviating from the resonance state; based on the impedance detuning compensation factor and a reference compensation capacitance value of the charger in a nominal resonance state, determining a target capacitance adjustment amount of the charger; and updating the control state of the switched capacitor array by using the target capacitance adjusting quantity so as to adjust the capacitance value of the impedance matching network, so that the input impedance of the charger approaches pure resistance. According to the technical scheme, the power factor and the energy conversion efficiency of the charger are remarkably improved.

The application relates to a sigma-delta modulator and method based on switch capacitor control. The application comprises an input voltage, two-stage operational amplifiers ATO1 and ATO2, a switch capacitor array and a quantizer, the input voltage is sequentially connected to the quantizer through the operational amplifier ATO1 and the operational amplifier ATO2, and the switch capacitor array is connected to the input voltage and the operational amplifier ATO1 respectively. The application introduces a new reference voltage in the modulator structure of a temperature sensor, improves the precision of the modulator output, adopts a simple timing control to realize common-mode feedback by using a small unit capacitor with the same area, reduces the capacitor area and simplifies the control timing.

This invention discloses a switched-capacitor circuit based on charge transfer. The sampling control terminal of the sampling clock generation circuit is electrically connected to the sampling switch control terminal of the sampling switched-capacitor array. The control terminal of the transfer drive array is connected to the drive control circuit, which controls the on / off state of each switch in the transfer drive array. The output terminal of the transfer drive array is electrically connected to the storage switched-capacitor array. Continuous cyclic sampling is performed through the sampling clock generation circuit and the sampling switched-capacitor array, and the cyclically sampled voltage values ​​are transferred to the storage switched-capacitor array through the transfer drive array. The output terminal of the storage switched-capacitor array is electrically connected to the quantization circuit. The quantization readout control circuit receives the readout data from the quantization circuit and outputs the data serially to an external device. This circuit can circumvent the contradiction between sampling depth and analog bandwidth, significantly improve the bandwidth of the analog bus, and increase the sampling depth of the switched-capacitor array.

The invention discloses an analog-to-digital conversion circuit supporting capacitor mismatch calibration and a chip. The analog-to-digital conversion circuit comprises an operational amplifier compensation circuit, a comparator, an SAR logic module, a first switched capacitor array and a second switched capacitor array. The operational amplifier compensation circuit is used for configuring compensation voltage in a port short-circuit mode and compensating offset voltage of an internal operational amplifier by using the compensation voltage; two output ends of the operational amplifier compensation circuit are respectively connected with two input ends of the comparator; two input ends of the comparator are respectively connected with the first switched capacitor array and the second switched capacitor array; and the SAR logic module is used for respectively adjusting an adjustable capacitor arranged in the first switched capacitor array and an adjustable capacitor arranged in the second switched capacitor array according to a comparison result output by the comparator after the operational amplifier compensation circuit completes offset voltage compensation. And mismatch calibration is carried out on the capacitor in the first switched capacitor array and the capacitor in the second switched capacitor array.

The invention relates to the technical field of radio frequency power supplies, in particular to a power supply system adaptive to multistage pulses and a matching method. The power supply system comprises a radio frequency power supply which outputs multi-stage pulses; and the matching network comprises a mechanical variable capacitor and a switched capacitor array and is connected between the radio frequency power supply and the load. According to the invention, the multi-stage pulse is matched through the mixed impedance network and the frequency of the radio frequency power supply, so that the purpose of quickly matching the multi-stage pulse is achieved. Meanwhile, by means of the thought of segmented matching, impedance matching is carried out on the first-stage pulse of the multi-stage pulse through the mechanical variable capacitor and the radio frequency power source frequency, in the subsequent pulse, the capacitance value of the mechanical variable capacitor is kept unchanged, impedance matching is carried out through the switched capacitor array and the radio frequency power source frequency, and the impedance matching is carried out; the impedance matching circuit is used for realizing rapid and accurate impedance matching in a complex multi-stage pulse process, and ensuring that radio frequency energy is efficiently and stably transmitted to a load.

The application discloses an electric meter sampling filter chip and system integrated with a programmable anti-aliasing filter, relates to the field of electric energy metering chips, and comprises a programmable anti-aliasing filter module, a digital control and interface module and a cooperative control unit. Through binary weighting control of a switch capacitor array, the cutoff frequency can be dynamically adjusted within the range of 1 kHz-100 kHz. The switching of three modes of Bessel, Butterworth and Chebyshev is physically realized through a reconstruction feedback network. The programmable AAF, ADC, control logic and digital interface are integrated on a single chip, thereby reducing the number of external components such as RC networks and operational amplifiers. Through FFT analysis of ADC sampling data, the signal-to-noise ratio is calculated in real time, and the filter mode is automatically switched. After configuration is completed, a hardware interrupt pin is triggered to replace MCU polling. The frequency response of the switch capacitor array is accurately controllable through laser trimming.

The invention discloses a high-frequency broadband low-noise amplifier of a low-voltage CMOS (complementary metal oxide semiconductor) process, and belongs to the field of radio frequency integrated circuits. The amplifier adopts a four-stage cascade structure and comprises two stages of single-ended common-source amplifiers and two stages of differential common-source amplifiers. An adjustable matching network is arranged between the single-end amplification stage and the differential amplification stage, and broadband impedance matching is achieved through a multi-tap inductor and a switched capacitor array. The single-ended amplifier adopts a transistor structure with an MOM capacitor array and an isolating ring to reduce noise. And the differential amplifier adopts an active MOS (Metal Oxide Semiconductor) tube neutralizing capacitor and a source electrode adjustable inductor, so that the bandwidth is effectively expanded and the common-mode interference is inhibited. According to the invention, high gain, low noise and broadband characteristics are realized under low power supply voltage, and the antenna is suitable for millimeter wave communication and a radar receiving front end.

The invention discloses a switched capacitor power amplifier exceeding track signal output, and belongs to the technical field of digital power amplifiers, the switched capacitor power amplifier comprises a switched capacitor array, the switched capacitor array comprises an SCPA basic structure, the SCPA basic structure adopts a pair of differential switches, the switches are directly switched between power supply voltage VDD and ground GND respectively, and the switched capacitor array is connected with the SCPA basic structure. The switched capacitor array further comprises a resonant structure, the resonant structure is located between the SCPA basic structure and power supply voltage VDD and GND, and the resonant structure and the SCPA basic structure form a resonant unit. The resonance unit enables the signal voltage of the power supply voltage node VD and the grounding voltage node VS to generate voltage fluctuation, and when the switch directly switches between the power supply voltage node VD and the grounding voltage node VS, the finally output signal voltage exceeds the amplitude limit of VDD-GND. According to the invention, the problem that the output power is limited because the voltage amplitude of the output signal in the prior art is always from VDD to GND and cannot exceed the range is solved.

The invention discloses an inter-channel interference correction method and device for an interleaved analog-to-digital converter, and the method comprises a test stage and a working stage: the test stage comprises the steps: sequentially selecting sub-ADC channels as interference source channels, and traversing the configuration combination of a switched capacitor array; storing the interference value and a mapping relation between the corresponding interference source channel, the configuration combination and the interfered channel; the working stage comprises the following steps: on the basis of the mapping relationship, querying interference values generated by all other sub-ADC channels except the sub-ADC channel itself in the overlapping channel set to an interfered channel under the current configuration, and superposing all the queried interference values to obtain a total interference value; and deducting the total interference value from the original conversion result of the interfered channel to obtain a corrected conversion result of the interfered channel. According to the invention, errors caused by charge transfer due to overlapping of sampling phases between channels can be corrected, so that the conversion precision of the interleaved analog-to-digital converter is improved.

This invention discloses a dual-chain switched capacitor array and its control method, including a short-chain sampling clock generation circuit, a long-chain sampling clock generation circuit, a sampling control circuit, a short-chain switched capacitor array, a long-chain switched capacitor array, and a readout control circuit. The clock terminals of the short-chain and long-chain sampling clock generation circuits are electrically connected to the input clock terminals of the sampling control circuit. The sampling control terminal of the sampling control circuit is electrically connected to the sampling switch control terminal of the short-chain and long-chain switched capacitor arrays, and the readout control terminal of the sampling control circuit is electrically connected to the readout switch control terminal of the short-chain and long-chain switched capacitor arrays. The output terminals of the short-chain and long-chain switched capacitor arrays are electrically connected to the readout control circuit. The readout control circuit receives the readout data from the short-chain and long-chain switched capacitor arrays and serially transmits the data off-chip. This array can sample fast leading-edge waveforms and slow trailing-edge waveforms at different sampling rates, improving measurement accuracy.

A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) comprises: a plurality of switch capacitor arrays, used to sample an analog input signal; a noise shaping circuit including a fourth-order CIFF (Cascade of Integrators with Feed-Forward) loop filter having two second-order cascaded CIFF loop filters, in the fourth-order CIFF loop filter, a first-order extraction capacitor and a second-order extraction capacitor sharing a first amplifier, and a third-order extraction capacitor and a fourth-order extraction capacitor sharing a second amplifier; a comparator for comparing a plurality of output signals from the noise shaping circuit to produce a plurality of comparison results; and a logic circuit for generating a digital output signal and controlling the switch capacitor arrays based on comparison results from the comparator.

The invention discloses a continuous tuning broadband VCO, which belongs to the technical field of radio frequency integrated circuits, and comprises a resonant network used for adjusting resonant frequency; and the N-type negative resistance pair and the P-type negative resistance pair are used for generating negative impedance to compensate resonance loss of the resonance network and keep a resonance state. By adopting a simple structure of the resonant network and the negative resistance pair, the broadband tuning can be realized without a switched capacitor array and a plurality of LC resonant cavity cores, the equivalent impedance of the resonant network is controlled by using the bias voltage and the control voltage, the problems of tuning dead zone, Q value degradation and the like are avoided, the continuous tuning is realized in the frequency range of 10GHz-20GHz, and in addition, the continuous tuning is realized in the frequency range of 10GHz-20GHz. A switching device and a plurality of LC resonant cavities are abandoned, the high Q value characteristic of the LC resonant cavities is kept all the time, wide tuning is achieved with a small area and low power consumption, and meanwhile excellent phase noise performance is obtained.