145results about How to "Prevent lockout" patented technology

A method and apparatus for protection against electrostatic discharge (ESD) with improved latch-up robustness featuring a silicide blocked p-type field effect transistor is disclosed. The transistor has a snapback voltage that is less than the breakdown voltage of its gate oxide. The transistor is part of an integrated circuit and coupled to an I/O pad having no n-diffusions connected directly to it. A given integrated circuit may employ one or more the transistors configured in accordance with the invention that are associated with one or more I/O pads within the integrated circuit.

The invention provides a method for defending periodic commutation failures of a one-tower double-circuit DC transmission system. The method comprises the following steps that (I) an inverter station determines a descent rate of voltage amplitude values according to instantaneous values of grid-side three-phase AC voltages; (II) changes of grid-side voltages are judged by using a sine and cosine component detecting method and a zero-order voltage method; (III) a turn-off angle added value and a turn-off angle returned time constant are determined by using a turn-off angle logic method, and a trigger angle is reduced through a turn-off angle controller; (IV) a rectification station puts instantaneous current control into a commutation failure recovery process. The method for defending the periodic commutation failures of the one-tower double-circuit DC transmission system can effectively prevent periodic commutation failures from occurring to a DC transmission system, and DC blocking accidents are prevented from occurring.

An I/O pad ESD protection circuit is composed of a SCR circuit, a first diode, a second diode, and an anti-latch-up circuit. The SCR circuit has a first connection terminal and a second connection terminal, respectively coupled to the I/O pad and the ground voltage, so as to discharge the electrostatic charges. The anti-latch-up circuit has two terminals, which are respectively coupled to the voltage source and the ground voltage, and another connection terminal, used to send an anti-latch-up signal to the SCR for changing the activating rate. The latch-up phenomenon is avoided.

The invention discloses a DC fault judgment method for a flexible multi-terminal DC transmission system. The DC rise rate in a DC fault is lowered by increasing a DC inductance value to prevent an MMC from being locked; or an AC instruction value of the MMC is set to be zero during the DC fault, so that a bridge arm current is lowered to prevent the MMC from being locked; or the MMC is locked during the DC fault, but an AC breaker of the MMC is not cut off, so that the power restoration speed after the fault is cleared is improved. The invention further discloses the DC fault judgment method for the flexible multi-terminal DC transmission system. The DC voltage mutation rate on a DC inductance line side is measured, so that the DC fault is judged when an absolute value of the mutation rate exceeds a certain threshold. The AC breaker of the MMC can be prevented from being cut off in the DC fault; the power restoration speed of the MMC employing an overhead line after the DC fault is cleared is greatly improved; meanwhile, a rapid and accurate judgment can be made for the DC fault; and timely fault treatment and control are facilitated, so that the risk that the MMC bears an over-current is reduced.

When a power supply is turned off its output voltages decrease over certain times. If the power supply is turned back on before the output voltages have had time to decrease to a level required by certain electronic circuits before power is reapplied, then these electronic circuits may malfunction or latch-up. A power supply shutdown control monitors voltage levels of the power supply. The power supply shutdown control prevents the power supply from being turned back on before the output voltages have reached a sufficiently low voltage level. A voltage reset monitor determines when a power supply voltage drops below a certain level, and then a memory device stores the instance of a power supply voltage drop and uses the stored instance to prevent the power supply from being turned on until the monitored voltage(s) have reached the sufficiently low voltage level. Then, the stored instance is reset and the power supply may be re-energized.

Distributed switches to suppress transient electrical overstress-induced latch-up are provided. In certain configurations, an integrated circuit (IC) or semiconductor chip includes a transient electrical overstress detection circuit that activates a transient overstress detection signal in response to detecting a transient electrical overstress event between a pair of power rails. The IC further includes mixed-signal circuits and latch-up suppression switches distributed across the IC, and the latch-up suppression switches temporarily clamp the power rails to one another in response to activation of the transient overstress detection signal to inhibit latch-up of the mixed-signal circuits.

A protection circuit according to an embodiment of the present invention is provided between a first terminal and a second terminal and includes: a capacitor element having one end connected to the second terminal; and a multi-cathode thyristor formed on a semiconductor substrate, and including an anode connected to the first terminal, a first cathode connected to the second terminal, and a second cathode disposed between the anode and the first cathode and connected to another terminal of the capacitor element.

A power semiconductor device is disclosed with layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side. The device can include a drift layer, a first base layer in direct electrical contact to the emitter electrode, a first source region embedded into the first base layer which contacts the emitter electrode and has a higher doping concentration than the drift layer, a first gate electrode in a same plane and lateral to the first base layer, a second base layer in the same plane and lateral to the first base layer, a second gate electrode on top of the emitter side, and a second source region electrically insulated from the second base layer, the second source region and the drift layer by a second insulating layer.

A voltage generator that prevents latch-up includes: a charge pump circuit that is controlled by first through third enable signals, boosts an internal power voltage generated from an external power voltage, and generates first through fourth voltages; a detector that detects the first through third voltages and generates first through third flag signals that go logic high when the first through third voltages reach predetermined respective voltage levels and maintain logic low when the voltages do not reach the predetermined respective voltage levels; and a charge pump controller that receives the first through third flag signals, and generates the first through third enable signals to have the first through fourth voltages sequentially generated. The voltage generator can prevent latch-up that may occur in a boosting mode or in a normal operation mode.

An input voltage Vin is supplied to a first terminal of a control circuit via an inductor connected to outside, and an output capacitor is connected to a second terminal. A switching transistor is provided between the first terminal and ground, and a synchronous rectifier transistor is provided between the first terminal and the second terminal. A first transistor is provided between a back gate of a synchronous rectifier transistor and the first terminal, and a second transistor is provided between the back gate and the second terminal. A switch control unit turns OFF the first transistor and the second transistor at a step-up stop interval; and turns OFF the first transistor and turns ON the second transistor at a step-up operation interval.

The invention provides a power system relay protection system based on wireless transmission. The power system relay protection system based on the wireless transmission comprises the following components: (1) an industrial wireless switch; (2) a wireless synchronization clock device; (3) a wireless merging unit device; (4) a wireless intelligent terminal device; and (5) a wireless protection device, wherein the wireless relay protection device comprises a wireless plugin, a management board plugin, a protection plugin, a power plugin and the like. The power system relay protection system based on the wireless transmission, provided by the invention, can effectively reduce building materials such as optical cables, copper cables and the like which are used during secondary wiring in a substation, shortens the construction period, saves the construction investment, reduces a secondary return circuit, prevents locking and misoperation of protection caused by the secondary return circuit problem improves the reliability of the protection system, is convenient to install and debug, and can reduce the workload of maintenance personnel.

A semiconductor substrate made of P⁻ type or P⁻⁻ type silicon having a thickness of approximately 700 μm and a resistivity of 10 Ω·cm to 1000 Ω·cm is provided, a BOX layer with a thickness of 0.2 μm to 10 μm is provided on the semiconductor substrate and a p⁻ type SOI layer is provided on this BOX layer. A first insulating film, which makes contact with the BOX layer, is locally buried in this p⁻ type SOI layer and a CMOS is formed in a region of the p⁻ type SOI layer wherein the above-described first insulating film is not provided. A second insulating film is provided above the first insulating film and over the CMOS, so as to cover the CMOS, and an inductor is provided on the region of this second insulating film corresponding to the first insulating film.

A memory device can include a group of memory cells, which can be arranged in a column (100) that receives power by way of a first cell supply nodes (106-0 to 106-m). A current limiter (110) can be situated between first cell supply nodes (106-0 to 106-m) and a power supply (VH), and limit a current (llimit) to less than a latch-up holding current (lhold_lu) for the group of memory cells (100). In a particle event, such as an α-particle strike, a current limiter (110) can prevent a latch-up holding current (lhold_lu) from developing, thus preventing latch-up from occurring. Current limiter (110) can include p-channel transistors and/or resistors, and thus consume a relatively small area of the memory device.

A high voltage semiconductor element and an operating method thereof are provided. The high voltage semiconductor element comprises a high voltage metal-oxide-semiconductor transistor (HVMOS) and a NPN type electro-static discharge bipolar transistor (ESD BJT). The HVMOS has a drain and a source. The NPN type ESD BJT has a first collector and a first emitter. The first collector is electronically connected to the drain, and the first emitter is electronically connected to the source.

A voltage generator capable of preventing latch-up is disclosed. The voltage generator includes a positive charge pump unit, a negative charge pump unit, a second stage charge pump unit, and a control unit. The positive charge pump unit is utilized for generating a positive charge pump voltage according to a first enable signal. The negative charge pump is utilized for generating a negative charge pump voltage according to a second enable signal. The second stage charge pump unit is utilized for generating a gate-on voltage and a gate-off voltage according to a third enable signal and a fourth enable signal. The control unit is utilized for generating the first enable signal, the second enable signal, the third enable signal, and the fourth enable signal and make the second stage charge pump unit generate the gate-on voltage (or the gate-off voltage) in a successively-increasing (or decreasing) manner.

The present invention provides a method for starting a modularized multi-level flexible direct-current transmission converter. The method comprises: connecting a direct-current side pole of each converter station, disconnecting an alternating-current circuit breaker of each converter station, and locking a sub module of each converter station; closing an alternating-current circuit breaker of an active station at one end, and a power supply carrying out passive charging on the active station and the remaining converter stations by using startup resistors; after the passive charging is completed, bypassing the startup resistor of the active station, unlocking the remaining converter stations, and carrying out active charging to reach a rated voltage of a power module; interlocking the remaining converter stations, the converter stations charged by the active station carrying out unlocking and starting direct-current voltage control subjected to a slope until the power module is charged to the rated voltage; and unlocking the remaining converter stations, after entering into a controlled stage again, carrying out grid connection and switching a control policy to a normal operation policy, and increasing power, wherein the converter operates normally. According to the method disclosed by the present invention, voltage consistency of the power module in the starting process can be ensured, so as to avoid startup failure and protection locking caused by unevenness of the capacitance and voltage of the power module.

Latch-up preventing circuits and methods are provided for ESD protection cells. A method of preventing latch-up in an ESD protection cell is described which includes monitoring the ESD protection cell to detect the activation of the ESD protection cell in response to an ESD event. After detection of the activation of the ESD protection cell, the supply current to the ESD protection cell is turned off, preventing latch-up. Circuit embodiments are described in which ESD protection circuits include are provided with a detection and reset circuit. The circuit is adapted to turn off the supply current to the ESD protection cell upon the detection of the activation of the ESD cell.