10results about How to "Avoid latch-up" patented technology

The invention belongs to the field of design of an electrostatic discharge (ESD) protection device of a high-voltage integrated circuit (IC), aims at an improved lateral silicon controlled rectifier (MLSCR), and particularly provides a multi-channel SCR device which is used for ESD protection of the high-voltage integrated circuit and is adjustable in trigger voltage and maintaining voltage, and the multi-channel SCR device can be used for achieving ESD protection of an input / output port (I / O for short) and a power domain. The device comprises two MLSCR structures, has the advantages of being adjustable in trigger voltage and maintaining voltage, high in latch-up resistance, high in robustness and the like, and can be suitable for integrated circuit ESD protection under various high-voltage power supply domains.

The present invention discloses a PNP type Schottky collector region AlGaN / GaN HBT device, which comprises, from bottom to top, a substrate, a buried oxide layer, a collector region, a base region and an emitter region, wherein the collector region comprises a lower P-type single crystal silicon layer and an upper metal silicide layer, the base region comprises an N-type AlGaN layer, and the emitter region comprises a P-type GaN layer; a collector electrode is arranged on the P-type single crystal silicon layer, a base electrode is arranged on the N-type AlGaN layer, and an emitter electrode is arranged on the P-type GaN layer. The present invention has good contact interface characteristics, can improve the switching speed and cut-off frequency of the device, has a simple process and is compatible with existing silicon-based processes.

The present invention provides an ESD protection device and an electronic device, the ESD protection device comprising: a main thyristor rectifier, the main thyristor rectifier having an anode terminal and a cathode terminal, the anode terminal being connected to the anode of the ESD protection device; at least one trigger unit, each of the trigger units comprising a secondary thyristor rectifier and a resistor unit arranged in parallel, the anode terminal of the secondary thyristor rectifier being connected to the cathode terminal of the main thyristor rectifier or the adjacent secondary thyristor rectifier, the cathode terminal of the secondary thyristor rectifier being connected to the anode terminal of the adjacent secondary thyristor rectifier or the cathode of the ESD protection device, and the resistor unit being connected in parallel between the anode terminal and the cathode terminal of the secondary thyristor rectifier. The ESD protection device can increase the holding voltage while basically keeping the trigger voltage unchanged, so as to better avoid the latch effect. The electronic device has similar advantages.

The invention discloses a chip with a latch protection function. The chip comprises a power port and a grounding port, the voltage converter is connected between the power supply port and the grounding port, and the voltage converter is used for obtaining power supply voltage according to input voltage of the power supply port; the functional circuit is connected between the output end of the voltage converter and the grounding port so as to receive the power supply voltage; the test port is connected with the output end of the voltage converter; and the latch protection circuit is used for detecting the voltage of the test port and short-circuiting the test port and the grounding port when the voltage of the test port drops to a preset voltage so as to protect the chip.

The application provides a silicon controlled rectifier (SCR) device, which comprises a high-voltage P well region and a high-voltage N well region. The high-voltage P well region is sequentially provided with a first P+ doped region and a first N+ doped region. The high-voltage N well region is sequentially provided with a second P+ doped region and a second N+ doped region, and a preset normal-pressure P well region is arranged below the first N+ doped region and / or a preset normal-pressure N well region is arranged below the second P+ doped region. In the SCR device and chip, the preset normal-pressure P well region is formed below the first N+ doped region in the high-voltage P well region and / or the preset normal-pressure N well region is formed below the second P+ doped region in the high-voltage N well region, the recombination efficiency of the emitter injection carriers of the SCR device is improved, the regenerative feedback effect of the SCR device in the conduction process is inhibited, the holding current is improved, and the latch-up phenomenon of the SCR device under the electrostatic protection impact is avoided.

The present invention provides a mesa structure PNP type Schottky collector region SOI SiGe HBT structure, comprising a single crystal silicon substrate and an SOI substrate composed of a buried oxide layer stacked on the surface of the single crystal silicon substrate, wherein a P-type heavily doped single crystal silicon layer, a metal silicide thin layer, an N-type heavily doped Si 1‑x Ge x The base layer, the P-type doped single crystal silicon emitter cap layer and the P-type heavily doped polycrystalline silicon emitter layer, the P-type heavily doped polycrystalline silicon emitter layer to the P-type doped single crystal silicon emitter cap layer are etched to form an emitter and base electrode contact table, the P-type heavily doped polycrystalline silicon emitter layer to the metal silicide thin layer are etched to form a collector electrode contact table, the table structure surface is covered with an oxide film layer, the electrode window is formed with a corresponding metal electrode, and the base electrode contact area is deposited with N-type heavily doped Si 1‑ y Ge y The present invention also provides a method for preparing the aforementioned structure. The present application can improve the device cutoff frequency and gain and reduce the base region transit time and is compatible with conventional silicon-based processes.

The present invention discloses an NPN type Schottky collector region AlGaN / GaN HBT device and a preparation method thereof, which comprises, from bottom to top, a substrate, a buried oxide layer, a collector region, a base region and an emitter region, wherein the collector region comprises a lower N-type single crystal silicon layer and an upper TiSi2 layer, the base region comprises a P-type GaN layer, and the emitter region comprises an N-type AlGaN layer and an N-type GaN cap layer thereon; a collector electrode is disposed on the N-type single crystal silicon layer, a base electrode is disposed on the base region, and an emitter electrode is disposed on the GaN cap layer. The present invention has good contact interface characteristics, can improve the switching speed and cut-off frequency of the device, has a simple process and is compatible with existing silicon-based processes.

This invention provides a bidirectional SCR electrostatic discharge (ESD) protection device, comprising a P-type substrate, an N-type buried layer, a P-type epitaxial layer, a deep N-type well, a first P-type well, a second P-type well, an N-type well, a high-voltage N-type well, heavily doped P-type material, a first shallow trench isolation layer, heavily doped N-type material, a first field oxygen isolation layer, and a floating field plate. The P-type substrate is located at the bottom layer, and the N-type buried layer is located above the P-type substrate, with their surfaces flush. The P-type epitaxial layer is located above the P-type substrate. The deep N-type well, the first P-type well, the second P-type well, the N-type well, the high-voltage N-type well, the heavily doped P-type material, and the heavily doped N-type material are all formed within the P-type epitaxial layer via ion implantation. This invention reduces the device's turn-on voltage through the floating field plate, and achieves sequential or simultaneous turn-on of different current discharge paths through two current discharge paths and the length of the field oxygen isolation layer, controlling the device's double hysteresis characteristics to avoid latch-up effects. The centrosymmetric structure increases the longitudinal current, improving the overall current capability of the device.

The utility model relates to chip on -line control technical field, concretely for adjustable chip power -on time sequence control circuit. Including at least two stages of DC -DC power module of concatenation, every stage DC -DC power module includes input power end, output voltage end, enable control end (EN) and power good signal end (PG). The utility model discloses through the DC -DC power module of cascaded setting, utilizes the RC delay circuit between power good signal end (PG) of preceding stage module and enable control end (EN) of rear stage module, has realized the flexible adjustment of rear stage module power -on delay time, need not to rely on complex control chip or software program, can accurate matching chip required power -on time sequence only through the adjustment of resistance capacitor parameter, has reduced circuit complexity and cost.

The utility model provides an SCR device used for ESD protection and an electrostatic protection circuit, the SCR device comprises an SCR structure, a BJT transistor structure triggered by NPN and a GGNMOS transistor structure triggered by PNP, so that the SCR device is provided with an SCR current discharge path, a BJT current discharge path and a GGNMOS current discharge path, the trigger voltage Vt of the SCR device is reduced, and the ESD protection circuit is used for ESD protection. The maintaining voltage Vh of the SCR device is improved to avoid the latch-up effect, and the ESD robustness of the SCR device is enhanced to resist the impact of ESD pulses.