59results about How to "Increase parasitic resistance" patented technology

The self-aligned trench-type DMOS transistor structure comprises a self-aligned source region being surrounded by a trench gate region. The self-aligned source region comprises a moderately-doped p-base diffusion region formed in a lightly-doped epitaxial semiconductor substrate, a self-aligned heavily-doped n+ source diffusion ring formed in a side surface portion of the moderately-doped p-base diffusion region, a heavily-doped p+ contact diffusion region formed in a surface portion of the moderately-doped p-base diffusion region surrounded by the heavily-doped n+ source diffusion ring, and a self-aligned source contact window formed by a semiconductor surface surrounded by a sidewall dielectric spacer. The trench gate region comprises a gate dielectric layer being lined over a trenched semiconductor surface with or without a thicker isolation dielectric layer formed on a bottom trenched semiconductor surface and a self-aligned highly conductive gate layer being formed at least over the gate dielectric layer.

To provide a technique capable of achieving improvement of the parasitic resistance in FINFETs. In the FINFET in the present invention, a sidewall is formed of a laminated film. Specifically, the sidewall is composed of a first silicon oxide film, a silicon nitride film formed over the first silicon oxide film, and a second silicon oxide film formed over the silicon nitride film. The sidewall is not formed on the side wall of a fin. Thus, in the present invention, the sidewall is formed on the side wall of a gate electrode and the sidewall is not formed on the side wall of the fin.

A field effect transistor includes a nitride semiconductor layer; an InxAlyGa1-x-yN layer (wherein 0<x<1, 0<y<1 and 0<x+y<1) formed on the nitride semiconductor layer; and a source electrode and a drain electrode formed on and in contact with the InxAlyGa1-x-yN layer. The lower ends of the conduction bands of the nitride semiconductor layer and the InxAlyGa1-x-yN layer are substantially continuous on the interface therebetween.

A resetable over-current self-protecting semiconductor power device comprises a vertical power semiconductor chip and an over-current protection layer composed of current limiting material such as a PTC material. The over-current protection layer may be sandwiched between the vertical power semiconductor chip and a conductive plate, which could be a leadframe, a metal plate, a PCB plate or a PCB that the device is mounted on.

A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S / D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S / D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S / D and the extension. A method of forming the aforementioned MOSFET device is also provided.

A vertical semiconductor power device includes a top surface and a bottom surface of a semiconductor substrate constituting a vertical current path for conducting a current there through. The semiconductor power device further includes an over current protection layer composed of a material having a resistance with a positive temperature coefficient (PTC) and the over current protection layer constituting as a part of the vertical current path connected to a source electrode and providing a feedback voltage a gate electrode of the vertical semiconductor power device for limiting a current passing there through for protecting the semiconductor power device at any voltage.

Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path is disclosed. The MRAM includes an MRAM array that includes MRAM bit cell rows each including a plurality of MRAM bit cells. MRAM bit cells on an MRAM bit cell row share a common electrode to provide a shared write operation circuit path for write operations. Dedicated read operation circuit paths are also provided for each MRAM bit cell separate from the write operation circuit path. As a result, the read operation circuit paths for the MRAM bit cells do not vary as a result of the different layout locations of the MRAM bit cells with respect to the common electrode. Thus, the read parasitic resistances of the MRAM bit cells do not vary from each other because of their different coupling locations to the common electrode.

The present disclosure discloses a method of forming a semiconductor layer on a substrate. The method includes patterning the semiconductor layer into a fin structure. The method includes forming a gate dielectric layer and a gate electrode layer over the fin structure. The method includes patterning the gate dielectric layer and the gate electrode layer to form a gate structure in a manner so that the gate structure wraps around a portion of the fin structure. The method includes performing a plurality of implantation processes to form source / drain regions in the fin structure. The plurality of implantation processes are carried out in a manner so that a doping profile across the fin structure is non-uniform, and a first region of the portion of the fin structure that is wrapped around by the gate structure has a lower doping concentration level than other regions of the fin structure.

A semiconductor device includes a semiconductor substrate of a first conductivity-type, a buried diffusion layer of a second conductivity-type formed in the semiconductor substrate, a first well of the second conductivity-type having a bottom portion in contact with a top portion of the buried diffusion layer, the first well having an annular shape in a planar view, and a second well of the first conductivity-type formed to be surrounded by the first well. The semiconductor device further includes a diffusion region formed between a first portion of the second well and a second portion of the second well, the diffusion region having an impurity concentration lower than that of the second well, so that a depletion layer formed in the diffusion region can be provided, a transistor formed on the second well to function as an ESD (electro-static discharge) protection element, and an external terminal connected to a drain of the transistor.

A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S / D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S / D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S / D and the extension. A method of forming the aforementioned MOSFET device is also provided.

Disclosed herein is a semiconductor device, including: a gate electrode formed on a semiconductor substrate through a gate insulating film; an extension region formed in the semiconductor substrate on a source side of the gate electrode; a source region formed in the semiconductor substrate on the source side of the gate electrode through the extension region; an LDD region formed in the semiconductor substrate on a drain side of the gate electrode; and a drain region formed in the semiconductor substrate on the drain side of the gate electrode through the LDD region; wherein the extension region is formed at a higher concentration than that of the LDD region so as to be shallower than the LDD region.

A semiconductor device has a semiconductor (e.g., a silicon substrate), an electrically conductive region (e.g., a source region and a drain region) which is in contact with the semiconductor to form a Schottky junction, and an insulator. The insulator is in contact with the semiconductor and the electrically conductive region, and has a fixed-charge containing region which contains a fixed charge and extends across a boundary between the semiconductor and the electrically conductive region.

A multi-finger transistor is described, including multiple parallel transistors. Each transistor includes a gate dielectric layer, a gate, a source / drain region, and a drift region in the peripheral substrate of the source / drain region separating the source / drain region and the channel region under the gate. The width of the drift region extending from the side boundary of the source / drain region increases stepwise from the edge sections of the multi-finger transistor toward the central section of the same.

A semiconductor device includes: a semiconductor substrate; a device active portion formed in the semiconductor substrate; a device isolation portion formed in the semiconductor substrate so as to surround the periphery of the device active portion; an insulating film stacked on the device active portion; and a gate electrode stacked on the insulating film. The device active portion includes: a source region and a drain region located opposite each other in a gate length direction, and a channel region interposed between the source region and the drain region. The channel region includes: a central region connecting the source and drain regions and having an approximately rectangular shape, and a protruding region protruding from one side end of the central region in a gate width direction. The channel region is located inwardly of the gate electrode when viewed in the stacking direction.

A vertical semiconductor power device includes a top surface and a bottom surface of a semiconductor substrate constituting a vertical current path for conducting a current there through. The semiconductor power device further includes an over current protection layer composed of a material having a resistance with a positive temperature coefficient (PTC) and the over current protection layer constituting as a part of the vertical current path connected to a source electrode and providing a feedback voltage a gate electrode of the vertical semiconductor power device for limiting a current passing there through for protecting the semiconductor power device at any voltage.

The invention provides a semiconductor device. The semiconductor device forms a silicide on a protection ring for latch prevention, and avoids the protection ring from being damaged by an ESD surge. As a solving means, the semiconductor device has a structure that, a silicide with a width (W3) is not formed on a surface of a second protection ring for latch prevention, and at a side facing a transistor forming region (20).

In a display apparatus, a thin film transistor, a planarization film, and at least two light-emitting devices are provided on a substrate, and the light-emitting device at least includes a light-emitting layer and first and second electrodes. At least two first contact holes and at least two second contact holes are provided in the planarization film at a part outside a display region and connect the first electrode to ground wiring and / or power wiring with a resistance lower than that of the first electrode, the distance between the second contact hole and the display region is longer than that between the first contact hole and the display region, and the opening area of the second contact hole is smaller than that of the first contact hole.

The invention discloses an LDMOS (laterally diffused metal oxide semiconductor) device and a manufacturing method thereof. A drift region of the LDMOS device comprises a first drift region and a second drift region; the first drift region is formed by an ion implantation region formed in a selected area of a silicon substrate; the second drift region is formed by doped polysilicon formed on the surface of the silicon substrate; the second drift region is overlapped on the first drift region, and a drain region is formed in the second drift region. Owing to arrangement of the second drift region, thickness of the whole drift region is increased, and accordingly parasitic resistance of the whole drift region is reduced while effectiveness in increase of linear current of the device and reduction of on resistance of the device can be achieved. In addition, the LDMOS device is capable of keeping high breakdown voltage and is low in process cost.

The invention discloses a power bipolar transistor and a manufacture method thereof and belongs to the field of semiconductor devices and technological manufacture. The power bipolar transistor sequentially comprises a collector area metal electrode, a collector area formed by first conduction type semiconductor materials and a base area formed by second conduction type semiconductor materials from bottom to top, wherein a base area metal electrode contacted with the surface of the base area and a transmission area formed by the first conduction type semiconductor materials are arranged above the base area; a transmission area metal electrode contacted with the surface of the transmission area is arranged above the transmission area, and isolation media are filled between the lateral wall of the transmission area and the base area metal electrode and between the base area metal electrode and the transmission area metal electrode. The lateral wall of the transmission area is wrapped by a medium layer, so that current of a base electrode directly flows to the lateral wall of the transmission area by contacting with the base area, and current side concentration effect is remitted. Simultaneously, the base area metal electrode is manufactured on the isolation media by punching holes, parasitic resistance of the base area cannot be added, and no influence can be caused on output power of the power bipolar transistor.