63results about How to "Enhanced ESD robustness" patented technology

Silicon is formed at selected locations on a silicon-insulator (SOI) substrate during fabrication of selected electronic components, including resistors, capacitors, and diodes. The silicon location is defined using a patterned, removable mask, and the silicon may be applied by deposition or growth and may take the form of polysilicon or crystalline silicon. Electrostatic discharge (ESD) characteristics of the SOI device is significantly improved by having a thick double layer of silicon in selected regions.

In various embodiments, the invention relates to bond pad structures including planar transistor structures operable as over-voltage clamps.

An antenna device for a portable device has an antenna loop of conducting material to be connected to radio circuitry in the portable device. The antenna loop is positioned opposite a ground plane of a PCB. Also, the antenna device also comprises at least one battery, which is positioned in the extension of a first side of the PCB, and acts as an extension of the ground plane of the PCB.

The present invention relates to an SCR (Silicon Controlled Rectifier) for the ESD (electrostatic discharge) protection comprising two terminal electrodes of a first electrode and a second electrode, a PMOS, an NMOS and an SCR structure. By utilizing an embedded SCR, a whole-chip ESD protection circuit design can be obtained. The present invention is suitable for IC products, and for applications by IC design industries and IC foundry industries.

A display device that includes a substrate having a display region and an adjacent peripheral region is provided, including; a plurality of sub-pixels provided within the display region; a plurality of data lines electrically connected to the sub-pixels; and a first electronic circuit group and a second electronic circuit group provided in the peripheral region, connected to the corresponding data lines. The first electronic circuit group includes a plurality of first electronic circuits, and the second electronic circuit group includes a plurality of second electronic circuits. Two adjacent first electronic circuits are arranged with a first interval therebetween, and the first interval has a first width. Two adjacent second electronic circuits are arranged with a second interval therebetween, and the second interval has a second width. The first width and the second width are different.

An electronic static discharge (ESD) protection device with a bidirectional silicon controlled rectifier (SCR) structure embedded with an interdigital N-channel metal oxide semiconductor (NMOS) can be applied to an ESD protection circuit of an on-chip integrated circuit (IC) and mainly comprises a P substrate, a P epitaxial layer, a first N pit, a P pit, a second N pit, a first N+ injection region, a first P+ injection region, a second N+ injection region, a third N+ injection region, a second P+ injection region, a fourth N+ injection region, a fifth N+ injection region, a third P+ injection region, a sixth N+ injection region, a plurality of poly-silicon gates, a plurality of thin gate oxide layers and a plurality of shallow isolation grooves. On one hand, under the positive and negative ESD pulse effects, an ESD current discharge path with a symmetric structure and complete same electrical property exists in the device, the ESD current discharge ability of the device can be improved, and bidirectional protection of an ESD pulse is achieved; and on the other hand, the interdigital NMOS composed of an NMOS M<1> and an NMOS M<2> and a parasitic P pit resistor form a resistance-capacitance coupling current path, so that the ESD robustness of the device is enhanced, the current density in an SCR current conduction path is reduced, the conduction resistance of the SCR is increased, and the maintaining voltage is increased.

An electrostatic discharge (ESD) protection device with enhanced ESD robustness. The ESD protection device comprises a pad, a finger-type MOS, a well stripe and a doped segment. The pad is on a semiconductor substrate of a first-conductive type. The finger-type MOS is on the semiconductor substrate and comprises drain regions, source regions and channel regions. Each drain region is of a second-conductive type and is coupled to the pad. Each source region is of the second-conductive type and coupled to a power rail. Channel regions are formed on the semiconductor, substantially parallel to each other. Each channel region is located between one source region and one drain region. The well stripe is of the second-conductive type and formed on the semiconductor, in an angle to the channel regions. The doped segment is of the first-conductive type and in the well stripe. Furthermore, the doped segment is coupled to the pad.

A read / write head for a disk drive having a shorting conductor from a shield of the read element to a conductor that runs from the write element to an external electrical contact pad. This allows for the measurement of the electrical isolation between the read sensor and the read shield via the external contact pads. Such a capability allows the electrical isolation to be measured both during the lapping process and subsequent to the heads being diced into separate sliders. This shorting conductor may be in the form of an internal shorting stud or in the form of an interim conductor that passes through the parting zone between adjacent heads. In the latter case, the shorting conductor is broken when the heads are diced so that a head of this embodiment can only be measured for electrical isolation prior to dicing.

A semiconductor device and method. The device includes a first domain and a second domain each having a power rail and a ground rail. The device further includes a signal line connected between the first domain and the second domain. The device also includes an electrostatic discharge protection circuit for providing cross-domain ESD protection. The protection circuit includes a blocking transistor connected between the first domain power rail and the signal line. The protection circuit also includes a power rail clamp connected between the first domain power rail and the first domain ground rail. The power rail clamp is operable to apply a control signal to a gate of the blocking transistor to switch it on during normal operation and to switch it off during an ESD event. The power rail clamp is operable during the ESD event to conduct an ESD current.

The invention discloses a bidirectional ESD protection anti-latch-up device of a holosymmetric dual-grid-control-diode triggering SCR structure, and the device can be used for improving the capabilityof an IC chip in resisting ESD. The device mainly consists of a P substrate, a P epitaxial part, a first N well, a P well, a second N well, a first N+ injection region, a first P+ injection region, asecond N+ injection region, a second P+ injection region, a third N+ injection region, a third P+ injection region, a fourth N+ injection region, a first polysilicon gate, a first thin gate oxide layer covering the first polysilicon gate, a second polysilicon gate, and a second thin gate oxide layer covering the second polysilicon gate. The device has a resistance-capacitance coupling auxiliary triggering path under the action of ESD stress, does not need an additional layout area, also can make the most of the advantages of low triggering voltage of a resistance-capacitance coupling circuitand the short start time, and shortens the voltage hysteresis amplitude of the device. In addition, the device also employs the conduction characteristics of the gate control diodes, improves the potential of a parasitic well resistor of the N well, and speeds up the starting of a current releasing path of the SCR structure. Moreover, the device has two ESD current releasing paths and a holosymmetric structure, facilitates the improvement of the ESD robustness of the device, and can achieve the bidirectional protection of ESD.

The invention discloses a high-voltage electronic static discharge (ESD) protection device with a positive-negative (PN) junction auxiliary trigger silicon controlled rectifier-laterally diffused metal oxide semiconductor (SCR-LDMOS) structure. The high-voltage ESD protection device comprises a P-type substrate, wherein a buried oxygen layer is arranged on the P-type substrate, a shift region is arranged on the buried oxygen layer, an N-buffer region, a P region and a P-body region are sequentially arranged on the shift region from left to right, a first drain heavily-doping N+ region and a first drain heavily-doping P+ region are sequentially arranged in the N-buffer region from left to right, a second source heavily-doping N+ region, a second source heavily-doping P+ region and a third source heavily-doping P+ region are sequentially arranged in the P-body region from left to right, and the P region and the second source heavily-doping P+ region are connected through a wire. When a drain of the ESD protection device encounters a positive ESD pulse, a reverse bias PN junction is used for helping improving the hole carrier concentration before trigger starting, and a trigger voltage V<t1> is reduced; and moreover, with the introduction of the reverse bias PN junction into the device, the positive and negative feedback effect of a parasitic SCR can be effectively prevented, thus, the maintaining voltage V<h> of the device can be effectively increased, and the latch-up effect of the device is prevented.

An ESD protection device structure includes a well having a first conductive type, a first doped region having a second conductive type disposed in the well, a second doped region having the first conductive type, and a third doped region having the second conductive type disposed in the well. The second doped region is disposed within the first doped region so as to form a vertical BJT, and the first doped region, the well and the third doped region forms a lateral BJT, so that pulse voltage that the ESD protection structure can tolerate can be raised.

An ESD protection component of an LDMOS structure and with high maintaining voltage can be used for an on-chip IC high-voltage ESD protection circuit and mainly comprises a P substrate, a high-voltage N trap, an N trap, a P trap, a P sink doping, a P+ injection region, a first N+ injection region, a second N+ injection region, a meal anode, a metal cathode, a polysilicon gate, a thin gate oxide layer and a plurality of field oxide isolation regions. According to the ESD protection component of the LDMOS structure, under the action of an high-voltage ESD, on one hand, a parasitic SCR current discharging path is formed by the P sink doping, the N trap, the high-voltage N trap, the P trap and the first N+ injection region, idle currents of the component are increased, and ESD robustness of the component is improved; on the other hand, by means of a biasing reversal PN junction formed between the second N+ injection region and the P sink doping, maintaining voltage of the component is improved and the latch-up-resistant capacity of the component is improved.

The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly to a low parasitic capacitance electrostatic discharge protection circuit. An ESD protection circuit is established with the structure in accordance with the present invention comprising a plurality of discharging paths. The ESD protection circuit is connected to the input / output pad of a radio frequency (RF) core circuit. Such that, the RF core circuit with the ESD protection circuit of the present invention feature much higher ESD robustness. And the parasitic capacitance of the ESD protection is reduced because of the structure of the present invention.

The present disclosure relates to non-planar ESD protection devices. The present disclosure provides a device structure and method of fabricating the structure that is essentially immune to latch-up and possess high ESD robustness and reliability. In an aspect, the present disclosure provides a mixed silicidation and selective epitaxy (epi) FinFET processes for latch-up immunity together with ESD robustness, thereby allowing achievement of ESD efficient parasitic structures together with latch-up immune and reliable functional devices. The present disclosure provides a dual silicidation scheme where ESD protection element(s) have fins that are partially silicided, and functional devices have fins that are fully silicided. The present disclosure also provides a hybrid contact and junction profile scheme where ESD protection element(s) have fins that are partially silicided with or without deep junctions depending on their application, and functional devices have fins that are fully silicided with the silicide edge crossing the junction. On the other hand, a dual Epi scheme is implemented such that ESD protection elements have fins with Epi contact, and functional devices have fins that are fully silicided without Epi (raised S / D) contact.

The present invention belongs to the technical field of electrons, especially relates to the design of an ESD (Electro-Static discharge) protection circuit, and especially provides a three-end compactand compound SCR device (CCSCR) for whole-chip ESD protection. The three-end compact and compound SCR device comprises a main discharge CCSCR and a RC auxiliary trigger detection circuit; the main discharge CCSCR is a three-end device, three parasitic SCR pathways are introduced on the basis of the CMOS device structure so that the whole-chip ESD protection with high robustness is achieved in a smaller territory area; the RC auxiliary trigger detection circuit is introduced to further reduce the triggering voltage of the device; and besides, the CCSCR can be taken as a two-end device to supply ESD protection between any one IO port and a power supply.

The invention provides an electrostatic protection device comprising a substrate, wherein a deep N trap is arranged in the substrate, a first P trap, a first N trap and a second P trap are sequentially arranged in the deep N trap from left to right, a first P+ injection region, a first N+ injection region and a second N+ injection region are sequentially arranged in the first P trap from left to right, a third N+ injection region, a fourth N+ injection region and a fourth P+ injection region are sequentially arranged in the second P trap from left to right, the second P+ injection region is bridged between the first P trap and the first N trap, the third P+ injection region is bridged between the first N trap and the second P trap, the first P+ injection region and the first N+ injection region are both connected with an anode, and the fourth P+ injection region and the fourth N+ injection region are both connected with a cathode. According to the electrostatic protection device, the maintaining voltage can be improved, the trigger voltage is reduced, and the ESD robustness of the device is improved.

Provided is an electrostatic discharge (ESD) protection structure including a substrate, a pick-up region, a first MOS device, a second MOS device, a first doped region and a second doped region. The pick-up region is located in the substrate. The first MOS device has a first drain region of a first conductivity type located in the substrate. The second MOS device has a second drain region of the first conductivity type located in the substrate. The first drain region is closer to the pick up region than the second drain region is. The first doped region of a second conductivity type is located under the first doped region. The second doped region of the second conductivity type is located under the second doped region. The area and / or doping concentration of the first doped region is greater than that of the second doped region.

The invention discloses a bidirectional high-voltage ESD protection device of a full-symmetric LDMOS triggered SCR structure, and belongs to the field of electrostatic discharge protection and surge resistance of integrated circuits. The protection device is mainly composed of a P substrate, a deep N well, a first P well, an N well, a second P well, a first P + injection region, a first N + injection region, a first polysilicon gate, a first thin gate oxide layer, a first field oxide isolation region, a second P + injection region, a second field oxide isolation region, a second polysilicon gate, a second thin gate oxide layer, a second N + injection region and a third P + injection region. The two NLDMOSs are embedded to form an auxiliary trigger SCR current path in which the on-state NLDMOS and the off-state NLDMOS are connected in series. The voltage withstanding capability of the device is improved, so that the device meets the ESD protection requirement of a high-voltage power supply domain, the ESD robustness of the device is enhanced, the discharge efficiency of the device in unit area is improved, the carrier concentration of a base region in a parasitic SCR structure is reduced, and the maintaining voltage of the device is improved.

The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I / O cell libraries. The ESD device according to the present invention uses a novel I / O cell layout structure for implementing a turn-on restrained method that reduces the turn-on speed of an ESD guarded MOS transistor by adding a pick-up diffusion region and / or varying channel lengths in the layout structure.

An ESD protection device of an IGBT structure and with a high maintaining voltage can be used in an on-chip IC high-voltage ESD protection circuit. The ESD protection device is mainly composed of a P substrate, a high-voltage N well, an N well, a P well, a first P+ injection region, a second P+ injection region, an N+ injection region, a third P+ injection region, a fourth P+ injection region, a metal anode, a metal cathode, a polycrystalline silicon gate, a thin gate oxide layer and a plurality of field oxide isolation regions. According to the ESD protection device of the IGBT structure, under the action of high-voltage ESD pulses, on one hand, a current discharge path with a PNPN structure is formed by the third P+ injection region, the N well, the high-voltage N well, the P well and the N+ injection region, thereby improving failure current of the device and enhancing ESD robustness of the device; and on the other hand, another current discharge path with a parasitic PNP triode and a parasitic resistor being connected in series is formed by the third P+ injection region, the N well, the fourth P+ injection region, the first P+ injection region, the P well and the second P+ injection region, thereby improving the maintaining voltage of the device and enhancing anti-latch capability of the device.

The invention relates to a layout method for a transistor with improved ESD robustness. The layout method includes defining a ring region from a first conductive type; defining a first and a second rectangular diffusion regions from a second conductive type, wherein the first and second rectangular diffusion regions are isolated from each other; defining a ring diffusion region of the second conductive type between the first and second rectangular diffusion regions; defining a first gate electrode between the first rectangular diffusion region of the second conductive type and the ring diffusion region of the second conductive region; and defining a second gate electrode between the second rectangular diffusion region of the second conductive type and the ring diffusion region of the second conductive type.