ESD protection design with turn-on restraining method and structures

a protection circuit and turn-on technology, applied in the direction of semiconductor devices, electrical equipment, semiconductor/solid-state device details, etc., can solve the problems of high cost, increased cost, and serious degradation of cmos integrated circuits (ics), and achieve the reduction of the turn-on speed of the first mos transistor, improve the esd robustness of i/o cells, and increase the drain breakdown voltage

a protection circuit and turn-on technology, applied in the direction of semiconductor devices, electrical equipment, semiconductor/solid-state device details, etc., can solve the problems of high cost, increased cost, and serious degradation of cmos integrated circuits (ics), and achieve the reduction of the turn-on speed of the first mos transistor, improve the esd robustness of i/o cells, and increase the drain breakdown voltage

USRE43215E1Inactive Publication Date: 2012-02-28TRANSPACIFIC IP LTD
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  • ESD protection design with turn-on restraining method and structures
  • ESD protection design with turn-on restraining method and structures
  • ESD protection design with turn-on restraining method and structures

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Embodiment Construction

[0054]The present invention will now be described by way of preferred embodiments with references to the accompanying drawings. Like numerals refer to corresponding parts of various drawings.

[0055]Referring now to FIGS. 7(a) and 7(b), one embodiment of the present invention is shown in which a simple layout is employed for drawing an additional P+ pick-up diffusion region 70, which surrounds one of the MOS transistors (Mn1 guarded device) 72 to reduce its parasitic base-emitter resistance. Therefore, the parasitic BJT in Mn1 has a slower turn-on speed than that of the other MOS transistor (Mn2 ESD protection device) 74. As shown in FIG. 7(b), a pre-buffer 76 with a core logic 77 is connected to the Mn1 device 72, a pad 78 is connected to the Mn1 device 72 and Mn2 device 74, and an ESD current discharging path is indicated by dash lines when the turn-on speed of Mn1 device 72 is slowed down. A corresponding top layout view is shown in FIG. 7(c) in which a cross-sectional view along t...

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Abstract

The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I / O cell libraries. The ESD device according to the present invention uses a novel I / O cell layout structure for implementing a turn-on restrained method that reduces the turn-on speed of an ESD guarded MOS transistor by adding a pick-up diffusion region and / or varying channel lengths in the layout structure.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention is directed generally to electrostatic discharge (ESD) protection circuits for input / output (I / O) devices, and more particularly, to improving ESD robustness in I / O cell libraries using novel layout techniques to implement a turn-on retraining arrangement that reduces the turn-on speed or increases the breakdown voltage of a MOS transistor.[0003]2. Description of the Related Art[0004]The ESD robustness of CMOS integrated circuits (IC) has been found to be seriously degraded due to deep-submicron CMOS technologies. To improve the ESD robustness of the output transistors, the ESD-implant process and the silicide-blocking process have been widely implemented in the deep-submicron CMOS technologies. In addition to the process modification to improve the ESD robustness of the output buffers, the symmetrical layout structure had been emphasized to realize the large-dimension output transistors by ensurin...

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Application Information

Patent Timeline
28 Feb 2012
Publication
USRE43215E1
IPC
H01L23/62; H01L27/02
CPC
H01L27/0277; H01L2924/0002; H01L2924/00
Inventors
KER, MING-DOU; PENG, JENG-JIE