Storage and column decoding circuit thereof

A memory and column decoding technology, which is applied in the field of memory and its column decoding circuit, can solve the problems of large memory power loss, etc., and achieve the effects of reducing power loss, reducing power loss, and reducing the amount of charge
CN103247334AActive Publication Date: 2013-08-14SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Patent Information

Authority / Receiving Office
CN ยท China
Current Assignee / Owner
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
Publication Date
2013-08-14

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Abstract

The invention discloses a storage and a column decoding circuit thereof. The column decoding circuit of the storage comprises a NAND gate circuit, a NOT gate circuit, a level shift circuit and a first driving circuit, which are connected in sequence, as well as a second driving circuit and a precharging circuit, wherein the second driving circuit comprises a first PMOS (P-channel Metal Oxide Semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube; the precharging circuit comprises a second PMOS tube and a third NMOS tube; a source electrode of the second PMOS tube is suitable for being connected with a precharging power supply; and when the storage performs read operation, a voltage provided by the precharging power supply is a supply voltage of the storage. According to the storage and the column decoding circuit thereof provided by the technical scheme of the invention, the power consumption of the storage in reading operation can be reduced.
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Description

technical field

[0001] The invention relates to the technical field of memory, in particular to a memory and a column decoding circuit thereof. Background technique

[0002] Memory (Memory) is a memory device in a computer system used to store programs and data. All information in the computer, including input raw data, computer programs, intermediate running results and final running results are stored in the memory. A memory contains many storage units. Usually, the storage units are arranged in an array, and each storage unit has an address corresponding to its position. When performing operations such as reading and writing to a certain storage unit in the storage array, the address needs to be decoded by the row decoding circuit and the column decoding circuit respectively, and the row and column where the storage unit is located are selected.

[0003] figure 1 It is a schematic diagram of the structure of a common memory. refer to figure 1 , the memory includes a ...

Claims

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