Distributed switches to suppress transient electrical overstress-induced latch-up

Abstract

Distributed switches to suppress transient electrical overstress-induced latch-up are provided. In certain configurations, an integrated circuit (IC) or semiconductor chip includes a transient electrical overstress detection circuit that activates a transient overstress detection signal in response to detecting a transient electrical overstress event between a pair of power rails. The IC further includes mixed-signal circuits and latch-up suppression switches distributed across the IC, and the latch-up suppression switches temporarily clamp the power rails to one another in response to activation of the transient overstress detection signal to inhibit latch-up of the mixed-signal circuits.

Description

FIELD OF THE DISCLOSURE[0001]Embodiments of the invention relate to electronic systems, and more particularly, to systems and devices for transient electrical overstress protection and latch-up prevention.BACKGROUND[0002]Certain electronic systems can be exposed to electrical overstress events, or electrical signals of short duration having rapidly changing voltage and high power. Electrical overstress events can include, for example, electrostatic discharge (ESD) events arising from the abrupt release of charge from an object or person to an electronic system.[0003]Electrical overstress events can damage or destroy integrated circuits (ICs) by generating overvoltage conditions and high levels of power dissipation in relatively small areas of the ICs. High power dissipation can increase IC temperature, and can lead to numerous problems, such as gate oxide punch-through, junction damage, metal damage, and surface charge accumulation.SUMMARY OF THE DISCLOSURE[0004]Distributed switches...

AI Technical Summary

Benefits of technology

[0004]Distributed switches to suppress transient electrical overstress-induced latch-up are provided. In certain configurations, an integrated circuit (IC) or semiconductor chip includes a transient electrical overstress detection circuit that activates a transient overstress detection signal in response to detecting a transient electrical overstress event between a pair of power rails. The IC further includes mixed-signal circuits and latch-up suppression switches distributed across the IC, and the latch-up suppression switches temporarily clamp the power rails to one another in response to activation of the transient overstress detection signal to inhibit latch-up of the mixed-signal circuits.

[0005]In one aspect, an integrated circuit is provided. The integrated circuit includes a first power rail, a second power rail, one or more electrical overstress detection circuits configured to activate at least one transient overstress detection signal in response to detecting a transient electrical overstress event between the first power rail and the second power rail, a plurality of distributed mixed-signal circuits powered by the first power rail and the second power rail, and a plurality of distributed latch-up suppression switches electrically connected between the first power rail and the second power rail. Additionally, when the integrated circuit is powered, the plurality of distributed latch-up suppression switches are operable to clamp the first power rail and the second power rail in response to activation of the at least one transient overstress detection signal to inhibit latch-up of the plurality of distributed mixed-signal circuits.

[0006]In another aspect, a method of inhibiting latch-up in an integrated circuit is provided. The method includes powering a mixed-signal circuit using a first power rail and a second power rail, activating a transient overstress detection signal in response to detecting a transient electrical overstress event between the first power rail and the second power rail, turning on a latch-up suppression switch that is electrically connected between the first power rail and the second power rail in response to activation of the transient overstress detection signal, and suppressing latch-up in the mixed-signal circuit by clamping the first power rail and the second power rail using the latch-up suppression switch.

[0007]In another aspect, an interface for a semiconductor chip is provided. The interface includes a first interface pad, a second interface pad, an electrical overstress detection circuit configured to activate a transient overstress detection signal in response to detecting a transient electrical overstress event between the first power rail and the second power rail, a mixed-signal circuit configured to receive power from the first interface pad and the second interface pad, and a latch-up suppression switch electrically connected between the first interface pad the second interface pad. The latch-up suppression switch is operable to clamp the first interface pad and the second interface pad in response to activation of the transient overstress detection signal to inhibit latch-up of the mixed-signal circuit.

Problems solved by technology

Certain electronic systems can be exposed to electrical overstress events, or electrical signals of short duration having rapidly changing voltage and high power.

Electrical overstress events can damage or destroy integrated circuits (ICs) by generating overvoltage conditions and high levels of power dissipation in relatively small areas of the ICs.

High power dissipation can increase IC temperature, and can lead to numerous problems, such as gate oxide punch-through, junction damage, metal damage, and surface charge accumulation.

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