166 results about "Flag signals" patented technology

The embodiment of the invention provides a delay measurement circuit and a memory. The delay measurement circuit is applied to the delay phase-locked loop and comprises a loop mark generation circuit which is electrically connected with a loop of the delay phase-locked loop and is configured to generate a loop mark signal and input the loop mark signal to the loop of the delay phase-locked loop when loop delay measurement is carried out on the delay phase-locked loop; after the loop mark signal circulates M times in the loop of the delay phase-locked loop, a measurement ending signal is generated, a target pulse signal is generated, and the effective pulse width of the target pulse signal is equal to M times of the loop delay; wherein M is an even number greater than 1; the counting circuit is electrically connected with the loop mark generation circuit and is configured to receive a frequency division clock signal, and the effective pulse width of the target pulse signal is timed by using the frequency division clock signal to obtain a timing result; and carrying out preset processing on the timing result to obtain a loop delay measurement result of the delay-locked loop. The embodiment of the invention is at least beneficial to increasing the margin value of the delay measurement circuit and improving the accuracy of loop delay measurement.

The embodiment of the present disclosure relates to the field of semiconductor circuit design, in particular to a memory device and a ZQ calibration method, comprising: two calibration resistance interfaces connected with the same ZQ calibration resistance; a first master chip, a first slave chip, a second master chip and a second slave chip commonly connected to the ZQ calibration resistance; in the command mode, a first signal receiver is used for receiving a ZQ calibration command, a second signal receiver is used for receiving and delaying the ZQ calibration command, the first master chip and the second master chip start calibration based on the ZQ calibration command, and the first master chip and the second master chip send a ZQ flag signal through a second transmission end after completing the calibration; a third signal receiver is used for receiving the ZQ flag signal through a first transmission end, the first slave chip and the second slave chip start calibration based on the ZQ flag signal, and the first slave chip and the second slave chip send the ZQ flag signal through the second transmission end after completing the calibration, and the embodiment of the present disclosure is used for realizing theoretically unlimited number of multi-chip sharing ZQ calibration resistance.

The invention provides a test method of a switch and electronic equipment, which can be applied to the technical field of switches. The method comprises the steps that under the condition that a first interface of a mainboard and a second interface of an interface board are in a connected state, a first controller arranged on the mainboard writes a preset value into a first register of a physical layer device arranged on the interface board through a management data input and output interface, so that the physical layer device is set to be in a loopback mode, reading a first flag bit signal from a second register of the physical layer device; in response to the fact that the first flag bit signal represents that the loopback mode of the physical layer device is successfully set, the first controller generates a preset diagnosis signal and sends the preset diagnosis signal to the physical layer device; in response to the received returned preset diagnosis signal, a test result is obtained according to the signal integrity of the returned preset diagnosis signal, and the test result indicates the connection state between the mainboard and the interface board.

The invention relates to a DUT test result processing method, an error memory, a digital board card and a test machine, the method comprises the following steps: capturing comparison data sampled based on N signal lines, the comparison data corresponding to each signal line comprising leading edge comparison data and trailing edge comparison data; wherein N is a natural number greater than 0; screening the comparison data corresponding to the N signal lines to extract error data and addresses of the error data; comparing the addresses of the error data, and generating a division mark signal according to an address comparison result and the number N of the signal lines; splicing the error data, the address of the error data and the division mark signal, and storing the spliced data into a first storage unit; sending the error data and the address of the error data in the first storage unit to a second storage unit in a split-beat manner according to the split-beat mark signal; the issuing storage time of the error data is saved, and the processing efficiency of the DUT test result is improved.

A storage device including: a controller configured to be connected to an external host through an interface; a plurality of memory devices configured to store data; and a power management device configured to output an internal power voltage for an operation of the plurality of memory devices using an external power voltage received through the interface and having a flag signal pad for receiving a flag signal from the controller when the controller fails to recognize at least one of the plurality of memory devices, wherein, when the flag signal is received, the power management device changes a slope of the internal power voltage, and supplies the internal power voltage having the changed slope to the plurality of memory devices.

The invention relates to a power-off detection circuit and a power-on and power-off indication circuit. The power-off detection circuit is used for generating a power-off marking signal when the power supply voltage is in a power-off state, the on resistance of the variable resistance unit is increased along with the reduction of the power supply voltage in the power-off state so as to increase the voltage of the first node, and the current in the mirror image branch can be increased along with the increase of the voltage of the first node so as to increase the voltage of the second node. According to the power-down mark output module, when the voltage of the second node is lower than a set value, an output power-down mark signal is converted from a first level to a second level, that is, a reliable power-down mark signal is formed, and generation of the power-down mark signal is irrelevant to whether the chip is in a low-power-consumption mode or not. Therefore, the chip can be powered off stably and reliably, and related circuits can be controlled or reset by using the power-off marking signal. The power-on and power-off indicating circuit comprises the power-off detection circuit.

The invention provides an SAR sidelobe signal reconnaissance method and system based on an FPGA. The method comprises the following steps: based on a block digital baseband signal, respectively carrying out frequency modulation slope estimation and local center frequency estimation processing on a target digital baseband signal by adopting short-time Fourier transform, binarization processing, parallel Hough transform and a K-Means clustering method, and correspondingly obtaining an approximate frequency modulation slope and an approximate local center frequency; performing matched filtering and CFAR detection processing on the target digital baseband signal based on the approximate frequency modulation slope and the approximate local center frequency to obtain a target preliminary judgment result; when the target preliminary judgment result is a high flag bit signal, performing iterative search on the approximate frequency modulation slope by adopting a matched filtering method and a one-dimensional search method to obtain a final frequency modulation slope; and obtaining the pulse repetition period of the target by using the final frequency modulation slope and the approximate local center frequency. The real-time processing capability is improved, and the reconnaissance precision is improved.

The present disclosure provides an error checking circuit, comprising: a first generation circuit for generating a read command; and the control circuit is used for reading conventional data in the storage array based on the read command, generating corresponding second verification data based on the conventional data, comparing the second verification data with initial verification data corresponding to the conventional data, and if the second verification data is different from the initial verification data, sending the second verification data to the storage array. If yes, generating an error flag signal of the first state; the second generation circuit is used for receiving the error flag signal and generating a write command based on the error flag signal in the first state; the control circuit is further used for replacing the initial verification data with the second verification data based on the write command.

The embodiment of the present disclosure relates to the field of semiconductor circuit design, in particular to a memory device and a ZQ calibration method, comprising: two calibration resistance interfaces connected with the same ZQ calibration resistance; a first master chip, a plurality of cascaded first slave chips, a second master chip and a plurality of cascaded second slave chips connected with the ZQ calibration resistance, and a first transmission end and a second transmission end used for transmitting a ZQ flag signal; a recognition module used for recognizing a priority calibration chip, a delay calibration chip, a master-slave chip cascaded with the priority calibration chip, and a secondary slave chip cascaded with the delay calibration chip; in a command mode, the priority calibration chip starts calibration based on a ZQ calibration command, the delay calibration chip starts calibration based on a delayed ZQ calibration command, and after calibration is completed, the ZQ flag signal is sent through the second transmission end; and the master-slave chip and the secondary slave chip start calibration based on the ZQ flag signal, so as to realize theoretically unlimited number of multi-chip sharing the ZQ calibration resistance.

The present disclosure provides a voltage generating circuit and a memory. The voltage generating circuit includes: a voltage output module configured to receive a reference voltage, generate a first output voltage, and provide the first output voltage to a power supply node, where the power supply node is connected to a load to supply power to the load; a voltage stabilizing module configured to receive the reference voltage and generate and output a control signal; and a compensation module configured to receive a power voltage, a flag signal and the control signal, be turned on in response to the flag signal, and configured to provide a second output voltage to the power supply node in response to a voltage value of the control signal, such that a voltage of the power supply node is recovered to the first output voltage.

The invention provides a traffic shaping method and device, a medium and an electronic terminal. The traffic shaping method comprises the following steps: acquiring a queue request signal; based on a traffic shaping mode of a queue in a port in the vehicle-mounted system, a counter corresponding to the traffic shaping mode is allocated to the queue, the counter is a credit counter or a token counter, and the counter supports deficit and can store the maximum packet length supported by a plurality of vehicle-mounted systems; and based on the counter, traffic shaping is performed on a request queue associated with the queue request signal, and a credit increment or a token bucket increment of the request queue is increased once every a fixed time period through a marking signal. According to the traffic shaping method, traffic shaping is carried out on the basis of the counter, so that the traffic shaping precision can be improved. And the traffic shaping method based on the credit and the token is supported in the vehicle-mounted system, so that the traffic shaping of the vehicle-mounted system is more flexible.

This application provides a high-voltage maintenance method, system, and product for OTA upgrades. The method includes: applying to a takeover controller, wherein the takeover controller is equipped with a high-voltage redundancy control program; the method includes: responding to an upgrade flag signal indicating that a target domain controller is performing an OTA upgrade, and, if it can receive a high-voltage switch signal, sending a high-voltage takeover ready signal to the target domain controller within a first duration; if it is determined that the target domain controller is not performing high-voltage control, performing high-voltage control on the vehicle according to the received high-voltage switch signal; if it is determined that the target domain controller stops sending high-voltage control commands within a second duration, sending a high-voltage control command within a third duration to take over the high-voltage control of the vehicle; and, while taking over the high-voltage control of the vehicle, continuously sending a high-voltage takeover status signal to the target domain controller to control the target domain controller to perform an OTA upgrade. The aim is to maintain high voltage on the vehicle during an OTA upgrade of the domain controller.

A memory circuit includes a compute in-memory (CIM) array. The CIM array includes a memory cell array configured to store a first set of data. The first set of data including a first set of weights or a second set of data. The first set of data being exponent portions of corresponding floating point numbers. The second set of data being a compressed version of the first set of weights. The first set of weights having a first data length, and the second set of data having a second data length less than the first data length. The CIM array further includes a decoder coupled to the memory cell array, and being configured to generate a first set of output signals in response to a first set of input signals, the first set of data and a flag signal.

The invention provides an attitude control energy optimization method for a spacecraft. The attitude control energy optimization method comprises the following steps: firstly, obtaining a smoothed attitude angle instruction and an attitude angle rate instruction by using a tracking differentiator; estimating impact disturbance through a nonlinear extended state observer; forming an impact disturbance sign signal according to the estimated value; obtaining a state error, establishing an attitude control law under a non-interference condition and an attitude control law under impact disturbance, and obtaining a corresponding control quantity and a sliding mode surface; according to the state error and the two attitude control laws, the switching compensation control quantity is calculated, the attitude control law under the impact disturbance containing integral switching compensation control is designed, and the smoothed control quantity under the impact disturbance is obtained; according to the impact disturbance mark signal, the control quantity under the interference-free condition or the control quantity under the smooth impact disturbance is selected and sent to the attitude control engine. The method effectively solves the energy optimization problem of the direct force control system when the parameters of the control system change drastically under large impact disturbance.

The application discloses a double-edge triggered asynchronous Gray code counter, wherein a first stage trigger Rise1 is used as a rising edge triggered D trigger, and the rest of the stage triggers Fall1, Fall2 and Fall3 are used as falling edge triggered D triggers. The application solves the problem that the utilization of clock frequency is not maximized due to the generation of the first stage flag signal in the existing Gray code counter.

Aspects of the disclosure are directed to a test mode save and restore operation. In accordance with one aspect, the disclosure includes a hold latch cell configured to execute a save directive for a first operational state of a digital logic system and to execute a restore directive for the first operational state in the digital logic system in an operational mode; a first multiplexer coupled to the hold latch cell, the first multiplexer configured to execute a test sequence on the digital logic system in a test mode; and a logical XOR circuit coupled to the hold latch cell, the logical XOR circuit configured to perform a fault detection on the save directive and the restore directive to generate an error flag signal.

The application discloses a cascaded processing method of a millimeter wave chip, a data transmission interface, equipment and a medium. The method comprises the following steps: obtaining target data from a front-stage chip or a rear-stage chip, and storing the target data into a data storage unit; determining a target data transmission mode based on a chip type of the rear-stage chip; adjusting target enabling modes of a data signal line, an effective flag signal line, a clock signal line and a reset signal line respectively based on the target data transmission mode through a register management unit, and enabling each signal line in a physical IO interface based on the corresponding target enabling mode, so as to transmit the target data to the rear-stage chip or the front-stage chip. According to the scheme provided in the embodiment of the application, the actual data transmission requirements of different rear-stage chip types are different, the target enabling modes of each signal line of the data transmission interface are adaptively adjusted based on the rear-stage chip type, and therefore the application flexibility of the millimeter wave cascaded chip is improved.

This invention discloses a fault handling method based on a dual-core lockstep processor. The dual-core lockstep processor includes a master processor and a slave processor. The dual-core lockstep processor receives data from the last four stages of the processor's pipeline via a fault detection module, outputting a fault flag signal and a fault program pointer. A front-end fault handling module receives the fault flag signal and the fault program pointer, performing a pipeline-level rollback. A back-end fault handling module controls the handshake and selection signals of the last four stages of the pipeline and executes a virtual write-back fault-tolerance mechanism, managing the operating status of the last four stages of the pipeline and the instruction fetch stage pipeline. This prevents data conflicts during superscalar processor fault handling, thereby achieving full coverage of fault handling while maintaining low time and area overhead, and simultaneously achieving high performance and high reliability. This invention can be widely applied in the field of dual-core lockstep processors.

This application provides a testing method and electronic device for a switch, applicable to the field of switch technology. The method includes: when a first interface on the motherboard and a second interface on an interface board are connected, a first controller on the motherboard writes a preset value to a first register of a physical layer device on the interface board via a management data input / output interface to set the physical layer device to loopback mode, and reads a first flag signal from a second register of the physical layer device; in response to the first flag signal indicating successful loopback mode setting of the physical layer device, the first controller generates a preset diagnostic signal and sends the preset diagnostic signal to the physical layer device; in response to receiving the returned preset diagnostic signal, a test result is obtained based on the signal integrity of the returned preset diagnostic signal, the test result indicating the connection status between the motherboard and the interface board.

Motor closed-loop detection circuit and method are provided. The circuit includes: motor open-loop path for providing open-loop angle increment and calculating open-loop angle; motor prediction path for estimating motor's angle increment to obtain estimated angle increment and calculating estimated angle; and closed-loop detection module for outputting first closed-loop flag signal when the open-loop angle increment equals the estimated angle increment n consecutive times within an electrical cycle feeding back the first closed-loop flag signal to the motor open-loop path to adjust the open-loop angle increment, and outputting second closed-loop flag signal when the updated open-loop angle equals the estimated angle. The hardware circuit and existing motor paths reuse simplify the design, reduce costs, and minimize CPU load and power consumption. Shared components across modules from a computing library save costs. The method is simple, fast, and easy to implement. A same circuit achieves dual-level closed-loop functionality with minimal area consumption.

The invention discloses an embedded multimedia card host device and a loopback test method thereof, and relates to the technical field of embedded multimedia card host devices. The embedded multimedia card host device comprises a loopback test control circuit which generates first pseudo-random sequence data and a data strobe signal corresponding to a first transmission mode, and verifies loopback test data according to a third clock signal to generate a flag signal; the transmitter circuit samples the two according to a transmission clock signal so as to output second pseudorandom sequence data and the first clock signal; the receiver circuit receives the first pseudo-random sequence data and the second pseudo-random sequence data through the input / output interface and outputs the third pseudo-random sequence data and the second clock signal; the delay phase-locked loop outputs the second clock signal as a receiving clock signal; the demultiplexer is used for processing the third pseudorandom sequence data according to the received clock signal so as to generate loopback test data; and a delay circuit which delays the receiving clock signal to generate a third clock signal.

The present application provides an asynchronous FIFO data transmission method and an asynchronous FIFO data buffer for data transmission between a write user side and a read user side. The method includes: when performing data transmission, obtaining the configuration bit of the asynchronous FIFO, if the configuration bit is equal to a first configuration value, the read user side detects whether there is an error in the data read by the read side FIFO, if there is erroneous data, then the reading of the data is stopped, and the read user side feeds back an error flag signal to the write user side; the error flag signal includes at least a pause signal and a read address corresponding to the erroneous data; the write user side pauses the writing of the write side FIFO according to the pause signal, and transmits the corresponding correct data according to the read address corresponding to the erroneous data to replace the erroneous data. The present application can improve the efficiency and accuracy of data transmission by detecting the erroneous data of the read side FIFO and retransmitting the corresponding erroneous data.

The application belongs to the technical field of simulation modeling, and discloses a power electronic converter simulation method and system based on a binary resistance model. c (k), then in stage 2, the predicted half-bridge natural switching state combination and the flag signal flag(k) and the real half-bridge natural switching state combination sigma hd (k) are sequentially updated. Finally, in stage 3, the combination of vectors flag(k), sigma hd (k) and the state vector x(k) is completed. The above method can accurately identify the state combination switching time of the natural switching half-bridge, and only needs to update the half-bridge natural switching state combination through simple logical operation, and only needs to calculate the state equation once in the whole calculation process, so that the modeling calculation amount is extremely low.

The application discloses a random memory and a testing device. The random memory comprises a clock transmission link and a second duty cycle detection circuit. The clock transmission link comprises a duty cycle adjustment circuit and a first duty cycle detection circuit. The duty cycle adjustment circuit is used for duty cycle adjustment on an input first clock signal to obtain a second clock signal. The first duty cycle detection circuit is used for first duty cycle detection on the second clock signal and feedback of a detection result to the duty cycle adjustment circuit. The second duty cycle detection circuit is coupled to an output end of the clock transmission link, used for second duty cycle detection on the second clock signal and output of a detection flag signal. The detection precision of the second duty cycle detection circuit is higher than that of the first duty cycle detection circuit. In this way, the detection problem of the frequency performance of the random memory is solved.

A memory circuit includes a compute in-memory (CIM) array. The CIM array includes a memory cell array configured to store a first set of data. The first set of data including a first set of weights or a second set of data. The first set of data being exponent portions of corresponding floating point numbers. The second set of data being a compressed version of the first set of weights. The first set of weights having a first data length, and the second set of data having a second data length less than the first data length. The CIM array further includes a decoder coupled to the memory cell array, and being configured to generate a first set of output signals in response to a first set of input signals, the first set of data and a flag signal.

The present application discloses a water-cooled temperature control system and method, which relates to the technical field of domain controller cooling. The water-cooled temperature control system includes: a domain control unit, which is used to periodically send the SOC temperature, and is also used to send an OTA start flag signal when receiving an OTA instruction; a cooling control module is used to feedback confirmation information when receiving the OTA start flag signal, and obtain the last received SOC temperature before receiving the feedback confirmation information as the initial temperature, and start a non-real-time water-cooled temperature control program; the non-real-time water-cooled temperature control program is: obtain the initial flow rate and the flow duration corresponding to the initial temperature, and use them as the water pump control parameters based on the pre-stored mapping table, and when the running time of the water pump at the initial flow rate value exceeds the flow duration, use a fixed flow rate as the water pump control parameter. The present application can enable the domain controller to work in a healthy temperature environment, improve the reliability and stability of the SOC chip, and the OTA upgrade success rate.

The application discloses a logic acceleration circuit and method of high-speed capacitive SAR ADC. The logic acceleration circuit comprises a two-way selector, a latch, a comparator and an adaptive asynchronous clock generator. The two-way selector is used for selecting the output latch result and the comparator result and is connected to the switch of the control capacitor array analog-digital converter (CDAC). The latch is used for latching the comparator result and is connected to the two-way selector. The comparator is used for comparing the output value of the CDAC with a reference voltage V ref , and outputting the comparison result. The comparison result is output to the two-way selector. After the comparison is completed, a comparison completion flag signal is output to the adaptive asynchronous clock generator. The adaptive asynchronous clock generator comprises a delay module DELAY and a plurality of NAND gates and NOT gates and is used for controlling the successive approximation steps. The application accelerates the logic operation, and each bit operation can be accelerated.

This disclosure relates to the field of integrated circuit technology, and more particularly to a hot-plug detection circuit, a control chip, and an electronic device. The input terminal of the hot-plug detection circuit is connected to the transmitting end of a signal transmission link. The signal transmission link includes a transmitting end, a transmission line, and a receiving end. The transmission line is pluggable to both the transmitting end and the receiving end. The hot-plug detection circuit is used to: determine a second differential positive voltage based on the difference between a first differential positive voltage and a first preset voltage at the transmitting end; determine a second differential negative voltage based on the difference between a first differential negative voltage and a second preset voltage; and generate a hot-plug flag signal based on the second differential positive voltage and the second differential negative voltage. The hot-plug detection circuit of this disclosure does not occupy additional port resources, is compatible with both DC-coupled and AC-coupled transmission, and can detect both insertion and removal of the transmission line at the transmitting end and at the receiving end.

Certain aspects of the present disclosure are directed towards a current assessment circuit. The current assessment circuit generally includes: a comparison circuit configured to compare a current associated with a voltage regulator with a current track threshold to yield a state flag signal; a duty cycle detection circuit configured to detect a duty cycle of the state flag signal; and a controller configured to adjust the current track threshold to assess a first average of the current based on the duty cycle of the state flag signal, wherein the current track threshold is adjusted by an amount based on the duty cycle.

The invention discloses a memory circuit and an operation method thereof. The memory circuit comprises a memory internal computing (CIM) array. The CIM array includes an array of memory cells for storing a first set of data. The first data set comprises a first weight set or a second data set. The first data set is an exponential portion of a corresponding floating-point number. The second set of data is a compressed version of the first set of weights. The first set of weights has a first data length, and the second set of data has a second data length less than the first data length. The CIM array further includes a decoder coupled to the array of memory cells and configured to generate a first set of output signals in response to the first set of input signals, the first set of data, and the flag signal. According to the memory circuit, the processing capacity executed by the memory circuit can be reduced, and the power efficiency can be improved.