102 results about "Flag signals" patented technology

The embodiment of the invention provides a delay measurement circuit and a memory. The delay measurement circuit is applied to the delay phase-locked loop and comprises a loop mark generation circuit which is electrically connected with a loop of the delay phase-locked loop and is configured to generate a loop mark signal and input the loop mark signal to the loop of the delay phase-locked loop when loop delay measurement is carried out on the delay phase-locked loop; after the loop mark signal circulates M times in the loop of the delay phase-locked loop, a measurement ending signal is generated, a target pulse signal is generated, and the effective pulse width of the target pulse signal is equal to M times of the loop delay; wherein M is an even number greater than 1; the counting circuit is electrically connected with the loop mark generation circuit and is configured to receive a frequency division clock signal, and the effective pulse width of the target pulse signal is timed by using the frequency division clock signal to obtain a timing result; and carrying out preset processing on the timing result to obtain a loop delay measurement result of the delay-locked loop. The embodiment of the invention is at least beneficial to increasing the margin value of the delay measurement circuit and improving the accuracy of loop delay measurement.

The embodiment of the present disclosure relates to the field of semiconductor circuit design, in particular to a memory device and a ZQ calibration method, comprising: two calibration resistance interfaces connected with the same ZQ calibration resistance; a first master chip, a first slave chip, a second master chip and a second slave chip commonly connected to the ZQ calibration resistance; in the command mode, a first signal receiver is used for receiving a ZQ calibration command, a second signal receiver is used for receiving and delaying the ZQ calibration command, the first master chip and the second master chip start calibration based on the ZQ calibration command, and the first master chip and the second master chip send a ZQ flag signal through a second transmission end after completing the calibration; a third signal receiver is used for receiving the ZQ flag signal through a first transmission end, the first slave chip and the second slave chip start calibration based on the ZQ flag signal, and the first slave chip and the second slave chip send the ZQ flag signal through the second transmission end after completing the calibration, and the embodiment of the present disclosure is used for realizing theoretically unlimited number of multi-chip sharing ZQ calibration resistance.

The invention relates to a DUT test result processing method, an error memory, a digital board card and a test machine, the method comprises the following steps: capturing comparison data sampled based on N signal lines, the comparison data corresponding to each signal line comprising leading edge comparison data and trailing edge comparison data; wherein N is a natural number greater than 0; screening the comparison data corresponding to the N signal lines to extract error data and addresses of the error data; comparing the addresses of the error data, and generating a division mark signal according to an address comparison result and the number N of the signal lines; splicing the error data, the address of the error data and the division mark signal, and storing the spliced data into a first storage unit; sending the error data and the address of the error data in the first storage unit to a second storage unit in a split-beat manner according to the split-beat mark signal; the issuing storage time of the error data is saved, and the processing efficiency of the DUT test result is improved.

The invention provides an SAR sidelobe signal reconnaissance method and system based on an FPGA. The method comprises the following steps: based on a block digital baseband signal, respectively carrying out frequency modulation slope estimation and local center frequency estimation processing on a target digital baseband signal by adopting short-time Fourier transform, binarization processing, parallel Hough transform and a K-Means clustering method, and correspondingly obtaining an approximate frequency modulation slope and an approximate local center frequency; performing matched filtering and CFAR detection processing on the target digital baseband signal based on the approximate frequency modulation slope and the approximate local center frequency to obtain a target preliminary judgment result; when the target preliminary judgment result is a high flag bit signal, performing iterative search on the approximate frequency modulation slope by adopting a matched filtering method and a one-dimensional search method to obtain a final frequency modulation slope; and obtaining the pulse repetition period of the target by using the final frequency modulation slope and the approximate local center frequency. The real-time processing capability is improved, and the reconnaissance precision is improved.

The present disclosure provides an error checking circuit, comprising: a first generation circuit for generating a read command; and the control circuit is used for reading conventional data in the storage array based on the read command, generating corresponding second verification data based on the conventional data, comparing the second verification data with initial verification data corresponding to the conventional data, and if the second verification data is different from the initial verification data, sending the second verification data to the storage array. If yes, generating an error flag signal of the first state; the second generation circuit is used for receiving the error flag signal and generating a write command based on the error flag signal in the first state; the control circuit is further used for replacing the initial verification data with the second verification data based on the write command.

The embodiment of the present disclosure relates to the field of semiconductor circuit design, in particular to a memory device and a ZQ calibration method, comprising: two calibration resistance interfaces connected with the same ZQ calibration resistance; a first master chip, a plurality of cascaded first slave chips, a second master chip and a plurality of cascaded second slave chips connected with the ZQ calibration resistance, and a first transmission end and a second transmission end used for transmitting a ZQ flag signal; a recognition module used for recognizing a priority calibration chip, a delay calibration chip, a master-slave chip cascaded with the priority calibration chip, and a secondary slave chip cascaded with the delay calibration chip; in a command mode, the priority calibration chip starts calibration based on a ZQ calibration command, the delay calibration chip starts calibration based on a delayed ZQ calibration command, and after calibration is completed, the ZQ flag signal is sent through the second transmission end; and the master-slave chip and the secondary slave chip start calibration based on the ZQ flag signal, so as to realize theoretically unlimited number of multi-chip sharing the ZQ calibration resistance.

A memory circuit includes a compute in-memory (CIM) array. The CIM array includes a memory cell array configured to store a first set of data. The first set of data including a first set of weights or a second set of data. The first set of data being exponent portions of corresponding floating point numbers. The second set of data being a compressed version of the first set of weights. The first set of weights having a first data length, and the second set of data having a second data length less than the first data length. The CIM array further includes a decoder coupled to the memory cell array, and being configured to generate a first set of output signals in response to a first set of input signals, the first set of data and a flag signal.

The invention provides an attitude control energy optimization method for a spacecraft. The attitude control energy optimization method comprises the following steps: firstly, obtaining a smoothed attitude angle instruction and an attitude angle rate instruction by using a tracking differentiator; estimating impact disturbance through a nonlinear extended state observer; forming an impact disturbance sign signal according to the estimated value; obtaining a state error, establishing an attitude control law under a non-interference condition and an attitude control law under impact disturbance, and obtaining a corresponding control quantity and a sliding mode surface; according to the state error and the two attitude control laws, the switching compensation control quantity is calculated, the attitude control law under the impact disturbance containing integral switching compensation control is designed, and the smoothed control quantity under the impact disturbance is obtained; according to the impact disturbance mark signal, the control quantity under the interference-free condition or the control quantity under the smooth impact disturbance is selected and sent to the attitude control engine. The method effectively solves the energy optimization problem of the direct force control system when the parameters of the control system change drastically under large impact disturbance.

The application discloses a double-edge triggered asynchronous Gray code counter, wherein a first stage trigger Rise1 is used as a rising edge triggered D trigger, and the rest of the stage triggers Fall1, Fall2 and Fall3 are used as falling edge triggered D triggers. The application solves the problem that the utilization of clock frequency is not maximized due to the generation of the first stage flag signal in the existing Gray code counter.

Aspects of the disclosure are directed to a test mode save and restore operation. In accordance with one aspect, the disclosure includes a hold latch cell configured to execute a save directive for a first operational state of a digital logic system and to execute a restore directive for the first operational state in the digital logic system in an operational mode; a first multiplexer coupled to the hold latch cell, the first multiplexer configured to execute a test sequence on the digital logic system in a test mode; and a logical XOR circuit coupled to the hold latch cell, the logical XOR circuit configured to perform a fault detection on the save directive and the restore directive to generate an error flag signal.

This invention discloses a fault handling method based on a dual-core lockstep processor. The dual-core lockstep processor includes a master processor and a slave processor. The dual-core lockstep processor receives data from the last four stages of the processor's pipeline via a fault detection module, outputting a fault flag signal and a fault program pointer. A front-end fault handling module receives the fault flag signal and the fault program pointer, performing a pipeline-level rollback. A back-end fault handling module controls the handshake and selection signals of the last four stages of the pipeline and executes a virtual write-back fault-tolerance mechanism, managing the operating status of the last four stages of the pipeline and the instruction fetch stage pipeline. This prevents data conflicts during superscalar processor fault handling, thereby achieving full coverage of fault handling while maintaining low time and area overhead, and simultaneously achieving high performance and high reliability. This invention can be widely applied in the field of dual-core lockstep processors.

This application provides a testing method and electronic device for a switch, applicable to the field of switch technology. The method includes: when a first interface on the motherboard and a second interface on an interface board are connected, a first controller on the motherboard writes a preset value to a first register of a physical layer device on the interface board via a management data input / output interface to set the physical layer device to loopback mode, and reads a first flag signal from a second register of the physical layer device; in response to the first flag signal indicating successful loopback mode setting of the physical layer device, the first controller generates a preset diagnostic signal and sends the preset diagnostic signal to the physical layer device; in response to receiving the returned preset diagnostic signal, a test result is obtained based on the signal integrity of the returned preset diagnostic signal, the test result indicating the connection status between the motherboard and the interface board.

Motor closed-loop detection circuit and method are provided. The circuit includes: motor open-loop path for providing open-loop angle increment and calculating open-loop angle; motor prediction path for estimating motor's angle increment to obtain estimated angle increment and calculating estimated angle; and closed-loop detection module for outputting first closed-loop flag signal when the open-loop angle increment equals the estimated angle increment n consecutive times within an electrical cycle feeding back the first closed-loop flag signal to the motor open-loop path to adjust the open-loop angle increment, and outputting second closed-loop flag signal when the updated open-loop angle equals the estimated angle. The hardware circuit and existing motor paths reuse simplify the design, reduce costs, and minimize CPU load and power consumption. Shared components across modules from a computing library save costs. The method is simple, fast, and easy to implement. A same circuit achieves dual-level closed-loop functionality with minimal area consumption.

A memory circuit includes a compute in-memory (CIM) array. The CIM array includes a memory cell array configured to store a first set of data. The first set of data including a first set of weights or a second set of data. The first set of data being exponent portions of corresponding floating point numbers. The second set of data being a compressed version of the first set of weights. The first set of weights having a first data length, and the second set of data having a second data length less than the first data length. The CIM array further includes a decoder coupled to the memory cell array, and being configured to generate a first set of output signals in response to a first set of input signals, the first set of data and a flag signal.

The application discloses a logic acceleration circuit and method of high-speed capacitive SAR ADC. The logic acceleration circuit comprises a two-way selector, a latch, a comparator and an adaptive asynchronous clock generator. The two-way selector is used for selecting the output latch result and the comparator result and is connected to the switch of the control capacitor array analog-digital converter (CDAC). The latch is used for latching the comparator result and is connected to the two-way selector. The comparator is used for comparing the output value of the CDAC with a reference voltage V ref , and outputting the comparison result. The comparison result is output to the two-way selector. After the comparison is completed, a comparison completion flag signal is output to the adaptive asynchronous clock generator. The adaptive asynchronous clock generator comprises a delay module DELAY and a plurality of NAND gates and NOT gates and is used for controlling the successive approximation steps. The application accelerates the logic operation, and each bit operation can be accelerated.

This disclosure relates to the field of integrated circuit technology, and more particularly to a hot-plug detection circuit, a control chip, and an electronic device. The input terminal of the hot-plug detection circuit is connected to the transmitting end of a signal transmission link. The signal transmission link includes a transmitting end, a transmission line, and a receiving end. The transmission line is pluggable to both the transmitting end and the receiving end. The hot-plug detection circuit is used to: determine a second differential positive voltage based on the difference between a first differential positive voltage and a first preset voltage at the transmitting end; determine a second differential negative voltage based on the difference between a first differential negative voltage and a second preset voltage; and generate a hot-plug flag signal based on the second differential positive voltage and the second differential negative voltage. The hot-plug detection circuit of this disclosure does not occupy additional port resources, is compatible with both DC-coupled and AC-coupled transmission, and can detect both insertion and removal of the transmission line at the transmitting end and at the receiving end.

Certain aspects of the present disclosure are directed towards a current assessment circuit. The current assessment circuit generally includes: a comparison circuit configured to compare a current associated with a voltage regulator with a current track threshold to yield a state flag signal; a duty cycle detection circuit configured to detect a duty cycle of the state flag signal; and a controller configured to adjust the current track threshold to assess a first average of the current based on the duty cycle of the state flag signal, wherein the current track threshold is adjusted by an amount based on the duty cycle.

This invention relates to a thin-film leakage current testing system, comprising a test voltage source that applies current to the thin film under test; a multi-stage current measurement unit, with its input connected to the thin film under test and its output connected to a window comparator; a window comparator used to define the linear output region of each stage unit and generate a flag signal; a pure hardware decision and gating circuit, composed of high-speed logic gates, which makes decisions according to the flag signal and preset priority to achieve seamless range switching and output gating; and a data output interface that transmits the collected leakage current and voltage data to an external device in a preset format. This invention integrates a multi-stage current measurement unit, a window comparator, and a pure hardware decision circuit, eliminating the need for combining multiple instruments and complex synchronous calibration. Users only need to connect the thin film and apply voltage; the system can automatically complete seamless measurements across the entire range, from weak leakage current to large breakdown current, significantly reducing setup barriers and operational complexity, and improving testing efficiency and result consistency.

The application discloses an embedded multimedia memory card and a monitoring system and method for data transmission thereof, and belongs to the technical field of data storage. The system comprises an address monitoring unit, a data monitoring unit, an expected value buffer unit and a comparison unit. The address monitoring unit is connected in parallel to an address channel and a write control channel of a transmission bus of the embedded multimedia memory card, and outputs a trigger signal when the write control channel is a write operation and a current address on the address channel belongs to a preset target address range. The data monitoring unit is connected in parallel to a write data channel of the transmission bus of the embedded multimedia memory card, and is used for acquiring actual write data of the write data channel when the trigger signal is acquired. The expected value buffer unit is used for storing expected data corresponding to the preset target address range. The comparison unit is used for comparing the actual write data with the target expected data in real time, and outputting an error flag signal in each clock cycle according to a comparison result.

The application discloses a microphone pre-AFE circuit with a listening wake-up function and belongs to the technical field of microphones. The microphone pre-AFE circuit comprises a microphone equivalent model, the output end of the microphone equivalent model is connected with a high-resistance biasing circuit and a listening wake-up circuit, the output end of the high-resistance biasing circuit is connected with an operational amplifier module, and the output end of the operational amplifier module is connected with a post-stage circuit. The operational amplifier module amplifies or attenuates the microphone signal in proportion through the feedback of a variable capacitor. When the microphone pre-AFE circuit is in a normal working mode, only the operational amplifier module works normally, and the listening wake-up circuit does not work. When the microphone pre-AFE circuit enters a listening standby mode, the operational amplifier module does not work, the microphone pre-AFE circuit maintains the listening wake-up circuit with a power consumption lower than that in the normal working mode, and the operational amplifier module amplifies the microphone signal when the listening wake-up circuit outputs a high FLAG signal. The application can realize lower power consumption and noise.

This invention discloses an image decoding system with anomaly detection and self-recovery mechanisms, belonging to the field of image processing technology. The system receives compressed data and sends decoded data through an external interface, and an external storage module caches the compressed and decoded data. The decoding module reads compressed data frame by frame to achieve frame-by-frame decompression, and uses a frame header flag signal and decoding timeout mechanism to achieve frame reset, clearing residual decoding state from the previous frame to achieve self-recovery of the decoding state during the frame cycle. During decoding, the system verifies the bitstream length information and counts the number of decoded pixels in real time, performing padding or discarding operations based on abnormal numbers to minimize the decoding error range. The anomaly diagnosis module performs anomaly reset based on the anomaly detection field of the decoding module when the system's abnormal state meets the reset conditions. This invention achieves anomaly detection and self-recovery "seamlessly" during decoding, providing an efficient, stable, and reliable decoding solution for scenarios with stringent real-time requirements, such as streaming media and remote sensing satellite imagery.

Circuits and methods for determining the characteristics of swappable pins in a peripheral in a 1-Wire or similar single-conductor system, thereby allowing each one of two pins to be either an I / O pin (connected to an I / O line) or a CAP pin (connected to a storage capacitor). Embodiments may utilize a hybrid buffer circuit that utilizes an effectively bi-directional PFET pull-up device coupled between the swappable pins A and B. Two open-drain NFETs pull-down devices are used, one on either side of the PFET and coupled to a respective pin (A or B), but with only one NFET being selected to be operable based on pin-determination flag signals from the pin detection circuitry. Such a hybrid buffer circuit would consume significantly less IC area than two complete conventional buffers, resulting in less leakage and less yield loss.

The application discloses a device monitoring method and electronic equipment, and relates to the technical field of device monitoring. The method comprises the following steps: in response to the power-on of an interconnection management device, a logic controller acquires a plurality of state detection signals related to the reset process of an interconnection controller; the logic controller generates a firmware loading flag signal based on the plurality of state detection signals, so as to be read by the management controller; in response to the fact that the firmware loading flag signal read by the management controller represents valid loading, the management controller accesses the interconnection controller to perform interconnection state monitoring after a preset waiting period. The application can take into account the differences in the architecture of the interconnection controller, control the access timing of the management controller to the interconnection controller, thereby avoiding the device monitoring method of the premature access of the management controller to the interconnection controller, and solving the problem that, in the related art, the premature access of the management controller to the interconnection controller leads to abnormal firmware loading of the interconnection manager, thereby leading to link training failure.

The application discloses a closed space unmanned system positioning method under external interference and relates to the technical field of unmanned system positioning. The application accurately identifies abnormal interference by using the detection mechanism of the extended sign signal design, and accurately estimates the positioning of the unmanned system by using the forward filtering and backward smoothing based on the generalized statistics. The application can realize high-precision positioning of the unmanned system in a complex scene where the error characteristics of wireless measurement signals present non-Gaussian coupling unknown interference, reduces the influence of unknown external disturbance and non-Gaussian noise on the positioning effect, improves the positioning accuracy of the unmanned system in indoor, downhole, basement and other closed and limited spaces, guarantees the normal operation of the unmanned system, and realizes the task target.

A semiconductor apparatus comprises a memory region, generates an invalid access flag signal indicating an invalid access to the memory region based on a row address signal input with a read command, and blocks data output in response to the invalid access flag signal.

The application discloses a timing control circuit of a display device and the display device, wherein the timing control circuit of the display device comprises a frequency detection circuit, a cache circuit and a clock generation circuit; the frequency detection circuit is configured to perform frequency detection on a synchronization signal corresponding to image data sent by an image processor to obtain a frequency flag signal, and the frequency flag signal represents a frame rate of the image data; the cache circuit is configured to cache the image data; and the clock generation circuit is coupled to the frequency detection circuit and is configured to generate a target pixel clock according to the frequency flag signal, and the target pixel clock is used to make a display panel display the image data at a refresh rate corresponding to the target pixel clock. In this way, the frame rate of the image data can be dynamically detected, the refresh rate of the display panel can be dynamically updated / switched, the power consumption of the timing control circuit can be reduced, and the matching between the frame rate and the refresh rate can be realized.

A memory device includes: a memory cell region including normal cells coupled to normal column selection lines, and row-hammer cells and redundancy cells respectively coupled to redundancy column selection lines; a repair control circuit configured to provide repair addresses and row-hammer flag signals, corresponding to repair information, according to a row address; and a column control circuit configured to activate at least one of the redundancy column selection lines according to the row-hammer flag signals or a comparison result of a column address and the repair addresses.

Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S / P) decoder coupled to a respective bus and to the common register. The S / P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S / P decoders.

This invention relates to an improved QC-LDPC decoder that eliminates wait cycles, belonging to the field of communication technology. It includes a posterior message storage module, a -C2V FIFO, a C2V_RAM, a V2C_signs FIFO, a permutation module, a calculation module, a FIFO buffer module, a C2V message recovery module, and an inverse permutation module. The posterior message storage module includes two real dual-port RAMs, llr_ram_0 and llr_ram_1. This invention reduces computational complexity, eliminates the need for calculating and storing flag signals, improves system flexibility, and eliminates wait cycles, thereby increasing system throughput. By using two real dual-port RAMs for ping-pong access to initial channel information and updated node posterior probability information, it saves inter-frame initial channel message buffering time, further improving system throughput and demonstrating good hardware utilization.

Embodiments of the present application provide a source driver, a driving method, a display driving system and method, and a display device. The source driver comprises: a driving signal output unit, configured to output a driving signal to a source output line and enter a high-impedance state in response to a high-impedance state control instruction; a high-impedance state flag generation circuit, coupled to the driving signal output unit, configured to generate a high-impedance state flag signal synchronized with a time when the driving signal output unit enters the high-impedance state; and a flag signal output unit, configured to output the high-impedance state flag signal. The technical solution of the embodiments of the present application can eliminate the driving voltage coupling error caused by the mismatch between the high-impedance state window and the multiplexing switch switching timing.