465 results about "Flag signals" patented technology

There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not a memory block of an inputted block address is a multi-bit memory block according to the stored multi-bit/single-bit information and outputting an appropriate flag signal. A read/write circuit for selectively performing multi-bit and single-bit read/program operations of the memory block corresponding to the block address is also included, as well as control logic for controlling the read/write circuit such that the read/write circuit can perform multi-bit or single-bit read/program operations based on the flag signal. An error checking and correction (ECC) circuit including a multi-bit ECC unit and a single-bit ECC unit for checking and correcting an error in a data of the read/write circuit can also be included.

In an error-correcting decoder, in which an input digital signal including reliability information is decoded by using a Viterbi algorithm as a first decoding process and a final decoded result is obtained by block-code decoding as a second decoding process, a flag signal is added to a location where a value of reliability of path metric determined by the Viterbi algorithm is lower than a threshold, as an original flagged location. A flag signal adding unit continuously adds flag signals to locations, from the original flagged location to locations preceding the originally flagged location, after back tracing. The flagged locations are then regarded as erasure locations in the block-code decoding process.

Some synchronous semiconductor memory devices accept a command clock which is buffered and a write clock which is unbuffered. Write command are synchronized to the command clock while the associated write data is synchronized to the write clock. Due to the use of the buffer, an arbitrary phase shift can exist between the command and write clocks. The presence of the phase shift between the two clocks makes it difficult to determine when a memory device should accept write data associated a write command. A synchronous memory device in accordance with the present invention utilizes the unbuffered strobe signal which is normally tristated during writes as a flag to mark the start of write data. A preamble signal may be asserted on the strobe signal line prior to asserting the flag signal in order to simplify flag detection.

The input data at address 0 is “00000000”, including many “0”s. The data at address 0 is inverted to “11111111”. At the same time, flag information “1” indicative of inversion is written into the flag bit of the same address 0. The input data at address 3 also includes many “0”s. Therefore, the data of address 3 is inverted, and flag information “1” is written. The input data at addresses 1 and 2 includes more “1”s than “0”s. Therefore, the data is not inverted, and flag information “0” is written. With regards to the written data, only the data at an address whose flag signal is “1” is inverted again in a reading mode to be eventually read out as a data output signal.

There is provided a multi-port memory device having a serial I/O interface, which is capable of providing an operation test without any collision with an internal command/address generation path through a limited external pin. The multi-port memory device includes a plurality of ports supporting a serial I/O interface, and the plurality of ports includes a transmission pad and a reception pad. The multi-port memory device includes: a memory core; a control block for generating an internal command signal, an internal address and a control signal, which correspond to the command and are necessary for an operation of the memory core, using commands and addresses inputted to the plurality of ports in a packet form; and a mode selection block for combining signals applied to a plurality of mode selection pads and generating a test mode flag signal, in which I/O data assigned to the transmission pad and the reception pad in a test mode in response to the test mode flag signal are exchanged with the memory core through the ports. Also, the command, the address and the control signal assigned to the transmission pad and the reception pad in the test mode are bypassed at the control block and provided to the memory core.

A system for detecting an initialization flag signal and distinguishing it from a normal flag signal having half the duration of the initialization flag signal. The initialization flag detection system may be included in the command buffer of a packetized DRAM that is used in a computer system. In one embodiment, the initialization flag detection system includes a pair of shift registers receiving the flag signal at their respective data inputs. One of the shift registers is clocked by a signal corresponding to an externally applied to command clock signal, while the other shift register is clocked by a quadrature clock signal. Together, the shift registers store a number of samples taken over a duration that is longer than the duration of the normal flag signal. The outputs of the shift registers are applied to a logic circuit, such as a NAND gate, that generates an initialization signal when all of the samples stored in the shift registers correspond to the logic levels of the flag signal. In another embodiment, the initialization flag detection system includes a plurality of latches receiving the flag signals at their data inputs. The latches are clocked by respective strobe signals corresponding to the command clock signal, but having phases that differ from each other. The outputs of the latches are applied to a logic circuit, such as a NAND) gate. Finally, in another embodiment of the invention, the bits of the command packet are sampled along with the flag signal and compared to the samples of the flag signal to detect when a command packet having a predetermined pattern does not correspond to a flag signal having a predetermined pattern.

An oscillator controller, has a phase frequency detector that compares a reference signal and a frequency-divided signal and outputs a phase difference signal; a charge pump that outputs a phase error signal according to the phase difference signal output from said phase frequency detector; a loop filter that filters the phase error signal output from said charge pump and outputs an oscillation frequency controlling voltage; a voltage-controlled oscillator that has an LC resonator having a coil, a variable capacitor connected to the opposite ends of the coil at the opposite ends thereof, and a capacitor connected in series with a switch between the opposite ends of said variable capacitor, the oscillation frequency of the voltage-controlled oscillator being controlled through adjustment of the capacitance value of said variable capacitor by said oscillation frequency controlling voltage; a frequency divider that divides the frequency of the output of said voltage-controlled oscillator and outputs said frequency-divided signal; a first counter that counts the number of waves of said reference signal to a desired number and outputs a first flag signal; a second counter that counts the number of waves of said frequency-divided signal to said desired number and outputs a second flag signal; a first comparator that compares said first flag signal and said second flag signal and outputs a frequency comparison signal; and a control circuit that controls said voltage-controlled oscillator, said first counter, said second counter and said frequency divider by outputting signals thereto.

Enhanced directional prediction apparatus and methods are taught which are based on edge-based adaptive directional estimation, for providing an improved prediction direction for intra prediction within a coding device. Image gradient vectors are obtained for pixels in the neighborhood of the current block, and edge directions determined. Candidate edge directions are processed to derive a dominant edge direction in response to defining an objective function as a summation of projections to a candidate direction and computing suggested direction of each neighboring pixel. The dominant edge direction may be utilized for the prediction direction, such as in response to a detection mode flag signaled to the decoder, or modified by an angular adjustment, which can be communicated to a decoder.

A system and method is disclosed that provides a thermal shutdown circuit that generates a plurality of temperature warning flag signals. Each temperature warning flag signal represents a different temperature. The thermal shutdown circuit comprises a plurality of inverter circuits in which each inverter circuit has a different temperature turn-on threshold. A temperature to binary code converter receives the temperature warning flag signals from the inverter circuits and generates a plurality of binary coded signals that represent a temperature that is detected by the thermal shutdown circuit. A host controller unit uses the temperature information from the binary coded signals to shut down subsystems in advance of an abrupt thermal shutdown of a system.

According to the present invention, there is provided a semiconductor integrated circuit having: a BIST circuit including, a data generator which generates and outputs write data to be supplied to a memory, an address generator which generates and outputs an address signal to be supplied to the memory, a control signal generator which generates and outputs a control signal for controlling the memory, a result analyzer which receives a flag signal, analyzes a result of a BIST, and outputs a BIST result signal, a BIST controller which controls operations of the data generator, the address generator, the control signal generator, and the result analyzer, and outputs a BIST state signal indicating a state of the BIST, and a diagnostic data storage circuit including a first capture register which captures and outputs, in accordance with a first clock, a latest address signal and the BIST state signal output from the BIST controller while no flag signal is supplied, and maintains outputs when the flag signal is supplied, a storage register which receive and stores the outputs from the first capture register in accordance with a second clock lower in speed than the first clock while no shift enable signal is supplied, thereby storing the address signal and the BIST signal corresponding to the supply timing of the flag signal, and outputs the stored contents outside by shifting them when the shift enable signal is supplied, and flag suppressing means for comparing the outputs from the first capture register with the stored contents of the storage register, and outputting a flag suppression signal, after the flag signal is supplied, until the latest address signal and the BIST state signal output from the first capture register match the address signal and the BIST control signal stored in the storage register; and a memory collar including, a memory cell which performs a write operation by receiving the write data, the address signal, and the control signal, and reads out and outputs the written data, in accordance with the first clock, a second capture register which captures latest data output from the memory cell while neither the shift enable signal nor the flag signal is supplied, maintains held contents when the flag signal is supplied, and outputs held contents outside by shifting the held contents when the shift enable signal is supplied, a comparator which compares the output from the second capture register with an expected value, and outputs a comparison result signal meaning failure detection if the output and the expected value do not match, and a flag register which outputs the flag signal on the basis of the comparison result signal while no flag suppression signal is supplied, and suppresses the output of the flag signal when the flag suppression signal is supplied

A continuous bi-directional file-play-record voice and video quality tester system (“CFPR-VVQT”) for measuring the quality of voice or video communication links from a customer premises equipment (“CPE”) through a Network under Test to a voice and video quality tester (“VVQT”). The start and end of a set of quality testing sample signals are determined by a start flag signal and an end flag signal, respectively, generated by the CFPR-VVQT. The flag signals may be triple tone modulation frequency (“TTMF”) tones. The CFPR-VVQT will measure the quality testing sample signals, determine a signal quality test result, and then transmit the test results back through Network under Test to the originating VVQT.

A system and method for controlling the electrical power consumption of an accessory device. A power transmission unit is adapted to generate electrical power. The system comprises a first controller, a current sensor and a second controller. The first controller is adapted to control the operation of the accessory device. The current sensor is configured to measure an amount of current being charged and discharged to and from the battery and generate a signal that corresponds to the measured amount of current charged and discharged to and from the battery. The second controller is configured to receive the signal from the current sensor and generate flag signal in response to detecting that current is being charged to the battery. The first controller is further adapted to control the accessory device to consume increased power from the electrical power generated by the power transmission unit in response to the flag signal.

A communication system, network node, and communication port architecture are provided for transporting data across a ring network. If a network node detects a signal failure, the communication port of the network node configures itself as timing master and communicates a shutdown command to the other network nodes. In addition, the communication port sets an internal flag signaling this “signal off” event. All other network nodes, which receive the shutdown flag, do not set this internal status, and instead, save a status of “no fault saved.” Accordingly, it can be easily determined where the loss of signal occurred.

Various embodiments of the present invention relates to systems, devices and methods of detecting tampering and preventing unauthorized access by incorporating programmability and randomness into a process of coupling, driving and sensing conductive wires that are arranged above sensitive areas in a secured system. Such a tampering detection system comprises a security mesh network, a random number generator, a security controller and a security monitor. The security mesh network includes a plurality of security elements made from the conductive wires. The security controller selects a subset of security elements, forms a security array, and generates a driving stimulus. The security monitor selects a SENSE node, monitors an output at the SENSE node, and generates a flag signal indicating the presence of a tampering attempt. Programmability and randomness are introduced to at least one of the system parameters including array configuration, driving stimulus, SENSE node, and detection mode via random numbers.

A semiconductor integrated circuit includes a data bus inversion (DBI) flag generating unit to generate DBI flag signals using a plurality of output data sets, a data inverting unit to invert the plurality of output data sets according to the DBI flag signals and transmit the plurality of output data sets through global transmission lines, and a plurality of data output units to output the plurality of output data sets, which are transmitted through the global transmission lines by pads.

A method, apparatus, article of manufacture, and a memory structure for signaling extension functions used in decoding a sequence comprising a plurality of pictures, each picture processed at least in part according to a picture parameter set is disclosed. In one embodiment, the method comprises reading a first extension flag signaling a first extension function in the processing of the sequence and determining if the first extension flag has a first value. Further, the method reads a second extension flag signaling a second extension function in the processing of the sequence and performs the second extension function according to the read second extension flag only if the first extension flag has a first value.

A FIFO memory device includes a write address generating means generating a write address in response to a write clock signal and a read address generating means generating a read address in response to a read clock signal. A memory cell array includes a plurality of memory cells arranged between a plurality of write and read word lines and a plurality of write and read bit lines, the memory cell array storing write data in response to the write address and outputting read data in response to the read address. A flag signal generating means compares a next write address with a current read address to generate a full flag signal in response to the write clock signal when the next write address and the current read address are equal, and compares a current write address with a next read address to generate an empty flag signal in response to the read clock signal when the current write address and the next read address are equal.