283 results about "Flag signals" patented technology

The invention discloses a time sequence control circuit of display equipment and the display equipment. The time sequence control circuit of the display equipment comprises a frequency detection circuit, a cache circuit and a clock generation circuit, wherein the frequency detection circuit is configured to perform frequency detection on a synchronizing signal corresponding to image data sent by the image processor to obtain a frequency marking signal, and the frequency marking signal represents the frame rate of the image data; the cache circuit is configured to cache image data; the clock generation circuit is coupled to the frequency detection circuit and is configured to generate a target pixel clock according to the frequency flag signal, and the target pixel clock is used for enabling the display panel to display the image data according to the refresh rate corresponding to the target pixel clock. By means of the mode, the frame rate of the image data can be dynamically detected, then the refresh rate of the display panel is dynamically updated / switched, the power consumption of the time sequence control circuit is reduced, and matching of the frame rate and the refresh rate is achieved.

The embodiment of the invention provides a delay measurement circuit and a memory. The delay measurement circuit is applied to the delay phase-locked loop and comprises a loop mark generation circuit which is electrically connected with a loop of the delay phase-locked loop and is configured to generate a loop mark signal and input the loop mark signal to the loop of the delay phase-locked loop when loop delay measurement is carried out on the delay phase-locked loop; after the loop mark signal circulates M times in the loop of the delay phase-locked loop, a measurement ending signal is generated, a target pulse signal is generated, and the effective pulse width of the target pulse signal is equal to M times of the loop delay; wherein M is an even number greater than 1; the counting circuit is electrically connected with the loop mark generation circuit and is configured to receive a frequency division clock signal, and the effective pulse width of the target pulse signal is timed by using the frequency division clock signal to obtain a timing result; and carrying out preset processing on the timing result to obtain a loop delay measurement result of the delay-locked loop. The embodiment of the invention is at least beneficial to increasing the margin value of the delay measurement circuit and improving the accuracy of loop delay measurement.

The invention relates to the technical field of integrated circuits, and discloses a clock synchronization method of a field programmable system-on-chip. The field programmable system-on-chip comprises a processor system and programmable logic. The clock synchronization method comprises the following steps: the processor system generates a timestamp by using a local timestamp generation module; the processor system carries out frequency division on the timestamp to obtain a timestamp marking signal; the processor system downsamples the timestamp using the timestamp flag signal; the processor system sends the timestamp marking signal and the downsampled timestamp to the programmable logic; the programmable logic generates a local clock; the programmable logic adopts a local clock to sample the timestamp marking signal; the programmable logic device adopts the sampled timestamp marking signal to sample the downsampled timestamp; the programmable logic uses the sampled timestamps. According to the invention, the problem of complex timestamp synchronization can be solved, and the precision of timestamp data is improved.

Provided are a storage system, a memory chip, and an error check and scrub method. The storage system includes a memory controller and a memory chip. The memory chip performs an error check and scrub ECS operation on a memory array; and sends a generated ECS finish flag signal to the memory controller after a current ECS operation is completed. The memory controller receives the ECS finish flag signal, and sends a generated ECS start flag signal to the memory chip based on the ECS finish flag signal, so that the memory chip enters a new ECS operation cycle.

The present disclosure provides a memory device and a ZQ calibration method. The memory device includes: two calibration resistor interfaces connected to a same ZQ calibration resistor; a first master chip, a plurality of first slave chips cascaded together, a second master chip, and a plurality of second slave chips cascaded together that are all connected to the ZQ calibration resistor, where first transmission terminals and second transmission terminals are configured to transmit a ZQ flag signal; and an identification module configured to identify a priority calibration chip and a delay calibration chip, and identify the slave chip cascaded with the priority calibration chip as a primary slave chip and the slave chip cascaded with the delay calibration chip as a secondary slave chip.

The embodiment of the present disclosure relates to the field of semiconductor circuit design, in particular to a memory device and a ZQ calibration method, comprising: two calibration resistance interfaces connected with the same ZQ calibration resistance; a first master chip, a first slave chip, a second master chip and a second slave chip commonly connected to the ZQ calibration resistance; in the command mode, a first signal receiver is used for receiving a ZQ calibration command, a second signal receiver is used for receiving and delaying the ZQ calibration command, the first master chip and the second master chip start calibration based on the ZQ calibration command, and the first master chip and the second master chip send a ZQ flag signal through a second transmission end after completing the calibration; a third signal receiver is used for receiving the ZQ flag signal through a first transmission end, the first slave chip and the second slave chip start calibration based on the ZQ flag signal, and the first slave chip and the second slave chip send the ZQ flag signal through the second transmission end after completing the calibration, and the embodiment of the present disclosure is used for realizing theoretically unlimited number of multi-chip sharing ZQ calibration resistance.

The invention discloses a successive approximation-pipeline hybrid analog-to-digital converter and a time sequence control method. The successive approximation-pipeline hybrid analog-to-digital converter comprises a first-stage analog-to-digital converter, a residual amplifier, a second-stage analog-to-digital converter and a sequential circuit module, the sequential circuit module is used for sequentially acquiring a sampling clock signal and a first mark signal quantized by the first-stage analog-to-digital converter from the sequential output end of the first-stage analog-to-digital converter, and acquiring a second mark signal quantized by the second-stage analog-to-digital converter from the sequential output end of the second-stage analog-to-digital converter; an amplification clock signal is generated according to the sampling clock signal, the first mark signal and the second mark signal, and the amplification clock signal is output to a time sequence control end of the residual amplifier; and the residual amplifier is used for performing residual amplification according to the amplified clock signal. According to the invention, the error rate of the successive approximation-pipeline hybrid analog-to-digital converter is reduced, and the linearity can be improved.

Provided are a control circuit, a control method, and a semiconductor memory. The control circuit includes a timing control module and a command control module. An output terminal of the timing control module is connected to an input terminal of the command control module. The timing control module is configured to receive a first clock signal, perform counting based on the first clock signal, generate an error check and scrub (ECS) flag signal, and send the ECS flag signal to the command control module. The ECS flag signal is in a valid state when a counting value meets a preset condition. The command control module is configured to receive the ECS flag signal, obtain a refresh command signal when the ECS flag signal is in the valid state, and generate an ECS command signal based on the refresh command signal.

The invention provides a test method of a switch and electronic equipment, which can be applied to the technical field of switches. The method comprises the steps that under the condition that a first interface of a mainboard and a second interface of an interface board are in a connected state, a first controller arranged on the mainboard writes a preset value into a first register of a physical layer device arranged on the interface board through a management data input and output interface, so that the physical layer device is set to be in a loopback mode, reading a first flag bit signal from a second register of the physical layer device; in response to the fact that the first flag bit signal represents that the loopback mode of the physical layer device is successfully set, the first controller generates a preset diagnosis signal and sends the preset diagnosis signal to the physical layer device; in response to the received returned preset diagnosis signal, a test result is obtained according to the signal integrity of the returned preset diagnosis signal, and the test result indicates the connection state between the mainboard and the interface board.

An aging monitoring circuit of a semiconductor memory device includes a threshold voltage sensing part including an aging monitoring transistor, enabled in response to activation of an aging monitoring signal, and generating a sensing threshold signal, a level of the sensing threshold signal depending on a threshold voltage of the aging monitoring transistor, a reference threshold storage part receiving the sensing threshold signal generated in response to activation of a reference sensing signal and storing a reference threshold voltage, a level of the reference threshold voltage depending on the level of the sensing threshold signal, and a level comparing part enabled in response to the activation of the aging monitoring signal and generating an aging flag signal, a logic state of the aging flag signal depending on a comparison result between the level of the sensing threshold signal and the level of the reference threshold voltage.

The invention relates to a DUT test result processing method, an error memory, a digital board card and a test machine, the method comprises the following steps: capturing comparison data sampled based on N signal lines, the comparison data corresponding to each signal line comprising leading edge comparison data and trailing edge comparison data; wherein N is a natural number greater than 0; screening the comparison data corresponding to the N signal lines to extract error data and addresses of the error data; comparing the addresses of the error data, and generating a division mark signal according to an address comparison result and the number N of the signal lines; splicing the error data, the address of the error data and the division mark signal, and storing the spliced data into a first storage unit; sending the error data and the address of the error data in the first storage unit to a second storage unit in a split-beat manner according to the split-beat mark signal; the issuing storage time of the error data is saved, and the processing efficiency of the DUT test result is improved.

A storage device including: a controller configured to be connected to an external host through an interface; a plurality of memory devices configured to store data; and a power management device configured to output an internal power voltage for an operation of the plurality of memory devices using an external power voltage received through the interface and having a flag signal pad for receiving a flag signal from the controller when the controller fails to recognize at least one of the plurality of memory devices, wherein, when the flag signal is received, the power management device changes a slope of the internal power voltage, and supplies the internal power voltage having the changed slope to the plurality of memory devices.

The invention relates to a power-off detection circuit and a power-on and power-off indication circuit. The power-off detection circuit is used for generating a power-off marking signal when the power supply voltage is in a power-off state, the on resistance of the variable resistance unit is increased along with the reduction of the power supply voltage in the power-off state so as to increase the voltage of the first node, and the current in the mirror image branch can be increased along with the increase of the voltage of the first node so as to increase the voltage of the second node. According to the power-down mark output module, when the voltage of the second node is lower than a set value, an output power-down mark signal is converted from a first level to a second level, that is, a reliable power-down mark signal is formed, and generation of the power-down mark signal is irrelevant to whether the chip is in a low-power-consumption mode or not. Therefore, the chip can be powered off stably and reliably, and related circuits can be controlled or reset by using the power-off marking signal. The power-on and power-off indicating circuit comprises the power-off detection circuit.

Methods, apparatus, and non-transitory computer-readable storage media for video encoding and compression employing high precision intra prediction techniques are provided. In one method, a decoder obtains a first control flag signaled on a specified level, the specified level comprising one of the following levels: a transform block (TB) level, a coding block (CB) level, a slice level, a picture level, or a sequence level, where the first control flag indicates whether to enable a decode-end high precision intra mode derivation (DHI) mode; in response to determining that the first control flag is enabled, the decoder acquires a second flag indicating whether to use DHI of the DHI mode on the specified level; and in response to determining to use the DHI mode, the decoder derives a high precision intra mode using a predefined method.

Embodiments of the present disclosure provide a control circuit, a control method, and a memory. The control circuit includes: a flag signal generation module, configured to generate a command / address inversion flag signal based on a command / address control signal and an initial inversion flag signal; an input processing module, configured to generate a first intermediate command / address signal based on the command / address control signal and an initial command / address signal; and a logic decoding module, configured to: receive the first intermediate command / address signal and the command / address inversion flag signal, and generate a power down mode entry signal or a power down mode exit signal based on the command / address inversion flag signal and the first intermediate command / address signal.

The invention provides an SAR sidelobe signal reconnaissance method and system based on an FPGA. The method comprises the following steps: based on a block digital baseband signal, respectively carrying out frequency modulation slope estimation and local center frequency estimation processing on a target digital baseband signal by adopting short-time Fourier transform, binarization processing, parallel Hough transform and a K-Means clustering method, and correspondingly obtaining an approximate frequency modulation slope and an approximate local center frequency; performing matched filtering and CFAR detection processing on the target digital baseband signal based on the approximate frequency modulation slope and the approximate local center frequency to obtain a target preliminary judgment result; when the target preliminary judgment result is a high flag bit signal, performing iterative search on the approximate frequency modulation slope by adopting a matched filtering method and a one-dimensional search method to obtain a final frequency modulation slope; and obtaining the pulse repetition period of the target by using the final frequency modulation slope and the approximate local center frequency. The real-time processing capability is improved, and the reconnaissance precision is improved.

The present disclosure provides an error checking circuit, comprising: a first generation circuit for generating a read command; and the control circuit is used for reading conventional data in the storage array based on the read command, generating corresponding second verification data based on the conventional data, comparing the second verification data with initial verification data corresponding to the conventional data, and if the second verification data is different from the initial verification data, sending the second verification data to the storage array. If yes, generating an error flag signal of the first state; the second generation circuit is used for receiving the error flag signal and generating a write command based on the error flag signal in the first state; the control circuit is further used for replacing the initial verification data with the second verification data based on the write command.

A driving controller and a display device including the driving controller are provided. The driving controller includes: an image conversion circuit configured to convert an image signal into an image data signal including valid data and blanking data; a still image determination circuit configured to output a flag signal of a valid level when the image signal is a still image; an operation mode determination circuit configured to output an operation mode signal indicating a low frequency mode when the flag signal is at a valid level, and configured to output an operation mode signal indicating an image switching mode when the flag signal changes between a valid level and an invalid level; and a blanking voltage determination circuit configured to output a blanking voltage signal corresponding to a first gray scale during the low frequency mode, and to output a blanking voltage signal corresponding to a second gray scale during the image switching mode, wherein the blanking data corresponds to the blanking voltage signal.

The embodiment of the present disclosure relates to the field of semiconductor circuit design, in particular to a memory device and a ZQ calibration method, comprising: two calibration resistance interfaces connected with the same ZQ calibration resistance; a first master chip, a plurality of cascaded first slave chips, a second master chip and a plurality of cascaded second slave chips connected with the ZQ calibration resistance, and a first transmission end and a second transmission end used for transmitting a ZQ flag signal; a recognition module used for recognizing a priority calibration chip, a delay calibration chip, a master-slave chip cascaded with the priority calibration chip, and a secondary slave chip cascaded with the delay calibration chip; in a command mode, the priority calibration chip starts calibration based on a ZQ calibration command, the delay calibration chip starts calibration based on a delayed ZQ calibration command, and after calibration is completed, the ZQ flag signal is sent through the second transmission end; and the master-slave chip and the secondary slave chip start calibration based on the ZQ flag signal, so as to realize theoretically unlimited number of multi-chip sharing the ZQ calibration resistance.

The present disclosure provides a voltage generating circuit and a memory. The voltage generating circuit includes: a voltage output module configured to receive a reference voltage, generate a first output voltage, and provide the first output voltage to a power supply node, where the power supply node is connected to a load to supply power to the load; a voltage stabilizing module configured to receive the reference voltage and generate and output a control signal; and a compensation module configured to receive a power voltage, a flag signal and the control signal, be turned on in response to the flag signal, and configured to provide a second output voltage to the power supply node in response to a voltage value of the control signal, such that a voltage of the power supply node is recovered to the first output voltage.

A system for signaling extension functions used in decoding a sequence including a plurality of pictures, each picture processed at least in part according to a picture parameter set is disclosed. An extension presence signaling flag is read and used to determine whether flags signaling the performance of extension functions are to be read. The flags are only read if indicated by the extension presence signaling flag.

The invention provides a traffic shaping method and device, a medium and an electronic terminal. The traffic shaping method comprises the following steps: acquiring a queue request signal; based on a traffic shaping mode of a queue in a port in the vehicle-mounted system, a counter corresponding to the traffic shaping mode is allocated to the queue, the counter is a credit counter or a token counter, and the counter supports deficit and can store the maximum packet length supported by a plurality of vehicle-mounted systems; and based on the counter, traffic shaping is performed on a request queue associated with the queue request signal, and a credit increment or a token bucket increment of the request queue is increased once every a fixed time period through a marking signal. According to the traffic shaping method, traffic shaping is carried out on the basis of the counter, so that the traffic shaping precision can be improved. And the traffic shaping method based on the credit and the token is supported in the vehicle-mounted system, so that the traffic shaping of the vehicle-mounted system is more flexible.

Provided are a control circuit, a control method, and a memory. The control circuit includes: a flag signal generation circuit, configured to generate a command / address inversion flag signal based on a command / address control signal and an initial inversion flag signal; an input processing circuit, configured to generate a first intermediate command / address signal based on the command / address control signal and an initial command / address signal; and a logic decoding circuit, configured to: receive the first intermediate command / address signal and the command / address inversion flag signal, and generate a power down mode entry signal or a power down mode exit signal based on the command / address inversion flag signal and the first intermediate command / address signal.

This application provides a high-voltage maintenance method, system, and product for OTA upgrades. The method includes: applying to a takeover controller, wherein the takeover controller is equipped with a high-voltage redundancy control program; the method includes: responding to an upgrade flag signal indicating that a target domain controller is performing an OTA upgrade, and, if it can receive a high-voltage switch signal, sending a high-voltage takeover ready signal to the target domain controller within a first duration; if it is determined that the target domain controller is not performing high-voltage control, performing high-voltage control on the vehicle according to the received high-voltage switch signal; if it is determined that the target domain controller stops sending high-voltage control commands within a second duration, sending a high-voltage control command within a third duration to take over the high-voltage control of the vehicle; and, while taking over the high-voltage control of the vehicle, continuously sending a high-voltage takeover status signal to the target domain controller to control the target domain controller to perform an OTA upgrade. The aim is to maintain high voltage on the vehicle during an OTA upgrade of the domain controller.

A temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

The present invention discloses a transmission detection circuit based on the processing of detection mark signals of a transceiver component. By setting a detection control terminal, a transmission signal source, an FPGA logic control circuit, a DAC module and a radio frequency channel, the detection control terminal is used to provide a transmission detection control signal for the FPGA logic control circuit and the radio frequency channel, and the transmission signal source is used to provide a signal source for transmission detection for the FPGA logic control circuit and the DAC module; then, the radio frequency channel detects and outputs the transmission signal according to the received transmission detection control signal, and at the same time, feeds back the detection mark signal to the FPGA logic control circuit when the radio frequency is output; finally, the FPGA logic control circuit is used to output the detection result according to the received transmission detection control signal, the signal source and the detection mark signal. The present invention is equipped with a detection control device, a DAC module and an FPGA logic control circuit on the basis of the radio frequency channel. It aims to solve the technical problem that the judgment accuracy of the successful transmission of the signal on the transceiver component is not high in the prior art.

A memory circuit includes a compute in-memory (CIM) array. The CIM array includes a memory cell array configured to store a first set of data. The first set of data including a first set of weights or a second set of data. The first set of data being exponent portions of corresponding floating point numbers. The second set of data being a compressed version of the first set of weights. The first set of weights having a first data length, and the second set of data having a second data length less than the first data length. The CIM array further includes a decoder coupled to the memory cell array, and being configured to generate a first set of output signals in response to a first set of input signals, the first set of data and a flag signal.

An electronic system includes a controller configured to output a command, external row addresses, and external column addresses, receive a flag signal, and output the flag signal to a host. The electronic system also includes a semiconductor device configured to correct an error of internal data output from a memory cell selected based on the command, the external row addresses, and the external column addresses to output error-corrected internal data as data, and output the flag signal that is enabled when correcting the error in the internal data a set number of times.

The invention provides an attitude control energy optimization method for a spacecraft. The attitude control energy optimization method comprises the following steps: firstly, obtaining a smoothed attitude angle instruction and an attitude angle rate instruction by using a tracking differentiator; estimating impact disturbance through a nonlinear extended state observer; forming an impact disturbance sign signal according to the estimated value; obtaining a state error, establishing an attitude control law under a non-interference condition and an attitude control law under impact disturbance, and obtaining a corresponding control quantity and a sliding mode surface; according to the state error and the two attitude control laws, the switching compensation control quantity is calculated, the attitude control law under the impact disturbance containing integral switching compensation control is designed, and the smoothed control quantity under the impact disturbance is obtained; according to the impact disturbance mark signal, the control quantity under the interference-free condition or the control quantity under the smooth impact disturbance is selected and sent to the attitude control engine. The method effectively solves the energy optimization problem of the direct force control system when the parameters of the control system change drastically under large impact disturbance.