968 results about "Multi port" patented technology

The invention relates to the technical field of computer network communication, and relates to a reconfigurable router architecture based on buffer sharing and a dynamic routing method. The router architecture comprises a demultiplexer used for distributing data packets to centralized buffer areas of other ports according to port load states; the virtual channel distribution module is configured to determine an output port of the data packet according to a routing algorithm and generate a corresponding virtual channel ID; the centralized buffer area supports multi-port sharing and is divided into a plurality of logic sub-channels according to virtual channel IDs, and each sub-channel manages a data packet queue through a head pointer and a tail pointer; the credit management module is used for monitoring the idle capacity of the centralized buffer area and transmitting congestion information through a reserved bit of a data packet; and the congestion register dynamically records the congestion state of the neighbor node through the congestion information table. According to the invention, the problems of unbalanced load, low utilization rate of a buffer area and high congestion control cost of a traditional router are solved.

The embodiment of the invention discloses a battery equalization management method and device based on port multiplexing. The method comprises the following steps: calculating a state-of-charge value of each single battery according to a sampling value of an electrical basic physical quantity; calculating a difference value between the state-of-charge value of each single battery and an average state-of-charge value of the battery pack to which the single battery belongs; determining the single batteries of which the difference values exceed a preset equalization threshold value as unbalanced batteries; and formulating an equalization sequence of the unbalanced batteries, and conducting the selection switch and the multiplexing switch according to the equalization sequence, so that the unbalanced batteries are connected with a primary side port of the multi-port converter for energy adjustment. According to the embodiment of the invention, the hardware complexity and the system cost are reduced by greatly reducing the usage amount of switch components. Meanwhile, the framework also improves the equalization efficiency and flexibility of the retired battery pack.

A power converter configured to be connected to three or more voltage parts, includes three or more power-conversion circuitries to be connected to respective ones of the three or more voltage parts, and a multi-port transformer connected to the three or more power-conversion circuitries at respectively different ports. The three or more voltage parts include a vehicle drive battery and a plurality of alternating-current (AC) voltage parts. Each of the plurality of AC voltage parts is configured to provide at least one of power input to a multi-port transformer side and power output from the multi-port transformer side.

A modular multiport converter system includes a plurality of distributed controllers, associated with different ports of the system that are able to synchronize to ensure that power drawn from the system is equal to power supplied to the system with precise timing. The distributed controllers are able to receive a clock signal from a leader controller, or from a vice leader controller in the event that leader controller is unable to function.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a chiplet-based multi-chip module (MCM) is disclosed. The chiplet-based MCM includes a package substrate and a first processing integrated circuit (IC) chiplet disposed on the package substrate. A second processing IC chiplet is disposed on the package substrate. At least one first row multi-port memory chiplet is disposed on the package substrate and coupled between the first processing IC chiplet and the second IC processing chiplet. Data transfers between the first processing IC chiplet and a destination IC chiplet are routed through the at least one first row multi-port memory chiplet.

The invention belongs to the technical field of intelligent substations, and particularly relates to an intelligent nuclear phase method and system for a substation. According to the method, a dynamic priority evaluation model is constructed, multi-source data of four kinds of basic factors including voltage phase difference, environment temperature and humidity, equipment vibration and historical errors are synthesized, and a fuzzy comprehensive evaluation method is utilized to calculate weights and dynamically sort the weights; a multi-port phase scattering model is constructed based on transformer substation topology, impedance mismatch points are analyzed by means of a Smith chart, and dual-stage optimization is implemented; constructing a three-layer decision input set according to the optimization model, designing a fuzzy logic driven adaptive rule engine, dynamically outputting a working condition level and matching a nuclear phase strategy; multi-dimensional quality evaluation, dynamic updating of factor weights and optimization of fuzzy model parameters are carried out by monitoring indexes such as reflection coefficients in real time, abnormal mode recognition and compensation strategy solidification are realized by fusing LSTM and a graph neural network, a self-evolution closed-loop system is formed, and finally, crossing of a nuclear phase process from accurate matching to autonomous evolution is realized.

The invention relates to the field of transformer control, and discloses a solid-state distribution transformer control system and method for improving access of a distributed power supply, which are used for solving the problem that original controller parameters are not representative due to access change of the distributed power supply when the solid-state distribution transformer is controlled. The method comprises the following steps: constructing a solid-state distribution transformer with a multi-port power regulation capability, setting initial control parameters, obtaining equivalent impedance influenced data, evaluating according to the equivalent impedance influenced data to obtain an equivalent impedance change index, judging whether the equivalent impedance is changed according to the equivalent impedance change index, and if the equivalent impedance is judged to be changed, judging whether the equivalent impedance is changed or not. If yes, dynamically correcting the initial control parameter according to the equivalent impedance change index to obtain an actual control parameter, and adjusting the output of the solid-state transformer according to the actual control parameter, thereby effectively improving the accuracy of transformer control and the reliability of energy supply.

The invention relates to the field of chip testing, in particular to a chip signal integrity test analysis method, device and equipment and a storage medium. The method comprises the following steps: extracting a chip performance index based on a chip design requirement document; performing saturation frequency excitation setting based on the chip performance index to generate an excitation test signal; performing a multi-port signal excitation test and parallel signal sampling based on the excitation test signal to generate a high signal-to-noise ratio response data set; obtaining a chip layout design file; performing chip communication link analysis on the chip layout design file, and constructing communication line layout data; performing signal mapping and waveform quality evaluation on the communication line layout data based on the high signal-to-noise ratio response data set to obtain a node signal distortion rate; and performing signal integrity quantization and theoretical signal integrity score comparison based on the node signal distortion rate, and marking a fault node. According to the invention, the chip testing efficiency is improved, and the signal abnormal part of the chip is accurately and efficiently detected.

A different network address is assigned to each port of a first device and a second device that are configured to exchange traffic over a multi-path connection of a transport layer protocol. When a timeout is detected by the first device indicating that a packet sent to a first network address assigned to a first port of the second device was not received, the first device can regenerate the packet with a second network address assigned to a second port of the second device, and send the regenerated packet to the second network address of the second device. The first device can send heartbeat packets to the first port in an exponential backoff manner and, upon receiving a heartbeat acknowledgement from the first port, resume sending the packets to the first port.

The invention provides a railway flexible traction system based on multi-source fusion. The system is composed of a central control unit, a V / v traction transformer unit and a multi-port flexible interconnection unit. The V / v traction transformer unit comprises a first power supply arm, a second power supply arm and a third power supply arm, the input ends of the V / v traction transformer unit are connected with a public power grid, the first and second power supply arms are connected to the multi-port flexible interconnection unit, and the third power supply arm provides passive support for a traction network. The multi-port flexible interconnection unit comprises a two-phase rectification module, a photovoltaic power generation module, an energy storage module and a single-phase inversion module which are commonly connected to a DC bus. The central control unit adjusts the output power of the multi-port flexible interconnection system and the control strategy of the single-phase inversion module in real time so as to realize flexible consumption of new energy and improvement of power supply stability. The system has the advantages of compatibility, cost effectiveness, new energy access and consumption, power supply reliability improvement, electric energy quality optimization, high adaptability and the like, and is suitable for upgrading and reconstruction of newly-built railway lines and existing railway lines.

The invention belongs to the field of PCIe (Peripheral Component Interconnect Express) chips, and relates to a CXL switching chip of a multi-core-grain architecture and a cross-core-grain routing switching method thereof, and a plurality of CXL switching core grains with uniform specifications are packaged and interconnected to form the CXL switching chip; each CXL switching core particle comprises a plurality of ports, each port can be configured to be in a CXL mode and a D2D mode, and the port of each CXL switching core particle at least comprises a physical layer, a CXL link layer, a CXL transaction layer, a D2D routing layer, a bypass and a multipath selection module; the CXL switching chip further comprises a multi-VC on-chip CXL switching network, and the multi-VC on-chip CXL switching network comprises at least one order-preserving switching VC and one out-of-order switching VC. According to the method, CXL switching chips of various specifications can be flexibly constructed, the design complexity and verification difficulty of the large-scale or multi-port CXL switching chips are effectively reduced, and the production yield of the chips is improved.

The invention discloses an offshore wind power collecting and sending-out system and method based on a multi-port multi-frequency alternating current and direct current hybrid integrated platform, and belongs to the field of power transmission and distribution of power systems. The system comprises an intermediate-frequency, power-frequency and low-frequency wind power collection subsystem, an offshore integrated platform, a direct-current sending-out submarine cable, a low-frequency sending-out submarine cable, an onshore converter station and an onshore frequency conversion station. The various wind power collection subsystems respectively collect wind turbine generator group outputs with corresponding frequencies and send the wind turbine generator group outputs to the offshore integrated platform; the offshore integrated platform converts intermediate-frequency, power-frequency and partial low-frequency electric energy into direct current and then transmits the direct current to the onshore converter station through the direct-current sending-out submarine cable, and the converter station converts the direct current into power-frequency alternating current; and after being boosted, the other low-frequency electric energy is sent to a land frequency conversion station through a low-frequency sending-out submarine cable to be converted into power-frequency alternating current, so that efficient collection and grid-connected sending-out of multi-frequency wind power resources are realized. According to the invention, the problem that a plurality of independent platforms need to be built in a complex multi-point grid-connected scene in the prior art can be solved.

A multi-port interface device for connecting multiple computing devices for data and power transfer includes a housing with an internal power source. A processor is electrically coupled to the internal power source. A power input port electrically coupled to the internal power source is designed to receive a power cord. The power cord is electrically couplable to an extrinsic power source to transfer power from the extrinsic power source to the internal power source. A plurality of ports electrically coupled to the processor is inset into the housing. Each port of the plurality of ports is exposed within the housing. The plurality of ports includes a plurality of universal serial bus ports and a memory card port.

A multi-port valve assembly, including a housing, a plurality of ports formed as part of the housing, and a rotor disposed in the housing, the rotor selectively in fluid communication with the ports. A first channel is integrally formed as part of the rotor, and a circumferential wall is part of the first channel, the circumferential wall at least partially surrounding a circular aperture which is also part of the first channel. The multi-port valve assembly also includes a second channel integrally formed as part of the rotor, the second channel fluidically isolated from the first channel, and at least two flow paths formed by the orientation of the rotor relative to the housing and the ports. The rotor is placed in one of a plurality of configurations relative to the ports and the housing such that each of the plurality of configurations includes the flow paths.

Methods related to wireless communication systems and uplink (UL) rank adaptation are provided. A user equipment (UE) receives, from a base station (BS), a configuration indicating a resource associated with a plurality of UL reference signal ports. The UE determines, based on at least one of an overheating status, a throughput, or a latency, a quantity of transmission layers for a transmission. The UE transmits, to the BS, an indication of at least one of (1) one or more UL reference signal ports of the plurality of UL reference signal resources associated with the UL reference signal resource based on the quantity of transmission layers, or (2) a number of UL reference signal ports associated with the multi-port UL reference signal resource based on the quantity of transmission layers.

The invention discloses a load insertion detection circuit, a control method thereof and a multi-port charger, and belongs to the technical field of multi-port charging. The load insertion detection circuit comprises a comparison unit, a first input end is connected with a load access node, a second input end is used for accessing a reference voltage, and the comparison unit outputs a first signal when the voltage of the first input end is greater than the voltage of the second input end; each pull-up circuit comprises a switch and a resistor which are connected in series, the first end of each pull-up circuit is electrically connected with the same power supply voltage node, the second end of each pull-up circuit is electrically connected with the load access node, and the resistance values of the resistors are different; the control circuit is electrically connected with the driving end of each switch and the output end of the comparison unit, the control circuit controls the corresponding switches to be switched on according to the sequence that the resistance values of the resistors are decreased progressively until the comparison unit outputs the first signal, the switching-on state of the switch which is switched on currently is maintained, load insertion detection is carried out, the detection range is enlarged, and the anti-interference performance is improved.

The invention belongs to the technical field of analog integrated circuit design and memory read-write, and provides a multi-valued RRAM read-write circuit with a write-and-read function. The multi-valued RRAM read-write circuit is a multi-port device capable of performing read-write simultaneously, in write operation, a low dropout regulator is utilized to provide voltage for the RRAM circuit and the standard resistance circuit, mirror current is generated, the resistance value of the RRAM is set to be the total resistance of the standard resistance circuit, an operational amplifier is connected into the circuit through a CMOS switch, and feedback is formed to stabilize the voltage at the two ends of the RRAM; and in the read operation, the CMOS switch is used for disconnecting the operational amplifier, and the voltage at the two ends of the RRAM device is directly read. Compared with an existing multi-valued read-write circuit, the multi-valued RRAM read-write circuit has the advantages that write-and-read multi-valued RRAM read-write is realized, and meanwhile, the read-write circuit is not separated, so that the write-in speed is increased, and the area of the read-write circuit is saved.

The invention belongs to the field of electromagnetic field numerical solution, and particularly provides a finite element mesh adaptive method for network parameter analysis of a multi-port microwave device, which comprises the following steps: firstly, establishing a geometric structure of the multi-port microwave device, setting simulation frequency, excitation and boundary conditions, and establishing an electromagnetic simulation model; secondly, performing preliminary division and finite element electromagnetic simulation calculation on a computational domain by adopting a tetrahedral mesh to obtain a numerical solution corresponding to each group of excitation, and synthesizing results based on a posterior error estimation method for posterior error estimation; and finally, according to a posterior error indication grid encryption parameter, carrying out simulation calculation again after encryption, and repeating the process until the solution meets the precision requirement. In conclusion, by combining the characteristics of a finite element algorithm and the characteristics of an error estimation algorithm, in the microwave device network parameter analysis process, multiple sets of excited numerical solutions are comprehensively used for posterior error estimation and grid adaptive encryption indication, so that the analysis precision of network parameters is improved.

The invention relates to the field of mass spectrometry, and describes a mass spectrometer based on multi-electrode coordination of a Jooden well. A multi-port ion source configured for multi-port input of electrons of ionization of gas molecules in a well and ions in an ion source outside the well, the ports being autonomously usable, comprising two external electrodes and four internal electrodes configured to excite periodic movement of ions in the well along an axis of symmetry and to detect signals caused by ions of secondary potential oscillation in the well, wherein ions are introduced into the trap from an external source with a slot, and ion movement is excited by applying an alternating voltage or the like to the electrodes. Or using a slot to introduce ions from an external source into a well in an external electrode, applying a potential to an internal electrode to create an electric field, the size of which is in a quadratic relationship with the coordinates, the electrodes having a specific equipotential surface geometry. Pulsed potentials can be applied to capture ions, multiple external ion sources can be equipped, and if the ion sources are not combined, each can be provided with a separate port. The mass spectrometer is uniquely designed in the aspects of ion input, excitation, detection, ion source configuration and the like.

A calibration method of calibrating a test instrument includes the following: consecutively connecting a set of calibration standards to at least one port and performing a calibration measurement for each calibration standard connected, thereby obtaining a first set of measurement data; determining, based on a multi-port error model and the first set of measurement data, a plurality of error terms of the multi-port error model, wherein at least one of the error terms includes a product of two error parameters; connecting an additional calibration standard to the at least one port; performing a calibration measurement with the additional calibration standard connected, thereby obtaining a second set of measurement data; and determining the two error parameters based on the second set of measurement data. Further, a calibration system is described.

The embodiment of the invention provides a communication method and a related device, the method is applied to a first communication device, and the method comprises the following steps: determining an offload bandwidth proportion of each port of a second communication device; sending first indication information, wherein the first indication information comprises the shunting bandwidth proportion of each port; shunt data from the second communication device is received. And multi-port transmission between the first communication equipment and the second communication equipment is realized. And furthermore, the bandwidth allocation balance of each port of the first communication equipment is realized, and the communication performance is improved.

Various implementations described herein are related to a device having first datapath circuitry with input devices that receive data from a number of write ports and provide first data. The device may have second datapath circuitry with logic gates that receive the first data from the input devices and provide the first data based on a read bitline signal. The device may have third datapath circuitry with output devices that receive the first data from the logic gates and provide second data to a number of read ports. Also, the number of read ports is greater than the number of write ports.

Methods, systems, and devices for wireless communications are described. In some wireless communications systems, a user equipment (UE) and a network entity may utilize multi-port mobility reference signals to assist with spatial based mobility procedures. The UE may receive a reference signal that is associated with multiple antenna ports. The UE may measure a multi-dimensional channel response based on the reference signal. The multi-dimensional channel response may be associated with measured channel metrics corresponding to the multiple antenna ports. The UE may transmit a report that includes a channel measurement vector based on the multi-dimensional channel response. The channel measurement vector may indicate multiple measured channel metrics for one or more dimensions of the multi-dimensional channel response. The network entity may transmit a message that indicates one or more metrics associated with mobility management for the UE based on the report that indicates the channel measurement vector.

The invention provides a method for testing the communication bandwidth of a 10-gigabit network between an FPGA (Field Programmable Gate Array) and a CPU (Central Processing Unit), which is applied to a radar system. The FPGA completes a function of regularly generating data and a function of downlink transmission of the data; the 10-gigabit network exchange board card completes data transmission and sends data to the CPU board card through a 10-gigabit network; and the CPU board card receives the data and calculates the communication bandwidth and the network quality. According to the invention, the limitation of traditional single-port point-to-point transmission or simple multi-port parallel transmission on synchronization, load balancing or protocol overhead is solved, and a solution is provided for how to effectively utilize multiple ports, enable the multiple ports to simultaneously and efficiently work and ensure parallel transmission of data without mutual interference.

The embodiment of the invention provides a CXL host controller, a data transmission method and a computer. The CXL host controller comprises a CXL host bridging module and a CXL multi-port controller, the CXL multi-port controller is connected with a physical link of the CXL equipment and is shared by a plurality of root ports managed by the CXL multi-port controller, and each root port is used for being connected with the corresponding CXL equipment; the plurality of root ports are activated by turns according to a time division multiplexing mechanism, and data transmission is carried out by using a physical link; the CXL host bridging module is used for receiving a processor message in a sending direction, converting the processor message into a CXL message and transmitting the CXL message to the CXL multi-port controller; and the CXL multi-port controller receives the CXL message of the CXL host bridging module in the sending direction, indicates the activated target root port based on the current clock period time division multiplexing signal, transmits a data packet corresponding to the CXL message to the target root port, and transmits the data packet to the CXL equipment through the target root port. According to the CXL host controller, multi-port expansion is realized, and higher compatibility and flexibility are provided for expansion of a CXL network and memory equipment.

The invention provides a multi-port multi-band intermodulation test method and equipment, and the method comprises the following steps: controlling one or more signal sources to respectively generate carrier signals of two different frequency points in respective target frequency bands; combining the carrier signals into a mixed wave signal through a signal cross network, and distributing the mixed wave signal into multiple paths of test signals, so that each path of test signal comprises the mixed wave signal of one frequency band or multiple frequency bands so as to access a signal port of external passive equipment; and polling and collecting reflected signals generated by each path of test signals through a signal collection unit, and generating test data based on the reflected signals. According to the method, intermodulation testing of multiple frequency bands is achieved, multi-frequency-band intermodulation testing can be conducted on multiple external passive devices at the same time, or multi-frequency-band intermodulation testing can be conducted on multiple ports of the external passive devices, and therefore the intermodulation detection efficiency is improved.

The invention discloses a calibration method and a calibration system. A calibration method for calibrating a test instrument comprising at least one port, at least one signal analysis module and at least one signal generator module is described. The at least one signal analysis module and the at least one signal generator module are each connected to the at least one port. The calibration method comprises the steps of: successively connecting a set of calibration standards to at least one port, and performing a calibration measurement for each connected calibration standard, thereby obtaining a first set of measurement data; determining a plurality of error terms of the multi-port error model based on the multi-port error model and the first set of measurement data, where at least one of the error terms includes a product of two error parameters; connecting an additional calibration standard to the at least one port; performing a calibration measurement if the additional calibration standard has been connected, thereby obtaining a second set of measurement data; and determining two error parameters based on the second set of measurement data.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a channel state information (CSI) reporting configuration indicating a plurality of port groups, each port group of the plurality of port groups comprising one or more ports of a plurality of ports associated with a multi-port channel state information-reference signal (CSI-RS) resource for reporting multiple transmission reception point (mTRP) coherent joint transmission (CJT) CSI, and indicating a plurality of codebook subset restrictions (CBSRs) associated with the multi-port CSI-RS resource, each of the plurality of CBSRs associated with a port group of the plurality of port groups. The UE may receive a multi-port CSI-RS communication. The UE may transmit an mTRP CJT CSI report based at least in part on the CSI reporting configuration and the multi-port CSI-RS communication. Numerous other aspects are described.

The invention belongs to the technical field of power system automation, and discloses a power grid equivalence method, system, equipment and medium for preserving the repeated low-voltage crossing characteristic of new energy, so as to solve the problems that the simulation efficiency is low, the analysis time is long, and the repeated low-voltage crossing characteristic of the new energy cannot be accurately preserved. The method comprises the following steps: taking a new energy collection bus as a starting point, and carrying out graded section division on a power transmission line of a power grid; based on the section division result, calculating the sensitivity to the short-circuit ratio of the new energy collection bus after each line in each section is cut off; determining an internal system, an external system and a boundary node connecting the internal system and the external system based on the sensitivity result; carrying out equivalence on an external system through a multi-port Thevenin equivalence method; and determining a final equivalent power grid according to the consistency of the new energy repeated low-voltage penetration condition of the system before and after equivalence under the disconnection fault. According to the method, on the premise of ensuring that the simulation precision reaches the standard, the analysis efficiency of the new energy repeated low-pass characteristics is improved.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.